miegl/b210-k7-fpga
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6f2cbbfd1613e632f76db7f1ecb2d2a2b4e21d8c
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2 Commits
Author SHA1 Message Date
Wade Fife f88b56d9cb fpga: x400: Change AXI XB for DRAM to 512-bit 
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.


Original-commit: 822cd03c8cd686f8b0554774adcbdd3803128bc2
 2022-03-04 18:46:12 -06:00
Wade Fife f5b6a04e5c fpga: x400: Add axi_inter_2x128_512_bd IP 
Original-commit: e88c447a1a890a38ee875c14ab55a713056709b9
 2022-02-07 13:08:11 -07:00