Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.
Original-commit: b0033158a4c520063540881451d8daac91e98714
This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.
This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.
Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927
Wade Fife