Commit Graph
3 Commits
Author SHA1 Message Date
Wade Fife 29ac752be0 fpga: sim: Check for empty packet in clear_unused_bytes
Original-commit: 2615547a82bc4e06ff5fcb79c5c1efed76b058c7
2021-06-17 08:16:59 -05:00
Andrew Moch d5bbce58cb fpga: sim: Update PkgEthernet
Consolidated calcuation of last_tkeep and tkeep_last. Changed error
checking to support unwrinkling tkeep/trailing changes in 100G
etherent and support for testing packet dropping on backup.


Original-commit: 473b0f5abe882ca316a7fe1a59234676940ef26b
2020-07-31 13:22:29 -05:00
Andrew Moch 23be04661f fpga: lib: Add synthesizable AXI4-Stream SV components
Components are connected together with AxiStreamIfc. Some features
include:
  (1) Add bytes to the start of a packet
  (2) Remove bytes from a packet
  (3) Wrappers for some older components
      a.  fifo - buffer but imediately pass a packet
      b.  packet_gate - buffer and hold till end of packet
      c.  width_conv - cross clock domains and change width of axi bus

The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
  - reached_packet_byte - notify when tdata contains a paritcular byte
  - get_packet_byte/get_packet_field - extract a byte or field from axi
  - put_packet_byte/put_packet_field - overwrite a byte or field onto axi


Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
2020-06-25 14:44:04 -05:00