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fpga: x4xx: Refactor MB CPLD code for future devices

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Original-commit: e2a79712a7949ffec88135236c744dc5d8bde217
This commit is contained in:
Javier Valenzuela
2023-05-23 09:05:27 +02:00
committed by Martin Braun
parent e9a6fe4e2e
commit ffdcc016cc
33 changed files with 5895 additions and 14 deletions
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top/x400/cpld/x410/ctrlport_to_jtag.v
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_jtag
//
// Description:
//
// This module wraps a JTAG master and provides a ControlPort slave
// interface.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers
// DEFAULT_PRESCALAR : Default clock divider to use
//
`default_nettype none
module ctrlport_to_jtag #(
parameter BASE_ADDRESS = 0,
parameter DEFAULT_PRESCALAR = 0
) (
//---------------------------------------------------------------------------
// ControlPort Slave
//---------------------------------------------------------------------------
input wire ctrlport_clk,
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status = 0,
output reg [31:0] s_ctrlport_resp_data = 0,
//---------------------------------------------------------------------------
// JTAG Signals
//---------------------------------------------------------------------------
output wire tck,
output wire tdi,
input wire tdo,
output wire tms
);
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "../regmap/jtag_regmap_utils.vh"
//---------------------------------------------------------------------------
// Local Registers
//---------------------------------------------------------------------------
reg [ TX_DATA_SIZE-1:0] tx_data_reg;
reg [ STB_DATA_SIZE-1:0] stb_data_reg;
reg [PRESCALAR_SIZE-1:0] prescalar_reg = DEFAULT_PRESCALAR;
reg [ LENGTH_SIZE-1:0] length_reg;
reg start_reg;
reg soft_rst_stb_reg;
//---------------------------------------------------------------------------
// Readback Signals from JTAG Master
//---------------------------------------------------------------------------
wire [31:0] rd_data;
wire ready;
//---------------------------------------------------------------------------
// Handling of CtrlPort
//---------------------------------------------------------------------------
localparam NUM_ADDRESSES = 32;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
wire soft_rst_requested = (s_ctrlport_req_addr == BASE_ADDRESS + CONTROL) &&
(s_ctrlport_req_data[RESET] == 1'b1);
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
tx_data_reg <= {TX_DATA_SIZE {1'b0}};
stb_data_reg <= {STB_DATA_SIZE {1'b0}};
prescalar_reg <= DEFAULT_PRESCALAR;
length_reg <= {LENGTH_SIZE {1'b0}};
start_reg <= 1'b0;
soft_rst_stb_reg <= 1'b0;
s_ctrlport_resp_ack <= 1'b0;
end else begin
// Request independent default assignments
start_reg <= 1'b0;
soft_rst_stb_reg <= 1'b0; // self-clearing strobe
// Write requests
if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {CTRLPORT_DATA_W{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Process write requests only in case ready is asserted because JTAG
// module requires these values to be stable when it is not ready.
//
// The one exception is when a soft-reset is requested to reset the
// bitq_fsm, in that case that is a valid write.
if (soft_rst_requested) begin
soft_rst_stb_reg <= 1'b1;
end else if (ready) begin
case (s_ctrlport_req_addr)
BASE_ADDRESS + TX_DATA: begin
tx_data_reg <= s_ctrlport_req_data;
end
BASE_ADDRESS + STB_DATA: begin
stb_data_reg <= s_ctrlport_req_data;
end
BASE_ADDRESS + CONTROL: begin
length_reg <= s_ctrlport_req_data[LENGTH_MSB:LENGTH];
prescalar_reg <= s_ctrlport_req_data[PRESCALAR_MSB:PRESCALAR];
// When the RESET bit is high, a soft-reset (i.e. no start strobe)
// must take place, which is handled by the default assignment.
// Otherwise, if the RESET bit is low, a start strobe should be
// issued, triggering a transaction.
start_reg <= (s_ctrlport_req_data[RESET] == 1'b0);
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Error in case ready is not asserted
end else begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
// Read requests
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + RX_DATA: begin
s_ctrlport_resp_data <= rd_data;
end
BASE_ADDRESS + CONTROL: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
s_ctrlport_resp_data[LENGTH_MSB:LENGTH] <= length_reg;
s_ctrlport_resp_data[PRESCALAR_MSB:PRESCALAR] <= prescalar_reg;
s_ctrlport_resp_data[READY] <= ready;
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//---------------------------------------------------------------------------
// JTAG Master
//---------------------------------------------------------------------------
// bitq_fsm reset is asserted by either the ctrlport_rst or the soft-reset
// strobe triggered through software.
wire bitq_resetn = ~(ctrlport_rst | soft_rst_stb_reg);
bitq_fsm #(
.IDLE_VALUE (1'b0)
) jtag_master (
.clk (ctrlport_clk),
.rstn (bitq_resetn),
.prescalar (prescalar_reg),
.bit_clk (tck),
.bit_in (tdo),
.bit_out (tdi),
.bit_stb (tms),
.start (start_reg),
.ready (ready),
.len (length_reg),
.wr_data (tx_data_reg),
.stb_data (stb_data_reg),
.rd_data (rd_data)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="JTAG_REGMAP" readablestrobes="false" markdown="true" generatevhdl="true" ettusguidelines="true">
//
// <group name="JTAG_REGS">
// <info>
// This register map is present for each JTAG module.
//
// Basic operation would be:
//
// - poll @.ready until asserted
// - write / read data
// - write @.CONTROL register along with @.reset deasserted to start a transaction
//
// For resetting the BITQ FSM, simply assert @.reset.
//
// This operation seems a little strange, but it is what the axi_bitq driver
// expects. This behavior has been implemented in previous products.
//
// </info>
//
// <register name="TX_DATA" readable="false" offset="0x00" size="32">
// <info>Data to be transmitted (TDI)</info>
// </register>
//
// <register name="STB_DATA" readable="false" offset="0x04" size="32">
// <info>Data to be transmitted (TMS)</info>
// </register>
//
// <register name="CONTROL" offset="0x08" size="32">
// <info>JTAG module status and control</info>
// <bitfield name="prescalar" range="7..0" initialvalue="true">
// <info>Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.</info>
// </bitfield>
// <bitfield name="length" range="12..8">
// <info>(Number of bits - 1) to be transferred</info>
// </bitfield>
// <bitfield name="reset" readable="false" range="31">
// <info>When asserted ('1') a soft-reset for the bitq FSM is triggered,
// preventing any transactions to take place.
//
// Deassert this bit, along with values for @.prescalar and @.length
// to trigger a new transaction (start strobe).</info>
// </bitfield>
// <bitfield name="ready" writable="false" range="31">
// <info>Bitq FSM is ready for input (no data transmission in progress).</info>
// </bitfield>
// </register>
//
// <register name="RX_DATA" offset="0x0C" writable="false" size="32">
// <info>Received data (TDO)</info>
// </register>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/x410/db_spi_shared_constants.sdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constants for the MB CPLD <-> DB CPLD SPI interface
#
# Delays are rounded to integer values which leave a slack of >1ns on each setup
# and hold path without requirement for adding hold delays (as reported
# by Quartus fitter report).
# The signal might change before the SCLK edge as the internal
# registers are driven by PLL reference clock rather than the SPI clock used
# for the port timing constaints.
set db_cpld_spi_max_out 14.000
set db_cpld_spi_min_out 2.000
set db_cpld_spi_max_in 2.000
set db_cpld_spi_min_in -2.000
top/x400/cpld/x410/mb_cpld.sdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constraints for the x410's motherboard CPLD.
#
#####################################################################
# JTAG to daughterboards
#####################################################################
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in and usage of X410 DB.
# Longest trace | Trace length | Trace delay
# TDI to DB 0 | 7.625 in | 1.296 ns
# --------------------------------------------
# JTAG parameters
# see https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1399899915639
set db_jtag_board_delay 1.296
set db_jtag_setup 3.000
set db_jtag_hold 10.000
set db_jtag_clk_to_out 20.000
set db0_jtag_outputs [get_ports {DB_JTAG_TDI[0] DB_JTAG_TMS[0]}]
set db0_jtag_inputs [get_ports {DB_JTAG_TDO[0]}]
set db1_jtag_outputs [get_ports {DB_JTAG_TDI[1] DB_JTAG_TMS[1]}]
set db1_jtag_inputs [get_ports {DB_JTAG_TDO[1]}]
##### DB 0 #####
# generated jtag clock is at least divided by 4
# max JTAG clock rate = 20 MHz
# source clock rate = 50 MHz
# only even dividers -> minimum value = 4
set db0_jtag_clk_register [get_registers {ctrlport_to_jtag:db0_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}]
create_generated_clock -source $pll_clk_out_pin \
-name db0_jtag_clk $db0_jtag_clk_register \
-divide_by 4
# see White Rabbit DAC for futher explanation
set_false_path -from $db0_jtag_clk_register -to $db0_jtag_clk_register
create_generated_clock \
-source $db0_jtag_clk_register \
-name db0_jtag_out_clk [get_ports {DB_JTAG_TCK[0]}]
set_output_delay -clock db0_jtag_out_clk \
-max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \
$db0_jtag_outputs
set_output_delay -clock db0_jtag_out_clk \
-min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \
$db0_jtag_outputs
# data is driven on CPLD on falling edge, which is 2 clock cycles ahead
# of the latch edge
set_multicycle_path -setup -start -to $db0_jtag_outputs 2
set_multicycle_path -hold -start -to $db0_jtag_outputs 3
# maximum delay accounts for slow clock and data propagation as
# well as clock to out time
set_input_delay -clock_fall -clock db0_jtag_out_clk \
-max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \
$db0_jtag_inputs
# worst-case everything changes immediatelly
set_input_delay -clock_fall -clock db0_jtag_out_clk \
-min [expr {2*$buffer_prop_min}] \
$db0_jtag_inputs
set_multicycle_path -setup -end -from $db0_jtag_inputs 2
set_multicycle_path -hold -end -from $db0_jtag_inputs 3
##### DB 1 #####
# generated jtag clock is at least divided by 4
set db1_jtag_clk_register [get_registers {ctrlport_to_jtag:db1_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}]
create_generated_clock -source $pll_clk_out_pin \
-name db1_jtag_clk $db1_jtag_clk_register \
-divide_by 4
# see White Rabbit DAC for futher explanation
set_false_path -from $db1_jtag_clk_register -to $db1_jtag_clk_register
create_generated_clock \
-source $db1_jtag_clk_register \
-name db1_jtag_out_clk [get_ports {DB_JTAG_TCK[1]}]
set_output_delay -clock db1_jtag_out_clk \
-max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \
$db1_jtag_outputs
set_output_delay -clock db1_jtag_out_clk \
-min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \
$db1_jtag_outputs
set_multicycle_path -setup -start -to $db1_jtag_outputs 2
set_multicycle_path -hold -start -to $db1_jtag_outputs 3
# maximum delay accounts for slow clock and data propagation as
# well as clock to out time
set_input_delay -clock_fall -clock db1_jtag_out_clk \
-max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \
$db1_jtag_inputs
# ideally everything changes immediatelly
set_input_delay -clock_fall -clock db1_jtag_out_clk \
-min [expr {2*$buffer_prop_min}] \
$db1_jtag_inputs
set_multicycle_path -setup -end -from $db1_jtag_inputs 2
set_multicycle_path -hold -end -from $db1_jtag_inputs 3
#####################################################################
# DB clock and reset
#####################################################################
# Output clocks for the daughterboards (SPI control)
create_generated_clock -source $pll_clk_out_pin \
-name db0_ref_clk [get_ports {DB_REF_CLK[0]}]
create_generated_clock -source $pll_clk_out_pin \
-name db1_ref_clk [get_ports {DB_REF_CLK[1]}]
# output reset within one clock period
set_max_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] $CLK_100_period
set_min_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] 0
#####################################################################
# DB SPI interfaces
#####################################################################
# --------- ----------------- -----------------
# FPGA | CS/SCLK/ | MB CPLD | | DB |
# |-- MOSI ->|--------> R1 ->|--------->| |
# SPI | | | | SPI |
# master |<- MISO --|<- R2 <--------|<---------| slave |
# --------- ----------------- -----------------
#
# The output clocks are derived from the PLL reference clock (PRC). The SCLK
# edges are aligned with the rising edge of PLL reference clock. There are two
# registers R1 and R2 in the SPI path between FPGA and DB.
# For the transmission of data from master to slave those registers are
# transparent. The overall reception is just delayed by 1 PLL reference clock
# cycle. In the other direction the MISO timing is different. The falling edge
# of SCLK is used for changing the data signals. The propagation of this signal
# to the DB is delayed by 1 PLL reference clock period because of register R1.
# The MISO signal is captured on the rising edge of SCLK on the FPGA. Register
# R2 in the MB CPLD changes the timing in a way that MISO has to be stable on
# the rising edge of PLL reference clock before the SCLK rising edge.
# Additionally a minimum of two PLL reference clock cycles are required for
# processing in the SPI slave. The number of processing cycles is denoted by n.
# Here is an example for n=2 and SPI bus with CPHA=0 and CPOL=0.
# Data is driven on the falling edge and captured on the rising edge of the
# clock signal. The falling edge of the SCLK@DB is delayed by a clock cycle
# because of R1. The FPGA as SPI master is capturing the data on the rising edge
# of SCLK. The register R2 on the MB CPLD is capturing the data one clock cycle
# earlier. Therefore MISO has to be stable one clock cycle earlier then the
# original SCLK at the MB CPLD input. The effective SCLK signal to use for the
# timing constraints of the DB therefore has a low period which is reduced by 2
# clock cycles (R1 + R2) of PLL reference clock. It still has the same period as
# SCLK. In this example the low period would be 2 PRC cycles and the high period
# would be 6 PRC cycles.
# The following waveform illustrates the timing for n=2. Based on the defined
# delays <XXXX> denotes the time when the signal is not stable.
#
# <--- R1 --->|<-------- n=2 -------->|<--- R2 --->
# PRC ___/-----\_____/-----\_____/-----\_____/-----\_____/----
# SCLK ---\_______________________________________________/----
# SCLK @ DB (ideal) ---------------\________________________________________
# SCLK @ DB (effective) ---------------\_______________________/----------------
# MOSI output @ MB CPLD --------------<XXXX>------------------------------------
# MISO input @ MB CPLD -------------------------<XXXX>-------------------------
# DB propagation and processing <--------->
# MOSI change @ FPGA ^
# MOSI change @ MB CPLD ^
# MISO capture @ MB CPLD ^
# MISO capture @ FPGA ^
#
# Although the delays are defined based on PLL reference clock the SPI bus clock
# must be divided by at least n+2, where n>1 to be functional. Increase n in
# case the DB propagation and processing time does not fit into n PLL reference
# clock cycles taking the delays from below into account (see waveform above).
# Make sure you defined the SPI bus clock frequency for the slave to n*PLL clock
# period (effective SPI clock). Set the required SPI DB clock divider on the
# FPGA before starting data transfer.
#
# The constants for this interface are defined in db_spi_shared_constants.sdc
#### DB 0 ####
create_generated_clock -source [get_ports {PLL_REF_CLK}] \
-name db0_ctrl_clk_int [get_registers {DB_CTRL_SCLK[0]~reg0}]
create_generated_clock -source [get_registers {DB_CTRL_SCLK[0]~reg0}] \
-name db0_ctrl_clk [get_ports {DB_CTRL_SCLK[0]}]
set db0_ctrl_outputs [get_ports {DB_CTRL_MOSI[0] DB_CTRL_CS_N[0]}]
set_output_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_out $db0_ctrl_outputs
set_output_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_out $db0_ctrl_outputs
set db0_ctrl_inputs [get_ports {DB_CTRL_MISO[0]}]
set_input_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_in $db0_ctrl_inputs
set_input_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_in $db0_ctrl_inputs
#### DB 1 ####
create_generated_clock -source [get_ports {PLL_REF_CLK}] \
-name db1_ctrl_clk_int [get_registers {DB_CTRL_SCLK[1]~reg0}]
create_generated_clock -source [get_registers {DB_CTRL_SCLK[1]~reg0}] \
-name db1_ctrl_clk [get_ports DB_CTRL_SCLK[1]]
set db1_ctrl_outputs [get_ports {DB_CTRL_MOSI[1] DB_CTRL_CS_N[1]}]
set_output_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_out $db1_ctrl_outputs
set_output_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_out $db1_ctrl_outputs
set db1_ctrl_inputs [get_ports {DB_CTRL_MISO[1]}]
set_input_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_in $db1_ctrl_inputs
set_input_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_in $db1_ctrl_inputs
#####################################################################
# DB specific LED constraints
#####################################################################
# LED signals
set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \
QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*]}]
set_min_delay -to $led_outputs 0
set_max_delay -to $led_outputs $prc_clock_period
#####################################################################
# MB CPLD PS SPI passthrough x410 specific
#####################################################################
#
# Get port to apply the multi-cycle constraint for x410 specific port.
# see common.sdc for more extensive doc and explanation
set binary_cs_ports_ti [get_ports {DB_CALEEPROM_CS_N[*]}]
set_multicycle_path -setup -start -to $binary_cs_ports_ti $ps_spi_setup_multicycle
set_multicycle_path -hold -start -to $binary_cs_ports_ti $ps_spi_hold_multicycle
###### DB Calibration EEPROM ######
# Use worst case board propagation delays to estimate input and output
# timing. The longest path assuming 170 ps/in is:
# db0_caleeprom_spi_cs_n | 4.387 in | 0.746 ns
set eeprom_board_prop_delay 0.746
# Within the path to the EEPROM on the DB there is a level-transistor.
# The maximum propagation delays are 0.1..3.3 ns to the DB and 3.7 ns from the DB.
set eeprom_lvl_trans_to_db_delay_min 0.1
set eeprom_lvl_trans_to_db_delay_max 3.3
set eeprom_lvl_trans_from_db_delay_max 3.7
# Data in setup and hold times of the EEPROM are 5ns (based on the
# CS_N setup and hold times).
set db_eeprom_setup 5
set db_eeprom_hold 5
# Ouput valid from SCK is min 0 ns and max 8 ns.
set db_eeprom_output_valid 8
# max out path assuming clock delay is 0 and data delay is maximum value
set eeprom_max_out [expr {$eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_max + $db_eeprom_setup}]
# min out path assuming clock delay is maximal and data delay is 0
set eeprom_min_out [expr {-($eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_min + $db_eeprom_hold)}]
# board propagation to eeprom and back + lvl_translator back and forth + clock to data on eeprom
set eeprom_max_in [expr {$eeprom_board_prop_delay*2 + $eeprom_lvl_trans_to_db_delay_max + $eeprom_lvl_trans_from_db_delay_max + $db_eeprom_output_valid}]
# assuming no delay for everything
set eeprom_min_in 0
### DB 0
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name db0_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[0]}]
set db0_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[0] DB_CALEEPROM_CS_N[0]}]
set_output_delay -clock db0_eeprom_clk -max $eeprom_max_out $db0_eeprom_outputs
set_output_delay -clock db0_eeprom_clk -min $eeprom_min_out $db0_eeprom_outputs
set db0_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[0]}]
# data is changed on the falling edge
set_input_delay -clock db0_eeprom_clk -clock_fall -max $eeprom_max_in $db0_eeprom_inputs
set_input_delay -clock db0_eeprom_clk -clock_fall -min $eeprom_min_in $db0_eeprom_inputs
### DB 1
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name db1_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[1]}]
set db1_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[1] DB_CALEEPROM_CS_N[1]}]
set_output_delay -clock db1_eeprom_clk -max $eeprom_max_out $db1_eeprom_outputs
set_output_delay -clock db1_eeprom_clk -min $eeprom_min_out $db1_eeprom_outputs
set db1_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[1]}]
# data is changed on the falling edge
set_input_delay -clock db1_eeprom_clk -clock_fall -max $eeprom_max_in $db1_eeprom_inputs
set_input_delay -clock db1_eeprom_clk -clock_fall -min $eeprom_min_in $db1_eeprom_inputs
top/x400/cpld/x410/mb_cpld.v
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top/x400/cpld/x410/quartus/mb_cpld.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 13:40:17 August 15, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "13:40:17 August 15, 2019"
# Revisions
PROJECT_REVISION = "mb_cpld"
top/x400/cpld/x410/quartus/mb_cpld.qsf
+433
View File
@@ -0,0 +1,433 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 12:02:17 February 20, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TopCpld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#--------------------------------------------------------------------------
# Project properties/settings
#--------------------------------------------------------------------------
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M04SAU169I7G
set_global_assignment -name TOP_LEVEL_ENTITY mb_cpld
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:02:17 FEBRUARY 20, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_JTAG_PIN_SHARING ON
set_global_assignment -name GENERATE_SVF_FILE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
#--------------------------------------------------------------------------
# Pin constraints
#--------------------------------------------------------------------------
# Clocking.
#------------------------------------------
# CPLD's PLL reference clock.
set_location_assignment PIN_H6 -to PLL_REF_CLK
set_location_assignment PIN_G5 -to "PLL_REF_CLK(n)"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to PLL_REF_CLK
# Reliable clock (100 MHz).
set_location_assignment PIN_H4 -to CLK_100
set_location_assignment PIN_H5 -to "CLK_100(n)"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to CLK_100
# Power supply clocks.
set_location_assignment PIN_H8 -to PWR_SUPPLY_CLK_CORE
set_location_assignment PIN_H9 -to PWR_SUPPLY_CLK_DDR4_S
set_location_assignment PIN_G12 -to PWR_SUPPLY_CLK_DDR4_N
set_location_assignment PIN_L13 -to PWR_SUPPLY_CLK_0P9V
set_location_assignment PIN_G13 -to PWR_SUPPLY_CLK_1P8V
set_location_assignment PIN_K10 -to PWR_SUPPLY_CLK_2P5V
set_location_assignment PIN_J10 -to PWR_SUPPLY_CLK_3P3V
set_location_assignment PIN_L12 -to PWR_SUPPLY_CLK_3P6V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_0P9V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_1P8V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_2P5V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P3V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P6V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_CORE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_S
# Oscillator power supply
set_location_assignment PIN_L2 -to PWR_EN_5V_OSC_100
set_location_assignment PIN_N2 -to PWR_EN_5V_OSC_122_88
set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_100
set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_122_88
# Interfaces from/to RFSoC.
#------------------------------------------
# PL SPI slave interface.
set_location_assignment PIN_G2 -to PL_CPLD_SCLK
set_location_assignment PIN_F5 -to PL_CPLD_MOSI
set_location_assignment PIN_F6 -to PL_CPLD_MISO
set_location_assignment PIN_G1 -to PL_CPLD_CS_N[0]
set_location_assignment PIN_G4 -to PL_CPLD_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_SCLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MOSI
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MISO
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[1]
# IRQ to PL.
set_location_assignment PIN_F4 -to PL_CPLD_IRQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_IRQ
# PS SPI slave interface.
set_location_assignment PIN_E3 -to PS_CPLD_SCLK
set_location_assignment PIN_E1 -to PS_CPLD_MOSI
set_location_assignment PIN_F1 -to PS_CPLD_MISO
set_location_assignment PIN_B1 -to PS_CPLD_CS_N[0]
set_location_assignment PIN_C1 -to PS_CPLD_CS_N[1]
set_location_assignment PIN_E4 -to PS_CPLD_CS_N[2]
set_location_assignment PIN_D1 -to PS_CPLD_CS_N[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_SCLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MOSI
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MISO
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[3]
# PL Interfaces to/from motherboard.
#------------------------------------------
# White Rabbit DAC SPI master interface.
set_location_assignment PIN_A12 -to CLK_DB_SCLK
set_location_assignment PIN_B13 -to CLK_DB_MOSI
set_location_assignment PIN_D12 -to CLK_DB_MISO
set_location_assignment PIN_D9 -to CLK_DB_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_CS_N
# iPASS interfaces.
set_location_assignment PIN_A6 -to IPASS_SCL[0]
set_location_assignment PIN_H2 -to IPASS_SCL[1]
set_location_assignment PIN_A7 -to IPASS_SDA[0]
set_location_assignment PIN_H3 -to IPASS_SDA[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[1]
set_location_assignment PIN_B11 -to IPASS_PRESENT_N[0]
set_location_assignment PIN_F8 -to IPASS_PRESENT_N[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[1]
# QSFP LEDs.
set_location_assignment PIN_E12 -to QSFP0_LED_ACTIVE[0]
set_location_assignment PIN_F12 -to QSFP0_LED_ACTIVE[1]
set_location_assignment PIN_E9 -to QSFP0_LED_ACTIVE[2]
set_location_assignment PIN_J1 -to QSFP0_LED_ACTIVE[3]
set_location_assignment PIN_F10 -to QSFP0_LED_LINK[0]
set_location_assignment PIN_F9 -to QSFP0_LED_LINK[1]
set_location_assignment PIN_N11 -to QSFP0_LED_LINK[2]
set_location_assignment PIN_D13 -to QSFP0_LED_LINK[3]
set_location_assignment PIN_M1 -to QSFP1_LED_ACTIVE[0]
set_location_assignment PIN_N3 -to QSFP1_LED_ACTIVE[1]
set_location_assignment PIN_L3 -to QSFP1_LED_ACTIVE[2]
set_location_assignment PIN_K2 -to QSFP1_LED_ACTIVE[3]
set_location_assignment PIN_M2 -to QSFP1_LED_LINK[0]
set_location_assignment PIN_M3 -to QSFP1_LED_LINK[1]
set_location_assignment PIN_K1 -to QSFP1_LED_LINK[2]
set_location_assignment PIN_L1 -to QSFP1_LED_LINK[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP0_LED_ACTIVE[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[3]
# DIO direction control.
set_location_assignment PIN_N12 -to DIO_DIRECTION_A[0]
set_location_assignment PIN_N10 -to DIO_DIRECTION_A[1]
set_location_assignment PIN_N9 -to DIO_DIRECTION_A[2]
set_location_assignment PIN_M4 -to DIO_DIRECTION_A[3]
set_location_assignment PIN_M5 -to DIO_DIRECTION_A[4]
set_location_assignment PIN_N4 -to DIO_DIRECTION_A[5]
set_location_assignment PIN_N5 -to DIO_DIRECTION_A[6]
set_location_assignment PIN_N7 -to DIO_DIRECTION_A[7]
set_location_assignment PIN_N8 -to DIO_DIRECTION_A[8]
set_location_assignment PIN_M8 -to DIO_DIRECTION_A[9]
set_location_assignment PIN_M9 -to DIO_DIRECTION_A[10]
set_location_assignment PIN_M13 -to DIO_DIRECTION_A[11]
set_location_assignment PIN_L5 -to DIO_DIRECTION_B[0]
set_location_assignment PIN_L4 -to DIO_DIRECTION_B[1]
set_location_assignment PIN_K5 -to DIO_DIRECTION_B[2]
set_location_assignment PIN_J5 -to DIO_DIRECTION_B[3]
set_location_assignment PIN_N6 -to DIO_DIRECTION_B[4]
set_location_assignment PIN_M7 -to DIO_DIRECTION_B[5]
set_location_assignment PIN_J6 -to DIO_DIRECTION_B[6]
set_location_assignment PIN_K6 -to DIO_DIRECTION_B[7]
set_location_assignment PIN_J7 -to DIO_DIRECTION_B[8]
set_location_assignment PIN_K7 -to DIO_DIRECTION_B[9]
set_location_assignment PIN_M12 -to DIO_DIRECTION_B[10]
set_location_assignment PIN_M11 -to DIO_DIRECTION_B[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[11]
# PS Interfaces to/from motherboard.
#------------------------------------------
# LMK04832 SPI master interface.
set_location_assignment PIN_J9 -to LMK32_SCLK
set_location_assignment PIN_H13 -to LMK32_MOSI
set_location_assignment PIN_L11 -to LMK32_MISO
set_location_assignment PIN_J13 -to LMK32_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_CS_N
# TPM 2.0 SPI master interface.
set_location_assignment PIN_D11 -to TPM_SCLK
set_location_assignment PIN_E10 -to TPM_MOSI
set_location_assignment PIN_C13 -to TPM_MISO
set_location_assignment PIN_L10 -to TPM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_CS_N
# Phase DAC SPI master interface.
set_location_assignment PIN_K8 -to PHASE_DAC_SCLK
set_location_assignment PIN_J8 -to PHASE_DAC_MOSI
set_location_assignment PIN_M10 -to PHASE_DAC_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N
# Daughterboards' JTAG master interfaces.
set_location_assignment PIN_J12 -to DB_JTAG_TCK[0]
set_location_assignment PIN_G9 -to DB_JTAG_TCK[1]
set_location_assignment PIN_K12 -to DB_JTAG_TDI[0]
set_location_assignment PIN_E13 -to DB_JTAG_TDI[1]
set_location_assignment PIN_H10 -to DB_JTAG_TDO[0]
set_location_assignment PIN_F13 -to DB_JTAG_TDO[1]
set_location_assignment PIN_K11 -to DB_JTAG_TMS[0]
set_location_assignment PIN_G10 -to DB_JTAG_TMS[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[1]
# Daughterboards' Calibration EEPROM SPI interfaces.
set_location_assignment PIN_C9 -to DB_CALEEPROM_CS_N[0]
set_location_assignment PIN_B9 -to DB_CALEEPROM_MISO[0]
set_location_assignment PIN_B10 -to DB_CALEEPROM_MOSI[0]
set_location_assignment PIN_A10 -to DB_CALEEPROM_SCLK[0]
set_location_assignment PIN_B5 -to DB_CALEEPROM_MOSI[1]
set_location_assignment PIN_B6 -to DB_CALEEPROM_SCLK[1]
set_location_assignment PIN_B4 -to DB_CALEEPROM_MISO[1]
set_location_assignment PIN_B3 -to DB_CALEEPROM_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[1]
# Daughterboards' Control interfaces.
set_location_assignment PIN_C10 -to DB_CTRL_SCLK[0]
set_location_assignment PIN_A9 -to DB_CTRL_MISO[0]
set_location_assignment PIN_A8 -to DB_ARST[0]
set_location_assignment PIN_A11 -to DB_CTRL_CS_N[0]
set_location_assignment PIN_E8 -to DB_CTRL_MOSI[0]
set_location_assignment PIN_D8 -to DB_REF_CLK[0]
set_location_assignment PIN_A3 -to DB_REF_CLK[1]
set_location_assignment PIN_A4 -to DB_CTRL_MISO[1]
set_location_assignment PIN_D6 -to DB_CTRL_CS_N[1]
set_location_assignment PIN_E6 -to DB_CTRL_SCLK[1]
set_location_assignment PIN_A5 -to DB_CTRL_MOSI[1]
set_location_assignment PIN_B2 -to DB_ARST[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[1]
# Miscellaneous.
#------------------------------------------
# Power supply clocks switch.
set_location_assignment PIN_J2 -to PS_CLK_ON_CPLD
set_instance_assignment -name IO_STANDARD "2.5 V" -to PS_CLK_ON_CPLD
# iPASS misc.
set_location_assignment PIN_B12 -to IPASS_POWER_DISABLE
set_location_assignment PIN_C11 -to IPASS_POWER_EN_FAULT[0]
set_location_assignment PIN_C12 -to IPASS_POWER_EN_FAULT[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_DISABLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[1]
# PCIe reset to FPGA.
set_location_assignment PIN_A2 -to PCIE_RESET
set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET
# TPM reset.
set_location_assignment PIN_K13 -to TPM_RESET_n
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_RESET_n
# File list.
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP OFF
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP OFF
set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd
set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd
set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys
set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
set_global_assignment -name SDC_FILE ../common/common.sdc
set_global_assignment -name SDC_FILE ../x410/db_spi_shared_constants.sdc
set_global_assignment -name SDC_FILE ../x410/mb_cpld.sdc
set_global_assignment -name VERILOG_FILE ../x410/mb_cpld.v
set_global_assignment -name VERILOG_FILE ../x410/ctrlport_to_jtag.v
set_global_assignment -name VERILOG_FILE ../common/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../common/ctrlport_to_spi.v
set_global_assignment -name VERILOG_FILE ../common/pl_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/pwr_supply_clk_gen.v
set_global_assignment -name VERILOG_FILE ../common/ps_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/ps_power_regs.v
set_global_assignment -name VERILOG_FILE ../common/reset_generator.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave.v
set_global_assignment -name QIP_FILE ../ip/pll/pll.qip
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v
set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_splitter.v
set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_terminator.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_top.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_shift.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_defines.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_clgen.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchronizer.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd
set_global_assignment -name QIP_FILE ../ip/oddr/oddr.qip
set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_IMPORT_FILE ../../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix"