fpga: x4xx: Refactor MB CPLD code for future devices

Original-commit: e2a79712a7949ffec88135236c744dc5d8bde217
2023-05-23 09:05:27 +02:00
parent e9a6fe4e2e
commit ffdcc016cc
33 changed files with 5895 additions and 14 deletions
@@ -0,0 +1,28 @@
+//
+// Copyright 2023 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: constants_regmap_utils.vh
+// Description:
+// The constants in this file are autogenerated by XmlParse.
+
+//===============================================================================
+// A numerically ordered list of registers and their HDL source files
+//===============================================================================
+
+
+//===============================================================================
+// RegTypes
+//===============================================================================
+
+//===============================================================================
+// Register Group CONSTANTS_GROUP
+//===============================================================================
+
+  // Enumerated type CONSTANTS_ENUM
+  localparam CONSTANTS_ENUM_SIZE = 4;
+  localparam PS_CPLD_SIGNATURE     = 'hA522D27;  // CONSTANTS_ENUM:PS_CPLD_SIGNATURE
+  localparam OLDEST_CPLD_REVISION  = 'h20122114;  // CONSTANTS_ENUM:OLDEST_CPLD_REVISION
+  localparam CPLD_REVISION         = 'h22080414;  // CONSTANTS_ENUM:CPLD_REVISION
+  localparam PL_CPLD_SIGNATURE     = 'h3FDC5C47;  // CONSTANTS_ENUM:PL_CPLD_SIGNATURE
@@ -0,0 +1,36 @@
+//
+// Copyright 2023 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: mb_cpld_pl_regmap_utils.vh
+// Description:
+// The constants in this file are autogenerated by XmlParse.
+
+//===============================================================================
+// A numerically ordered list of registers and their HDL source files
+//===============================================================================
+
+  // PL_REGISTERS : 0x0 (mb_cpld.v)
+  // JTAG_DB0     : 0x60 (mb_cpld.v)
+  // JTAG_DB1     : 0x80 (mb_cpld.v)
+
+//===============================================================================
+// RegTypes
+//===============================================================================
+
+//===============================================================================
+// Register Group MB_CPLD_PL_WINDOWS
+//===============================================================================
+
+  // PL_REGISTERS Window (from mb_cpld.v)
+  localparam PL_REGISTERS = 'h0; // Window Offset
+  localparam PL_REGISTERS_SIZE = 'h40;  // size in bytes
+
+  // JTAG_DB0 Window (from mb_cpld.v)
+  localparam JTAG_DB0 = 'h60; // Window Offset
+  localparam JTAG_DB0_SIZE = 'h20;  // size in bytes
+
+  // JTAG_DB1 Window (from mb_cpld.v)
+  localparam JTAG_DB1 = 'h80; // Window Offset
+  localparam JTAG_DB1_SIZE = 'h20;  // size in bytes