fpga: e320: Fix timeout for timekeeper registers
This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem. Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
This commit is contained in:
Wade Fife
+215
-122
@@ -178,6 +178,7 @@ module e320_core #(
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output reg [31:0] dboard_ctrl,
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output reg [15:0] device_id
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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/////////////////////////////////////////////////////////////////////////////////
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//
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@@ -202,8 +203,12 @@ module e320_core #(
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/////////////////////////////////////////////////////////////////////////////////
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// Register base
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localparam REG_BASE_MISC = 14'h0;
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localparam REG_BASE_TIMEKEEPER = 14'h1000;
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localparam [CTRLPORT_ADDR_W-1:0] REG_BASE_MISC = 20'h0;
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localparam [CTRLPORT_ADDR_W-1:0] REG_BASE_TIMEKEEPER = 20'h1000;
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// Register region sizes. Give each register region a 256-byte window.
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localparam REG_GLOB_ADDR_W = 8;
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localparam REG_TIMEKEEPER_ADDR_W = 8;
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// Misc Registers
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localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00;
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@@ -226,7 +231,7 @@ module e320_core #(
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localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
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localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
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localparam NUM_TIMEKEEPERS = 16'd1;
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localparam NUM_TIMEKEEPERS = 1;
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wire m_ctrlport_req_wr;
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wire m_ctrlport_req_rd;
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@@ -240,19 +245,6 @@ module e320_core #(
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reg [31:0] fp_gpio_master_reg = 32'h0;
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reg [31:0] fp_gpio_src_reg = 32'h0;
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wire reg_wr_req;
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wire [REG_AWIDTH-1:0] reg_wr_addr;
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wire [REG_DWIDTH-1:0] reg_wr_data;
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wire reg_rd_req;
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wire [REG_AWIDTH-1:0] reg_rd_addr;
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wire reg_rd_resp;
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wire [REG_DWIDTH-1:0] reg_rd_data;
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reg reg_rd_resp_glob;
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reg [REG_DWIDTH-1:0] reg_rd_data_glob;
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wire reg_rd_resp_tk;
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wire [REG_DWIDTH-1:0] reg_rd_data_tk;
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reg [31:0] scratch_reg = 32'h0;
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reg [31:0] bus_counter = 32'h0;
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@@ -263,55 +255,156 @@ module e320_core #(
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bus_counter <= bus_counter + 32'd1;
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end
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// Regport Master to convert AXI4-Lite to regport
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axil_regport_master #(
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.DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (REG_AWIDTH), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
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) core_regport_master_i (
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// Clock and reset
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/////////////////////////////////////////////////////////////////////////////
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//
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// Bus Bridge
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//
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/////////////////////////////////////////////////////////////////////////////
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// We need a really long timeout for CtrlPort transactions, since the
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// radio_clk for the timekeeper might be really slow compared to s_axi_aclk.
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localparam CTRLPORT_TIMEOUT = 20;
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wire cp_req_wr_aclk;
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wire cp_req_rd_aclk;
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wire [CTRLPORT_ADDR_W-1:0] cp_req_addr_aclk;
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wire [CTRLPORT_DATA_W-1:0] cp_req_data_aclk;
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wire cp_resp_ack_aclk;
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wire [ CTRLPORT_STS_W-1:0] cp_resp_status_aclk;
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wire [CTRLPORT_DATA_W-1:0] cp_resp_data_aclk;
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// Convert the AXI4-Lite transactions to CtrlPort
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axil_ctrlport_master #(
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.TIMEOUT (CTRLPORT_TIMEOUT),
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.AXI_AWIDTH (REG_AWIDTH),
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.CTRLPORT_AWIDTH (CTRLPORT_ADDR_W)
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) axil_ctrlport_master_i (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_wr_keep (/*unused*/),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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.m_ctrlport_req_wr (cp_req_wr_aclk),
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.m_ctrlport_req_rd (cp_req_rd_aclk),
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.m_ctrlport_req_addr (cp_req_addr_aclk),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (cp_req_data_aclk),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (cp_resp_ack_aclk),
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.m_ctrlport_resp_status (cp_resp_status_aclk),
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.m_ctrlport_resp_data (cp_resp_data_aclk)
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);
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//--------------------------------------------------------------------
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wire cp_req_wr;
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wire cp_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] cp_req_addr;
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wire [CTRLPORT_DATA_W-1:0] cp_req_data;
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wire cp_resp_ack;
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wire [ CTRLPORT_STS_W-1:0] cp_resp_status;
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wire [CTRLPORT_DATA_W-1:0] cp_resp_data;
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// Cross transactions from s_axi_clk to bus_clk domain
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ctrlport_clk_cross ctrlport_clk_cross_i (
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.rst (~s_axi_aresetn),
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.s_ctrlport_clk (s_axi_aclk),
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.s_ctrlport_req_wr (cp_req_wr_aclk),
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.s_ctrlport_req_rd (cp_req_rd_aclk),
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.s_ctrlport_req_addr (cp_req_addr_aclk),
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.s_ctrlport_req_portid ({CTRLPORT_PORTID_W{1'b0}}),
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.s_ctrlport_req_rem_epid ({CTRLPORT_REM_EPID_W{1'b0}}),
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.s_ctrlport_req_rem_portid ({CTRLPORT_PORTID_W{1'b0}}),
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.s_ctrlport_req_data (cp_req_data_aclk),
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.s_ctrlport_req_byte_en ({CTRLPORT_BYTE_EN_W{1'b1}}),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time ({CTRLPORT_TIME_W{1'b0}}),
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.s_ctrlport_resp_ack (cp_resp_ack_aclk),
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.s_ctrlport_resp_status (cp_resp_status_aclk),
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.s_ctrlport_resp_data (cp_resp_data_aclk),
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.m_ctrlport_clk (bus_clk),
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.m_ctrlport_req_wr (cp_req_wr),
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.m_ctrlport_req_rd (cp_req_rd),
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.m_ctrlport_req_addr (cp_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (cp_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (cp_resp_ack),
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.m_ctrlport_resp_status (cp_resp_status),
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.m_ctrlport_resp_data (cp_resp_data)
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);
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wire cp_glob_req_wr;
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wire cp_glob_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] cp_glob_req_addr;
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wire [CTRLPORT_DATA_W-1:0] cp_glob_req_data;
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reg cp_glob_resp_ack = 1'b0;
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reg [CTRLPORT_DATA_W-1:0] cp_glob_resp_data = 1'bX;
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wire cp_tk_req_wr;
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wire cp_tk_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] cp_tk_req_addr;
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wire [CTRLPORT_DATA_W-1:0] cp_tk_req_data;
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wire cp_tk_resp_ack;
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wire [CTRLPORT_DATA_W-1:0] cp_tk_resp_data;
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// Split the CtrlPort for the global registers and the timekeeper registers
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ctrlport_decoder_param #(
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.NUM_SLAVES (2),
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.PORT_BASE ({ REG_BASE_TIMEKEEPER, REG_BASE_MISC }),
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.PORT_ADDR_W ({ REG_TIMEKEEPER_ADDR_W, REG_GLOB_ADDR_W })
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) ctrlport_decoder_param_i (
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.ctrlport_clk (bus_clk),
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.ctrlport_rst (bus_rst),
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.s_ctrlport_req_wr (cp_req_wr),
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.s_ctrlport_req_rd (cp_req_rd),
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.s_ctrlport_req_addr (cp_req_addr),
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.s_ctrlport_req_data (cp_req_data),
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.s_ctrlport_req_byte_en ({CTRLPORT_BYTE_EN_W{1'b1}}),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time ({CTRLPORT_TIME_W{1'b0}}),
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.s_ctrlport_resp_ack (cp_resp_ack),
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.s_ctrlport_resp_status (cp_resp_status),
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.s_ctrlport_resp_data (cp_resp_data),
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.m_ctrlport_req_wr ({ cp_tk_req_wr, cp_glob_req_wr }),
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.m_ctrlport_req_rd ({ cp_tk_req_rd, cp_glob_req_rd }),
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.m_ctrlport_req_addr ({ cp_tk_req_addr, cp_glob_req_addr }),
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.m_ctrlport_req_data ({ cp_tk_req_data, cp_glob_req_data }),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack ({ cp_tk_resp_ack, cp_glob_resp_ack }),
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.m_ctrlport_resp_status ({2{CTRL_STS_OKAY}}),
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.m_ctrlport_resp_data ({ cp_tk_resp_data, cp_glob_resp_data })
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);
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/////////////////////////////////////////////////////////////////////////////
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//
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// Global Registers
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// -------------------------------------------------------------------
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//
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/////////////////////////////////////////////////////////////////////////////
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// Write Registers
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always @ (posedge bus_clk) begin
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@@ -323,118 +416,123 @@ module e320_core #(
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gps_ctrl <= 32'h3; // Default to gps_en, out of reset
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dboard_ctrl <= 32'h1; // Default to mimo
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device_id <= 16'h0;
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end else if (reg_wr_req) begin
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case (reg_wr_addr)
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REG_DEVICE_ID: begin
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device_id <= reg_wr_data[15:0];
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end
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REG_FP_GPIO_MASTER: begin
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fp_gpio_master_reg <= reg_wr_data;
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end
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REG_FP_GPIO_RADIO_SRC: begin
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fp_gpio_src_reg <= reg_wr_data;
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end
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REG_SCRATCH: begin
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scratch_reg <= reg_wr_data;
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end
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cp_glob_resp_ack <= 1'b0;
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cp_glob_resp_data <= 'bX;
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end begin
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cp_glob_resp_ack <= 1'b0;
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if (cp_glob_req_wr) begin
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cp_glob_resp_ack <= 1'b1;
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case (cp_glob_req_addr[REG_GLOB_ADDR_W-1:0])
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REG_DEVICE_ID:
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device_id <= cp_glob_req_data[15:0];
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REG_FP_GPIO_MASTER:
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fp_gpio_master_reg <= cp_glob_req_data;
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REG_FP_GPIO_RADIO_SRC:
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fp_gpio_src_reg <= cp_glob_req_data;
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REG_SCRATCH:
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scratch_reg <= cp_glob_req_data;
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REG_CLOCK_CTRL: begin
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pps_select <= reg_wr_data[1:0];
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ref_select <= reg_wr_data[2];
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cp_glob_resp_data <= 32'b0;
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pps_select <= cp_glob_req_data[1:0];
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ref_select <= cp_glob_req_data[2];
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end
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REG_FP_GPIO_CTRL: begin
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fp_gpio_ctrl <= reg_wr_data;
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end
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REG_GPS_CTRL: begin
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gps_ctrl <= reg_wr_data;
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end
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REG_DBOARD_CTRL: begin
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dboard_ctrl <= reg_wr_data;
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REG_FP_GPIO_CTRL:
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fp_gpio_ctrl <= cp_glob_req_data;
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REG_GPS_CTRL:
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gps_ctrl <= cp_glob_req_data;
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REG_DBOARD_CTRL:
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dboard_ctrl <= cp_glob_req_data;
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default: begin
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// Don't acknowledge if the address doesn't match
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cp_glob_resp_ack <= 1'b0;
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end
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endcase
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end
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end
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// Read Registers
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always @ (posedge bus_clk) begin
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if (bus_rst) begin
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reg_rd_resp_glob <= 1'b0;
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end
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else begin
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if (cp_glob_req_rd) begin
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cp_glob_resp_data <= 0; // Unused bits will read 0
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cp_glob_resp_ack <= 1'b1;
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if (reg_rd_req) begin
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reg_rd_resp_glob <= 1'b1;
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case (reg_rd_addr)
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case (cp_glob_req_addr[REG_GLOB_ADDR_W-1:0])
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REG_DEVICE_ID:
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reg_rd_data_glob <= device_id;
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cp_glob_resp_data <= { 16'd0, device_id };
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REG_RFNOC_INFO:
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reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
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cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
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REG_COMPAT_NUM:
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reg_rd_data_glob <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
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cp_glob_resp_data <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
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REG_FP_GPIO_CTRL:
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reg_rd_data_glob <= fp_gpio_ctrl;
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cp_glob_resp_data <= fp_gpio_ctrl;
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REG_FP_GPIO_MASTER:
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reg_rd_data_glob <= fp_gpio_master_reg;
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cp_glob_resp_data <= fp_gpio_master_reg;
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REG_FP_GPIO_RADIO_SRC:
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reg_rd_data_glob <= fp_gpio_src_reg;
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cp_glob_resp_data <= fp_gpio_src_reg;
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REG_DATESTAMP:
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reg_rd_data_glob <= build_datestamp;
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cp_glob_resp_data <= build_datestamp;
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REG_GIT_HASH:
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`ifndef GIT_HASH
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`define GIT_HASH 32'h0BADC0DE
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`endif
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reg_rd_data_glob <= `GIT_HASH;
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cp_glob_resp_data <= `GIT_HASH;
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REG_SCRATCH:
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reg_rd_data_glob <= scratch_reg;
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cp_glob_resp_data <= scratch_reg;
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REG_CLOCK_CTRL: begin
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reg_rd_data_glob <= 32'b0;
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reg_rd_data_glob[1:0] <= pps_select;
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reg_rd_data_glob[2] <= ref_select;
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reg_rd_data_glob[3] <= refclk_locked;
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cp_glob_resp_data <= 32'b0;
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cp_glob_resp_data[1:0] <= pps_select;
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cp_glob_resp_data[2] <= ref_select;
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cp_glob_resp_data[3] <= refclk_locked;
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end
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REG_XADC_READBACK:
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reg_rd_data_glob <= xadc_readback;
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cp_glob_resp_data <= xadc_readback;
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REG_BUS_CLK_RATE:
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reg_rd_data_glob <= BUS_CLK_RATE;
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cp_glob_resp_data <= BUS_CLK_RATE;
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REG_BUS_CLK_COUNT:
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reg_rd_data_glob <= bus_counter;
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cp_glob_resp_data <= bus_counter;
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REG_SFP_PORT_INFO:
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reg_rd_data_glob <= sfp_ports_info;
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cp_glob_resp_data <= sfp_ports_info;
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REG_GPS_CTRL:
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reg_rd_data_glob <= gps_ctrl;
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cp_glob_resp_data <= gps_ctrl;
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REG_GPS_STATUS:
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reg_rd_data_glob <= gps_status;
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cp_glob_resp_data <= gps_status;
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REG_DBOARD_CTRL:
|
||||
reg_rd_data_glob <= dboard_ctrl;
|
||||
cp_glob_resp_data <= dboard_ctrl;
|
||||
|
||||
REG_DBOARD_STATUS:
|
||||
reg_rd_data_glob <= dboard_status;
|
||||
cp_glob_resp_data <= dboard_status;
|
||||
|
||||
REG_NUM_TIMEKEEPERS:
|
||||
reg_rd_data_glob <= NUM_TIMEKEEPERS;
|
||||
cp_glob_resp_data <= NUM_TIMEKEEPERS;
|
||||
|
||||
default:
|
||||
reg_rd_resp_glob <= 1'b0;
|
||||
endcase
|
||||
default: begin
|
||||
// Don't acknowledge if the address doesn't match
|
||||
cp_glob_resp_ack <= 1'b0;
|
||||
end
|
||||
else if (reg_rd_resp_glob) begin
|
||||
reg_rd_resp_glob <= 1'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -887,33 +985,28 @@ module e320_core #(
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Regport Mux for response
|
||||
regport_resp_mux #(
|
||||
.WIDTH (32),
|
||||
.NUM_SLAVES (2)
|
||||
) reg_resp_mux_i (
|
||||
.clk(bus_clk), .reset(bus_rst),
|
||||
.sla_rd_resp({reg_rd_resp_tk, reg_rd_resp_glob}),
|
||||
.sla_rd_data({reg_rd_data_tk, reg_rd_data_glob}),
|
||||
.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Timekeeper
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire [63:0] radio_time;
|
||||
|
||||
timekeeper #(
|
||||
.BASE_ADDR (REG_BASE_TIMEKEEPER),
|
||||
.BASE_ADDR (0), // ctrlport_decoder removes the base offset
|
||||
.TIME_INCREMENT (1'b1)
|
||||
) timekeeper_i (
|
||||
.tb_clk (radio_clk),
|
||||
.tb_rst (radio_rst),
|
||||
.s_ctrlport_clk (bus_clk),
|
||||
.s_ctrlport_req_wr (reg_wr_req),
|
||||
.s_ctrlport_req_rd (reg_rd_req),
|
||||
.s_ctrlport_req_addr (reg_wr_req ? reg_wr_addr: reg_rd_addr),
|
||||
.s_ctrlport_req_data (reg_wr_data),
|
||||
.s_ctrlport_resp_ack (reg_rd_resp_tk),
|
||||
.s_ctrlport_resp_data (reg_rd_data_tk),
|
||||
.s_ctrlport_req_wr (cp_tk_req_wr),
|
||||
.s_ctrlport_req_rd (cp_tk_req_rd),
|
||||
.s_ctrlport_req_addr (cp_tk_req_addr),
|
||||
.s_ctrlport_req_data (cp_tk_req_data),
|
||||
.s_ctrlport_resp_ack (cp_tk_resp_ack),
|
||||
.s_ctrlport_resp_data (cp_tk_resp_data),
|
||||
.sample_rx_stb (rx_stb[0]),
|
||||
.pps (pps_radioclk),
|
||||
.tb_timestamp (radio_time),
|
||||
|
||||
Reference in New Issue
Block a user