miegl/b210-k7-fpga
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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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top/x300/timing.ucf
+36
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NET "FPGA_CLK_p" TNM_NET = "FPGA_CLK_p";
TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50 %;
NET "FPGA_CLK_n" TNM_NET = "FPGA_CLK_n";
TIMESPEC "TS_FPGA_CLK_n" = PERIOD "FPGA_CLK_n" 5000 ps HIGH 50 %;
NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK";
TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %;
#NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P";
#TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 8333 ps HIGH 50 %;
#NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P";
#TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 8333 ps HIGH 50 %;
NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P";
TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 5000 ps HIGH 50 %;
OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING;
OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING;
NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P";
TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 5000 ps HIGH 50 %;
OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING;
OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING;
NET "bus_clk" TNM = bus_clk_grp;
NET "ioport2_clk" TNM = ioport2_clk_grp;
NET "rio40_clk" TNM = rio40_clk_grp;
TIMESPEC TS_BUS_CLK_TO_IOPORT2_CLK_FALEPATH = FROM bus_clk_grp TO ioport2_clk_grp TIG;
TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_grp TIG;
TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG;
TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG;