Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,79 @@
+/*******************************************************************************
+*     (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved.              *
+*                                                                              *
+*     This file contains confidential and proprietary information              *
+*     of Xilinx, Inc. and is protected under U.S. and                          *
+*     international copyright and other intellectual property                  *
+*     laws.                                                                    *
+*                                                                              *
+*     DISCLAIMER                                                               *
+*     This disclaimer is not a license and does not grant any                  *
+*     rights to the materials distributed herewith. Except as                  *
+*     otherwise provided in a valid license issued to you by                   *
+*     Xilinx, and to the maximum extent permitted by applicable                *
+*     law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND                  *
+*     WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES              *
+*     AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING                *
+*     BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-                   *
+*     INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and                 *
+*     (2) Xilinx shall not be liable (whether in contract or tort,             *
+*     including negligence, or under any other theory of                       *
+*     liability) for any loss or damage of any kind or nature                  *
+*     related to, arising under or in connection with these                    *
+*     materials, including for any direct, or any indirect,                    *
+*     special, incidental, or consequential loss or damage                     *
+*     (including loss of data, profits, goodwill, or any type of               *
+*     loss or damage suffered as a result of any action brought                *
+*     by a third party) even if such damage or loss was                        *
+*     reasonably foreseeable or Xilinx had been advised of the                 *
+*     possibility of the same.                                                 *
+*                                                                              *
+*     CRITICAL APPLICATIONS                                                    *
+*     Xilinx products are not designed or intended to be fail-                 *
+*     safe, or for use in any application requiring fail-safe                  *
+*     performance, such as life-support or safety devices or                   *
+*     systems, Class III medical devices, nuclear facilities,                  *
+*     applications related to the deployment of airbags, or any                *
+*     other applications that could lead to death, personal                    *
+*     injury, or severe property or environmental damage                       *
+*     (individually and collectively, "Critical                                *
+*     Applications"). Customer assumes the sole risk and                       *
+*     liability of any use of Xilinx products in Critical                      *
+*     Applications, subject only to applicable laws and                        *
+*     regulations governing limitations on product liability.                  *
+*                                                                              *
+*     THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS                 *
+*     PART OF THIS FILE AT ALL TIMES.                                          *
+*******************************************************************************/
+
+//  Generated from component ID: xilinx.com:ip:fir_compiler:5.0
+
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+hbint3 YourInstanceName (
+	.sclr(sclr), // input sclr
+	.clk(clk), // input clk
+	.ce(ce), // input ce
+	.nd(nd), // input nd
+	.coef_ld(coef_ld), // input coef_ld
+	.coef_we(coef_we), // input coef_we
+	.coef_din(coef_din), // input [17 : 0] coef_din
+	.rfd(rfd), // output rfd
+	.rdy(rdy), // output rdy
+	.data_valid(data_valid), // output data_valid
+	.din_1(din_1), // input [23 : 0] din_1
+	.din_2(din_2), // input [23 : 0] din_2
+	.dout_1(dout_1), // output [46 : 0] dout_1
+	.dout_2(dout_2)); // output [46 : 0] dout_2
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file hbint3.v when simulating
+// the core, hbint3. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+