Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,33 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila.v
+// /___/   /\     Timestamp  : Wed Jan 30 10:07:41 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila(
+    CONTROL,
+    CLK,
+    DATA,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [255 : 0] DATA;
+input [7 : 0] TRIG0;
+
+endmodule