Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,28 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_icon.veo
+// /___/   /\     Timestamp  : Wed Jan 30 10:04:14 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+chipscope_icon YourInstanceName (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+