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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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top/x300/coregen_chipscope/_xmsgs/pn_parser.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/ashish/git/fpgadev/usrp3/top/b250/coregen_chipscope/chipscope_ila.v&quot; into library work</arg>
</msg>
</messages>
top/x300/coregen_chipscope/_xmsgs/xst.xmsgs
+666
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 292: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_reset_ctrl.vhd" Line 88: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match.vhd" Line 93: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 104: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 105: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gandx_srl_k7.vhd" Line 102: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7.vhd" Line 64: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_slice_rpm_unset.vhd" Line 76: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_slice_rpm_unset.vhd" Line 77: Using initial value <arg fmt="%s" index="1">&apos;0&apos;</arg> for <arg fmt="%s" index="2">logic_0</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 120: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 110: Net &lt;<arg fmt="%s" index="1">iCFG_EN_VEC[15]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 83: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 84: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_rpm_unset.vhd" Line 156: Using initial value <arg fmt="%s" index="1">&quot;111111&quot;</arg> for <arg fmt="%s" index="2">srl_remainder</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 183: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 184: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="89" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd" Line 68: &lt;<arg fmt="%s" index="1">ramb18e1</arg>&gt; remains a black-box since it has no binding entity.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trace_buffer.vhd" Line 201: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 383: Net &lt;<arg fmt="%s" index="1">iCFG_EN_VEC[15]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 384: Net &lt;<arg fmt="%s" index="1">iCFG_EN_16_0</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 385: Net &lt;<arg fmt="%s" index="1">iCFG_EN_16_1</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 279: Net &lt;<arg fmt="%s" index="1">iCONTROL_IN[17]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 283: Net &lt;<arg fmt="%s" index="1">iATC_CLKIN</arg>&gt; does not have a driver.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila.vhd</arg>&quot; line <arg fmt="%s" index="2">44</arg>: Output port &lt;<arg fmt="%s" index="3">TRIG_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG2</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG4</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG5</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG6</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG7</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG8</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG9</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG10</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG11</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG12</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG13</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG14</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG15</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd</arg>&quot; line <arg fmt="%s" index="2">1028</arg>: Output port &lt;<arg fmt="%s" index="3">TRIG_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_YES_D.U_ILA</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCONTROL_IN&lt;17:15&gt;</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">TRIG_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iATC_CLKIN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;2:2&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;10:9&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;17:14&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;34:20&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">ATC_CLKIN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">601</arg>: Output port &lt;<arg fmt="%s" index="3">HALT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RST</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">627</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_TSEQ_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_TRIG</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">790</arg>: Output port &lt;<arg fmt="%s" index="3">CAP_EXT_TRIGOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_G2_SQ.U_CAPCTRL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">874</arg>: Output port &lt;<arg fmt="%s" index="3">WR_TSTAMP_OVERFLOW</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_CAPSTOR</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_VEC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_16_0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_16_1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigger.vhd</arg>&quot; line <arg fmt="%s" index="2">254</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_TC</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG_RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_combo.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_MU</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_TSEQ_EN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_VEC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CAP_ENDSTATE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TSTAMP_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_ctrl_g2_sq.vhd</arg>&quot; line <arg fmt="%s" index="2">468</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_SRLT_NE_1.U_WHCMPCE</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIGGER</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REWIND</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_TSTAMP</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_GAP</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_REWIND</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RD_TSTAMP_EN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd</arg>&quot; line <arg fmt="%s" index="2">418</arg>: Output port &lt;<arg fmt="%s" index="3">DOBDO</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RAMB18E1</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd</arg>&quot; line <arg fmt="%s" index="2">418</arg>: Output port &lt;<arg fmt="%s" index="3">DOPADOP</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RAMB18E1</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd</arg>&quot; line <arg fmt="%s" index="2">418</arg>: Output port &lt;<arg fmt="%s" index="3">DOPBDOP</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RAMB18E1</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[127].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[127].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[126].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[126].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[125].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[125].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[124].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[124].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[123].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[123].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[122].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[122].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[121].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[121].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[120].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[120].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[119].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[119].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[118].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[118].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[117].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[117].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[116].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[116].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[115].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[115].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[114].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[114].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[113].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[113].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[112].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[112].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[111].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[111].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[110].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[110].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[109].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[109].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[108].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[108].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[107].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[107].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[106].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[106].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[105].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[105].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[104].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[104].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[103].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[103].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[102].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[102].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[101].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[101].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[100].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[100].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[99].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[99].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[98].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[98].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[97].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[97].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[96].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[96].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[95].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[95].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[94].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[94].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[93].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[93].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[92].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[92].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[91].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[91].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[90].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[90].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[89].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[89].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[88].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[88].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[87].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[87].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[86].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[86].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[85].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[85].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[84].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[84].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[83].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[83].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[82].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[82].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[81].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[81].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[80].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[80].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[79].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[79].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[78].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[78].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[77].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[77].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[76].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[76].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[75].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[75].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[74].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[74].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[73].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[73].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[72].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[72].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[71].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[71].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[70].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[70].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[69].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[69].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[68].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[68].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[67].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[67].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[66].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[66].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[65].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[65].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36</arg> in unit <arg fmt="%s" index="2">I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36</arg> of type <arg fmt="%s" index="3">RAMB36</arg> has been replaced by <arg fmt="%s" index="4">RAMB36E1</arg>
</msg>
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
top/x300/coregen_chipscope/chipscope_icon.asy
+9
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@@ -0,0 +1,9 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 chipscope_icon
RECTANGLE Normal 32 32 544 864
LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.ucf
+9
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.xdc
+7
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# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/x300/coregen_chipscope/chipscope_icon.gise
+31
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@@ -0,0 +1,31 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_icon.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_icon.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_icon.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_chipscope/chipscope_icon.ncf
View File
top/x300/coregen_chipscope/chipscope_icon.ngc
+3
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File diff suppressed because one or more lines are too long
top/x300/coregen_chipscope/chipscope_icon.ucf
+9
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/x300/coregen_chipscope/chipscope_icon.v
+27
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@@ -0,0 +1,27 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Wed Jan 30 10:04:14 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
endmodule
top/x300/coregen_chipscope/chipscope_icon.veo
+28
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Wed Jan 30 10:04:14 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/x300/coregen_chipscope/chipscope_icon.xco
+56
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Jan 30 18:03:44 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: a8aec264
top/x300/coregen_chipscope/chipscope_icon.xdc
+7
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@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/x300/coregen_chipscope/chipscope_icon.xise
+72
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="chipscope_icon.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fbg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-30T10:04:16" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D24924FA7EC9C09E9A5A6576055B8A9C" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_chipscope/chipscope_icon_flist.txt
+15
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# Output products list for <chipscope_icon>
chipscope_icon.asy
chipscope_icon.constraints/chipscope_icon.ucf
chipscope_icon.constraints/chipscope_icon.xdc
chipscope_icon.gise
chipscope_icon.ngc
chipscope_icon.ucf
chipscope_icon.v
chipscope_icon.veo
chipscope_icon.xco
chipscope_icon.xdc
chipscope_icon.xise
chipscope_icon_flist.txt
chipscope_icon_readme.txt
chipscope_icon_xmdf.tcl
top/x300/coregen_chipscope/chipscope_icon_readme.txt
+45
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The following files were generated for 'chipscope_icon' in directory
/home/jblum/coregen_chipscope/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_icon.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_icon.constraints/chipscope_icon.ucf
* chipscope_icon.constraints/chipscope_icon.xdc
* chipscope_icon.ngc
* chipscope_icon.ucf
* chipscope_icon.v
* chipscope_icon.veo
* chipscope_icon.xdc
* chipscope_icon_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_icon.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* chipscope_icon.gise
* chipscope_icon.xise
Deliver Readme:
Readme file for the IP.
* chipscope_icon_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_icon_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_chipscope/chipscope_icon_xmdf.tcl
Executable
+88
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# The package naming convention is <core_name>_xmdf
package provide chipscope_icon_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::chipscope_icon_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::chipscope_icon_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon
}
# ::chipscope_icon_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_chipscope/chipscope_ila.asy
+21
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@@ -0,0 +1,21 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 chipscope_ila
RECTANGLE Normal 32 32 288 704
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName control[35:0]
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Wide 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName data[255:0]
PINATTR Polarity IN
LINE Wide 0 176 32 176
PIN 0 176 LEFT 36
PINATTR PinName trig0[7:0]
PINATTR Polarity IN
top/x300/coregen_chipscope/chipscope_ila.cdc
+275
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@@ -0,0 +1,275 @@
#ChipScope Core Generator Project File Version 3.0
#Wed Jan 30 10:07:41 PST 2013
SignalExport.clockChannel=CLK
SignalExport.dataChannel<0000>=DATA[0]
SignalExport.dataChannel<0001>=DATA[1]
SignalExport.dataChannel<0002>=DATA[2]
SignalExport.dataChannel<0003>=DATA[3]
SignalExport.dataChannel<0004>=DATA[4]
SignalExport.dataChannel<0005>=DATA[5]
SignalExport.dataChannel<0006>=DATA[6]
SignalExport.dataChannel<0007>=DATA[7]
SignalExport.dataChannel<0008>=DATA[8]
SignalExport.dataChannel<0009>=DATA[9]
SignalExport.dataChannel<0010>=DATA[10]
SignalExport.dataChannel<0011>=DATA[11]
SignalExport.dataChannel<0012>=DATA[12]
SignalExport.dataChannel<0013>=DATA[13]
SignalExport.dataChannel<0014>=DATA[14]
SignalExport.dataChannel<0015>=DATA[15]
SignalExport.dataChannel<0016>=DATA[16]
SignalExport.dataChannel<0017>=DATA[17]
SignalExport.dataChannel<0018>=DATA[18]
SignalExport.dataChannel<0019>=DATA[19]
SignalExport.dataChannel<0020>=DATA[20]
SignalExport.dataChannel<0021>=DATA[21]
SignalExport.dataChannel<0022>=DATA[22]
SignalExport.dataChannel<0023>=DATA[23]
SignalExport.dataChannel<0024>=DATA[24]
SignalExport.dataChannel<0025>=DATA[25]
SignalExport.dataChannel<0026>=DATA[26]
SignalExport.dataChannel<0027>=DATA[27]
SignalExport.dataChannel<0028>=DATA[28]
SignalExport.dataChannel<0029>=DATA[29]
SignalExport.dataChannel<0030>=DATA[30]
SignalExport.dataChannel<0031>=DATA[31]
SignalExport.dataChannel<0032>=DATA[32]
SignalExport.dataChannel<0033>=DATA[33]
SignalExport.dataChannel<0034>=DATA[34]
SignalExport.dataChannel<0035>=DATA[35]
SignalExport.dataChannel<0036>=DATA[36]
SignalExport.dataChannel<0037>=DATA[37]
SignalExport.dataChannel<0038>=DATA[38]
SignalExport.dataChannel<0039>=DATA[39]
SignalExport.dataChannel<0040>=DATA[40]
SignalExport.dataChannel<0041>=DATA[41]
SignalExport.dataChannel<0042>=DATA[42]
SignalExport.dataChannel<0043>=DATA[43]
SignalExport.dataChannel<0044>=DATA[44]
SignalExport.dataChannel<0045>=DATA[45]
SignalExport.dataChannel<0046>=DATA[46]
SignalExport.dataChannel<0047>=DATA[47]
SignalExport.dataChannel<0048>=DATA[48]
SignalExport.dataChannel<0049>=DATA[49]
SignalExport.dataChannel<0050>=DATA[50]
SignalExport.dataChannel<0051>=DATA[51]
SignalExport.dataChannel<0052>=DATA[52]
SignalExport.dataChannel<0053>=DATA[53]
SignalExport.dataChannel<0054>=DATA[54]
SignalExport.dataChannel<0055>=DATA[55]
SignalExport.dataChannel<0056>=DATA[56]
SignalExport.dataChannel<0057>=DATA[57]
SignalExport.dataChannel<0058>=DATA[58]
SignalExport.dataChannel<0059>=DATA[59]
SignalExport.dataChannel<0060>=DATA[60]
SignalExport.dataChannel<0061>=DATA[61]
SignalExport.dataChannel<0062>=DATA[62]
SignalExport.dataChannel<0063>=DATA[63]
SignalExport.dataChannel<0064>=DATA[64]
SignalExport.dataChannel<0065>=DATA[65]
SignalExport.dataChannel<0066>=DATA[66]
SignalExport.dataChannel<0067>=DATA[67]
SignalExport.dataChannel<0068>=DATA[68]
SignalExport.dataChannel<0069>=DATA[69]
SignalExport.dataChannel<0070>=DATA[70]
SignalExport.dataChannel<0071>=DATA[71]
SignalExport.dataChannel<0072>=DATA[72]
SignalExport.dataChannel<0073>=DATA[73]
SignalExport.dataChannel<0074>=DATA[74]
SignalExport.dataChannel<0075>=DATA[75]
SignalExport.dataChannel<0076>=DATA[76]
SignalExport.dataChannel<0077>=DATA[77]
SignalExport.dataChannel<0078>=DATA[78]
SignalExport.dataChannel<0079>=DATA[79]
SignalExport.dataChannel<0080>=DATA[80]
SignalExport.dataChannel<0081>=DATA[81]
SignalExport.dataChannel<0082>=DATA[82]
SignalExport.dataChannel<0083>=DATA[83]
SignalExport.dataChannel<0084>=DATA[84]
SignalExport.dataChannel<0085>=DATA[85]
SignalExport.dataChannel<0086>=DATA[86]
SignalExport.dataChannel<0087>=DATA[87]
SignalExport.dataChannel<0088>=DATA[88]
SignalExport.dataChannel<0089>=DATA[89]
SignalExport.dataChannel<0090>=DATA[90]
SignalExport.dataChannel<0091>=DATA[91]
SignalExport.dataChannel<0092>=DATA[92]
SignalExport.dataChannel<0093>=DATA[93]
SignalExport.dataChannel<0094>=DATA[94]
SignalExport.dataChannel<0095>=DATA[95]
SignalExport.dataChannel<0096>=DATA[96]
SignalExport.dataChannel<0097>=DATA[97]
SignalExport.dataChannel<0098>=DATA[98]
SignalExport.dataChannel<0099>=DATA[99]
SignalExport.dataChannel<0100>=DATA[100]
SignalExport.dataChannel<0101>=DATA[101]
SignalExport.dataChannel<0102>=DATA[102]
SignalExport.dataChannel<0103>=DATA[103]
SignalExport.dataChannel<0104>=DATA[104]
SignalExport.dataChannel<0105>=DATA[105]
SignalExport.dataChannel<0106>=DATA[106]
SignalExport.dataChannel<0107>=DATA[107]
SignalExport.dataChannel<0108>=DATA[108]
SignalExport.dataChannel<0109>=DATA[109]
SignalExport.dataChannel<0110>=DATA[110]
SignalExport.dataChannel<0111>=DATA[111]
SignalExport.dataChannel<0112>=DATA[112]
SignalExport.dataChannel<0113>=DATA[113]
SignalExport.dataChannel<0114>=DATA[114]
SignalExport.dataChannel<0115>=DATA[115]
SignalExport.dataChannel<0116>=DATA[116]
SignalExport.dataChannel<0117>=DATA[117]
SignalExport.dataChannel<0118>=DATA[118]
SignalExport.dataChannel<0119>=DATA[119]
SignalExport.dataChannel<0120>=DATA[120]
SignalExport.dataChannel<0121>=DATA[121]
SignalExport.dataChannel<0122>=DATA[122]
SignalExport.dataChannel<0123>=DATA[123]
SignalExport.dataChannel<0124>=DATA[124]
SignalExport.dataChannel<0125>=DATA[125]
SignalExport.dataChannel<0126>=DATA[126]
SignalExport.dataChannel<0127>=DATA[127]
SignalExport.dataChannel<0128>=DATA[128]
SignalExport.dataChannel<0129>=DATA[129]
SignalExport.dataChannel<0130>=DATA[130]
SignalExport.dataChannel<0131>=DATA[131]
SignalExport.dataChannel<0132>=DATA[132]
SignalExport.dataChannel<0133>=DATA[133]
SignalExport.dataChannel<0134>=DATA[134]
SignalExport.dataChannel<0135>=DATA[135]
SignalExport.dataChannel<0136>=DATA[136]
SignalExport.dataChannel<0137>=DATA[137]
SignalExport.dataChannel<0138>=DATA[138]
SignalExport.dataChannel<0139>=DATA[139]
SignalExport.dataChannel<0140>=DATA[140]
SignalExport.dataChannel<0141>=DATA[141]
SignalExport.dataChannel<0142>=DATA[142]
SignalExport.dataChannel<0143>=DATA[143]
SignalExport.dataChannel<0144>=DATA[144]
SignalExport.dataChannel<0145>=DATA[145]
SignalExport.dataChannel<0146>=DATA[146]
SignalExport.dataChannel<0147>=DATA[147]
SignalExport.dataChannel<0148>=DATA[148]
SignalExport.dataChannel<0149>=DATA[149]
SignalExport.dataChannel<0150>=DATA[150]
SignalExport.dataChannel<0151>=DATA[151]
SignalExport.dataChannel<0152>=DATA[152]
SignalExport.dataChannel<0153>=DATA[153]
SignalExport.dataChannel<0154>=DATA[154]
SignalExport.dataChannel<0155>=DATA[155]
SignalExport.dataChannel<0156>=DATA[156]
SignalExport.dataChannel<0157>=DATA[157]
SignalExport.dataChannel<0158>=DATA[158]
SignalExport.dataChannel<0159>=DATA[159]
SignalExport.dataChannel<0160>=DATA[160]
SignalExport.dataChannel<0161>=DATA[161]
SignalExport.dataChannel<0162>=DATA[162]
SignalExport.dataChannel<0163>=DATA[163]
SignalExport.dataChannel<0164>=DATA[164]
SignalExport.dataChannel<0165>=DATA[165]
SignalExport.dataChannel<0166>=DATA[166]
SignalExport.dataChannel<0167>=DATA[167]
SignalExport.dataChannel<0168>=DATA[168]
SignalExport.dataChannel<0169>=DATA[169]
SignalExport.dataChannel<0170>=DATA[170]
SignalExport.dataChannel<0171>=DATA[171]
SignalExport.dataChannel<0172>=DATA[172]
SignalExport.dataChannel<0173>=DATA[173]
SignalExport.dataChannel<0174>=DATA[174]
SignalExport.dataChannel<0175>=DATA[175]
SignalExport.dataChannel<0176>=DATA[176]
SignalExport.dataChannel<0177>=DATA[177]
SignalExport.dataChannel<0178>=DATA[178]
SignalExport.dataChannel<0179>=DATA[179]
SignalExport.dataChannel<0180>=DATA[180]
SignalExport.dataChannel<0181>=DATA[181]
SignalExport.dataChannel<0182>=DATA[182]
SignalExport.dataChannel<0183>=DATA[183]
SignalExport.dataChannel<0184>=DATA[184]
SignalExport.dataChannel<0185>=DATA[185]
SignalExport.dataChannel<0186>=DATA[186]
SignalExport.dataChannel<0187>=DATA[187]
SignalExport.dataChannel<0188>=DATA[188]
SignalExport.dataChannel<0189>=DATA[189]
SignalExport.dataChannel<0190>=DATA[190]
SignalExport.dataChannel<0191>=DATA[191]
SignalExport.dataChannel<0192>=DATA[192]
SignalExport.dataChannel<0193>=DATA[193]
SignalExport.dataChannel<0194>=DATA[194]
SignalExport.dataChannel<0195>=DATA[195]
SignalExport.dataChannel<0196>=DATA[196]
SignalExport.dataChannel<0197>=DATA[197]
SignalExport.dataChannel<0198>=DATA[198]
SignalExport.dataChannel<0199>=DATA[199]
SignalExport.dataChannel<0200>=DATA[200]
SignalExport.dataChannel<0201>=DATA[201]
SignalExport.dataChannel<0202>=DATA[202]
SignalExport.dataChannel<0203>=DATA[203]
SignalExport.dataChannel<0204>=DATA[204]
SignalExport.dataChannel<0205>=DATA[205]
SignalExport.dataChannel<0206>=DATA[206]
SignalExport.dataChannel<0207>=DATA[207]
SignalExport.dataChannel<0208>=DATA[208]
SignalExport.dataChannel<0209>=DATA[209]
SignalExport.dataChannel<0210>=DATA[210]
SignalExport.dataChannel<0211>=DATA[211]
SignalExport.dataChannel<0212>=DATA[212]
SignalExport.dataChannel<0213>=DATA[213]
SignalExport.dataChannel<0214>=DATA[214]
SignalExport.dataChannel<0215>=DATA[215]
SignalExport.dataChannel<0216>=DATA[216]
SignalExport.dataChannel<0217>=DATA[217]
SignalExport.dataChannel<0218>=DATA[218]
SignalExport.dataChannel<0219>=DATA[219]
SignalExport.dataChannel<0220>=DATA[220]
SignalExport.dataChannel<0221>=DATA[221]
SignalExport.dataChannel<0222>=DATA[222]
SignalExport.dataChannel<0223>=DATA[223]
SignalExport.dataChannel<0224>=DATA[224]
SignalExport.dataChannel<0225>=DATA[225]
SignalExport.dataChannel<0226>=DATA[226]
SignalExport.dataChannel<0227>=DATA[227]
SignalExport.dataChannel<0228>=DATA[228]
SignalExport.dataChannel<0229>=DATA[229]
SignalExport.dataChannel<0230>=DATA[230]
SignalExport.dataChannel<0231>=DATA[231]
SignalExport.dataChannel<0232>=DATA[232]
SignalExport.dataChannel<0233>=DATA[233]
SignalExport.dataChannel<0234>=DATA[234]
SignalExport.dataChannel<0235>=DATA[235]
SignalExport.dataChannel<0236>=DATA[236]
SignalExport.dataChannel<0237>=DATA[237]
SignalExport.dataChannel<0238>=DATA[238]
SignalExport.dataChannel<0239>=DATA[239]
SignalExport.dataChannel<0240>=DATA[240]
SignalExport.dataChannel<0241>=DATA[241]
SignalExport.dataChannel<0242>=DATA[242]
SignalExport.dataChannel<0243>=DATA[243]
SignalExport.dataChannel<0244>=DATA[244]
SignalExport.dataChannel<0245>=DATA[245]
SignalExport.dataChannel<0246>=DATA[246]
SignalExport.dataChannel<0247>=DATA[247]
SignalExport.dataChannel<0248>=DATA[248]
SignalExport.dataChannel<0249>=DATA[249]
SignalExport.dataChannel<0250>=DATA[250]
SignalExport.dataChannel<0251>=DATA[251]
SignalExport.dataChannel<0252>=DATA[252]
SignalExport.dataChannel<0253>=DATA[253]
SignalExport.dataChannel<0254>=DATA[254]
SignalExport.dataChannel<0255>=DATA[255]
SignalExport.dataEqualsTrigger=false
SignalExport.dataPortWidth=256
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPortCount=1
SignalExport.triggerPortIsData<0000>=false
SignalExport.triggerPortWidth<0000>=8
SignalExport.type=ila
top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.ucf
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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "DATA<*" S;
NET "DATA<*" KEEP;
top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.xdc
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#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/x300/coregen_chipscope/chipscope_ila.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_chipscope/chipscope_ila.ncf
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top/x300/coregen_chipscope/chipscope_ila.ngc
+3
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File diff suppressed because one or more lines are too long
top/x300/coregen_chipscope/chipscope_ila.ucf
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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "DATA<*" S;
NET "DATA<*" KEEP;
top/x300/coregen_chipscope/chipscope_ila.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila.v
// /___/ /\ Timestamp : Wed Jan 30 10:07:41 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_ila(
CONTROL,
CLK,
DATA,
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL;
input CLK;
input [255 : 0] DATA;
input [7 : 0] TRIG0;
endmodule
top/x300/coregen_chipscope/chipscope_ila.veo
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila.veo
// /___/ /\ Timestamp : Wed Jan 30 10:07:41 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_ila YourInstanceName (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK), // IN
.DATA(DATA), // IN BUS [255:0]
.TRIG0(TRIG0) // IN BUS [7:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/x300/coregen_chipscope/chipscope_ila.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Jan 30 18:05:25 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=chipscope_ila
CSET constraint_type=external
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=16384
CSET sample_on=Rising
CSET trigger_port_width_1=8
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 529ae269
top/x300/coregen_chipscope/chipscope_ila.xdc
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#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/x300/coregen_chipscope/chipscope_ila.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="chipscope_ila.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fbg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-30T10:07:43" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CE4C98CD1DB11D55C53E652EE111F1A3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_chipscope/chipscope_ila_flist.txt
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# Output products list for <chipscope_ila>
chipscope_ila.asy
chipscope_ila.cdc
chipscope_ila.constraints/chipscope_ila.ucf
chipscope_ila.constraints/chipscope_ila.xdc
chipscope_ila.gise
chipscope_ila.ncf
chipscope_ila.ngc
chipscope_ila.ucf
chipscope_ila.v
chipscope_ila.veo
chipscope_ila.xco
chipscope_ila.xdc
chipscope_ila.xise
chipscope_ila_flist.txt
chipscope_ila_readme.txt
chipscope_ila_xmdf.tcl
top/x300/coregen_chipscope/chipscope_ila_readme.txt
+47
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The following files were generated for 'chipscope_ila' in directory
/home/jblum/coregen_chipscope/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_ila.cdc
* chipscope_ila.constraints/chipscope_ila.ucf
* chipscope_ila.constraints/chipscope_ila.xdc
* chipscope_ila.ncf
* chipscope_ila.ngc
* chipscope_ila.ucf
* chipscope_ila.v
* chipscope_ila.veo
* chipscope_ila.xdc
* chipscope_ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_ila.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* chipscope_ila.gise
* chipscope_ila.xise
Deliver Readme:
Readme file for the IP.
* chipscope_ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_chipscope/chipscope_ila_xmdf.tcl
Executable
+87
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# The package naming convention is <core_name>_xmdf
package provide chipscope_ila_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::chipscope_ila_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::chipscope_ila_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila
}
# ::chipscope_ila_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_chipscope/coregen.cgp
+9
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET package = ffg900
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false