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top/x300/coregen/gige_sfp_mdio/doc/gig_eth_pcs_pma_v11_5_vinfo.html
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<TITLE>gig_eth_pcs_pma_v11_5_vinfo</TITLE>
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<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v11.5
Release Date: December 18, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
This file contains the change log for all released versions of the Xilinx
LogiCORE IP core Ethernet 1000BASE-X PCS/PMA or SGMII.
For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm">www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm</A>
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements, see:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
2. DEVICE SUPPORT
2.1. ISE
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
Virtex-6 devices
Virtex-6 CXT/LXT/SXT/HXT
Virtex-6 Lower Power (-1L) LXT/SXT
Defense Grade Virtex-6Q (XQ) LXT/SXT
Spartan-6 devices
Spartan-6 LX/LXT
Defense Grade Spartan-6Q LX/LXT
All Virtex-5 devices
Virtex-4 devices
Virtex-4 LX/SX/FX
Spartan-3 device families
Spartan-3
Spartan-3A and Spartan-3AN
Spartan-3A DSP
Spartan-3E
2.2. VIVADO
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
3. NEW FEATURE HISTORY
3.1 ISE
v11.5
- ISE 14.4 software support
- GT updates for Spartan-7,Series-7 and Virtex -6 Tranceivers.
v11.4
- ISE 14.2 software support
- Support for Zynq Devices
v11.3
- ISE 14.1 software support
- Support for Artix7 Devices
- Support for Virtex-7 HT Devices
v11.2
- ISE 13.4 software support
- Added programability through configuration vector
v11.1
- ISE 13.1 software support
- Updated status vector
- SGMII PHY mode
- Support for Kintex7 Devices
- Support for Virtex7 Devices
3.2 Vivado
v11.5
- Vivado 2012.4 software support
- GT updates for Series-7 transceivers.
v11.4
- Vivado 2012.2 software support
- Initial public release
- Block level user editable logic delivered as part of the core
4. RESOLVED ISSUES
4.1 ISE
The following issues are resolved in the indicated IP versions:
v11.5
- None
v11.4
- None
v11.3
- AR: 45676
- AR: 46123
v11.2
- AR: 42672
- AR: 36961
- AR: 42842
- AR: 43421
- AR: 43482
v11.1
- AR: 36957
- AR: 36961
- AR: 35681
4.2 Vivado
v11.5
- None
v11.4
- None
5. KNOWN ISSUES & LIMITATIONS
- For a comprehensive listing of Known Issues for this core, please see the IP
Release Notes Guide,
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Feedback on this IP core may also be submitted under the "Leave Feedback"
menu item in Vivado/PlanAhead.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/18/2012 Xilinx, Inc. 11.5 ISE 14.4 and Vivado 2012.4.
GT updates and CR closures.
07/25/2012 Xilinx, Inc. 11.4 ISE 14.2 and Vivado 2012.2.
Support for Zynq Devices. Sync LVDS Solution
04/24/2012 Xilinx, Inc. 11.3 ISE 14.1, Artix-7 and Vivado 2012.1 support
01/18/2012 Xilinx, Inc. 11.2 ISE 13.4 Support
09/06/2011 Xilinx, Inc. 11.1 Rev 1 Patch release for ISE 13.1
03/01/2011 Xilinx, Inc. 11.1 ISE 13.1 and Virtex-7 / Kintex-7 support
07/30/2010 Xilinx, Inc. 10.5 Rev 1 Patch release for ISE 12.2
07/23/2010 Xilinx, Inc. 10.5 ISE 12.2 support and Virtex-6 LVDS I/O
04/19/2010 Xilinx, Inc. 10.4 Release for ISE 12.1
03/09/2010 Xilinx, Inc. 10.3 Rev 1 Patch release for ISE 11.5
09/16/2009 Xilinx, Inc. 10.3 11.3, Virtex-6 HXT and Lower Power support
06/24/2009 Xilinx, Inc. 10.2 Release for ISE 11.2 and Spartan-6 support
04/27/2009 Xilinx, Inc. 10.1 Release for ISE 11.1
03/24/2008 Xilinx, Inc. 9.1 Release for ISE 10.1
08/15/2007 Xilinx, Inc. 9.0 Release for 9.2i
04/02/2007 Xilinx, Inc. 8.1 Rev 1 Spartan-3A DSP support
03/05/2007 Xilinx, Inc. 8.1 Release for ISE 9.1i
10/26/2006 Xilinx, Inc. 8.0 Release for Virtex-5 and Spartan-3A
07/19/2006 Xilinx, Inc. 7.1 Release for ISE 8.2i
05/22/2006 Xilinx, Inc. 7.0 Rev 1 Virtex-4 FX CES4 update
01/18/2006 Xilinx, Inc. 7.0 Release for ISE 8.1i
06/24/2005 Xilinx, Inc. 6.0 patch1 Patch release
05/12/2005 Xilinx, Inc. 6.0 Release for ISE 7.1i
09/30/2004 Xilinx, Inc. 5.0 Release for ISE 6.3i
================================================================================
8. LEGAL DISCLAIMER
(c) Copyright 2004 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_block.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This Core Block Level wrapper connects the core to a
// Series-7 Transceiver.
//
//
// ------------------------------------------------------------
// | Core Block wrapper |
// | |
// | ------------------ ----------------- |
// | | Core | | Transceiver | |
// | | | | | |
// | | | | | |
// | | | | | |
// ---------->| GMII |--------->| TXP |-------->
// | | Tx | | TXN | |
// | | | | | |
// | | | | | |
// | | | | | |
// | | | | | |
// | | | | | |
// | | GMII | | RXP | |
// <----------| Rx |<---------| RXN |<--------
// | | | | | |
// | ------------------ ----------------- |
// | |
// ------------------------------------------------------------
//
//
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// The module declaration for the Core Block wrapper.
//------------------------------------------------------------------------------
module gige_sfp_mdio_block
(
// Transceiver Interface
//----------------------
input gtrefclk, // Very high quality 125MHz clock for GT transceiver.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output txoutclk, // txoutclk from GT transceiver (62.5MHz)
output resetdone, // The GT transceiver has completed its reset cycle
input mmcm_locked, // locked indication from MMCM
input userclk, // 62.5MHz global clock.
input userclk2, // 125MHz global clock.
input independent_clock_bufg,// 200MHz Independent clock,
input pma_reset, // transceiver PMA reset signal
// GMII Interface
//---------------
input [7:0] gmii_txd, // Transmit data from client MAC.
input gmii_tx_en, // Transmit control signal from client MAC.
input gmii_tx_er, // Transmit control signal from client MAC.
output [7:0] gmii_rxd, // Received Data to client MAC.
output gmii_rx_dv, // Received control signal to client MAC.
output gmii_rx_er, // Received control signal to client MAC.
output gmii_isolate, // Tristate control to electrically isolate GMII.
// Management: MDIO Interface
//---------------------------
input mdc, // Management Data Clock
input mdio_i, // Management Data In
output mdio_o, // Management Data Out
output mdio_t, // Management Data Tristate
input [4:0] phyad, // Port address for MDIO.
input [4:0] configuration_vector, // Alternative to MDIO interface.
input configuration_valid, // Validation signal for Config vector
// General IO's
//-------------
output [15:0] status_vector, // Core status.
input reset, // Asynchronous reset for entire core.
input signal_detect // Input from PMD to indicate presence of optical input.
);
//---------------------------------------------------------------------------
// Internal signals used in this block level wrapper.
//---------------------------------------------------------------------------
// Core <=> Transceiver interconnect
wire plllock; // The PLL Locked status of the Transceiver
wire mgt_rx_reset; // Reset for the receiver half of the Transceiver
wire mgt_tx_reset; // Reset for the transmitter half of the Transceiver
wire [1:0] rxbufstatus; // Elastic Buffer Status (bit 1 asserted indicates overflow or underflow).
wire rxchariscomma; // Comma detected in RXDATA.
wire rxcharisk; // K character received (or extra data bit) in RXDATA.
wire [2:0] rxclkcorcnt; // Indicates clock correction.
wire [7:0] rxdata; // Data after 8B/10B decoding.
wire rxrundisp; // Running Disparity after current byte, becomes 9th data bit when RXNOTINTABLE='1'.
wire rxdisperr; // Disparity-error in RXDATA.
wire rxnotintable; // Non-existent 8B/10 code indicated.
wire txbuferr; // TX Buffer error (overflow or underflow).
wire loopback; // Set the Transceiver for loopback.
wire powerdown; // Powerdown the Transceiver
wire txchardispmode; // Set running disparity for current byte.
wire txchardispval; // Set running disparity value.
wire txcharisk; // K character transmitted in TXDATA.
wire [7:0] txdata; // Data for 8B/10B encoding.
wire enablealign; // Allow the transceivers to serially realign to a comma character.
//---------------------------------------------------------------------------
// Instantiate the core
//---------------------------------------------------------------------------
gige_sfp_mdio gig_eth_pcs_pma_core
(
.mgt_rx_reset (mgt_rx_reset),
.mgt_tx_reset (mgt_tx_reset),
.userclk (userclk2),
.userclk2 (userclk2),
.dcm_locked (mmcm_locked),
.rxbufstatus (rxbufstatus),
.rxchariscomma (rxchariscomma),
.rxcharisk (rxcharisk),
.rxclkcorcnt (rxclkcorcnt),
.rxdata (rxdata),
.rxdisperr (rxdisperr),
.rxnotintable (rxnotintable),
.rxrundisp (rxrundisp),
.txbuferr (txbuferr),
.powerdown (powerdown),
.txchardispmode (txchardispmode),
.txchardispval (txchardispval),
.txcharisk (txcharisk),
.txdata (txdata),
.enablealign (enablealign),
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_isolate (gmii_isolate),
.mdc (mdc),
.mdio_in (mdio_i),
.mdio_out (mdio_o),
.mdio_tri (mdio_t),
.phyad (phyad),
.configuration_vector (configuration_vector),
.configuration_valid (configuration_valid),
.status_vector (status_vector),
.reset (reset),
.signal_detect (signal_detect)
);
//---------------------------------------------------------------------------
// Component Instantiation for the Series-7 Transceiver wrapper
//---------------------------------------------------------------------------
gige_sfp_mdio_transceiver transceiver_inst (
.encommaalign (enablealign),
.loopback (loopback),
.powerdown (powerdown),
.usrclk (userclk),
.usrclk2 (userclk2),
.independent_clock (independent_clock_bufg),
.data_valid (status_vector[1]),
.txreset (mgt_tx_reset),
.txchardispmode (txchardispmode),
.txchardispval (txchardispval),
.txcharisk (txcharisk),
.txdata (txdata),
.rxreset (mgt_rx_reset),
.rxchariscomma (rxchariscomma),
.rxcharisk (rxcharisk),
.rxclkcorcnt (rxclkcorcnt),
.rxdata (rxdata),
.rxdisperr (rxdisperr),
.rxnotintable (rxnotintable),
.rxrundisp (rxrundisp),
.rxbuferr (rxbufstatus[1]),
.txbuferr (txbuferr),
.plllkdet (plllock),
.txoutclk (txoutclk),
.txn (txn),
.txp (txp),
.rxn (rxn),
.rxp (rxp),
.gtrefclk (gtrefclk),
.pmareset (pma_reset),
.mmcm_locked (mmcm_locked),
.resetdone (resetdone)
);
// Unused
assign rxbufstatus[0] = 1'b0;
// Loopback is performed in the core itself. To alternatively use
// Transceiver loopback, please drive this port appropriately.
assign loopback = 1'b0;
endmodule // gige_sfp_mdio_block
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_example_design.ucf
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# This value should be modified to match your device
CONFIG PART = xc7k325t-ffg900-2;
#***********************************************************
# The following constraints target the Transceiver Physical*
# Interface which is instantiated in the Example Design. *
#***********************************************************
#-----------------------------------------------------------
# Clock source used for the IDELAY Controller (if present) -
# and for the transceiver reset circuitry -
#-----------------------------------------------------------
NET "independent_clock" TNM_NET = "independent_clock";
TIMESPEC "ts_independent_clock" = PERIOD "independent_clock" 5000 ps HIGH 50 %;
#-----------------------------------------------------------
# PCS/PMA Clock period Constraints: please do not relax -
#-----------------------------------------------------------
NET "gtrefclk" TNM_NET = "gtrefclk";
TIMESPEC "ts_gtrefclk" = PERIOD "gtrefclk" 8 ns HIGH 50 %;
NET "txoutclk" TNM_NET = "txoutclk";
TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 16 ns HIGH 50 %;
#-----------------------------------------------------------
# Transceiver I/O placement: -
#-----------------------------------------------------------
#INST "gtrefclk_p" LOC = "G7";
#INST "gtrefclk_n" LOC = "G8";
INST "core_wrapper?transceiver_inst?gtwizard_inst?gtwizard_i?gt0_gtwizard_i?gtxe2_i" LOC = "GTXE2_CHANNEL_X0Y10";
#-----------------------------------------------------------
# Setting TIG constraints for rx and tx sync sms -
#-----------------------------------------------------------
INST "*/*/*/gt0_txresetfsm_i/mmcm_lock_int*" TNM = tx_mmcm_lock_delay_grp;
INST "*/*/*/gt0_txresetfsm_i/*mmcm_lock_reclocke*" TNM = tx_mmcm_lock_reclocked_delay_grp;
TIMESPEC TS_TX_MMCM_LOCK = FROM tx_mmcm_lock_delay_grp TO tx_mmcm_lock_reclocked_delay_grp TIG;
INST "*/*/*/gt0_txresetfsm_i/time_out_wait_bypass" TNM = tx_time_out_wait_bypass_delay_grp;
INST "*/*/*/gt0_txresetfsm_i/time_out_wait_bypass_*" TNM = tx_time_out_wait_bypass_delay_sync_grp;
TIMESPEC TS_TX_TIME_OUT_WAIT_SYNC = FROM tx_time_out_wait_bypass_delay_grp TO tx_time_out_wait_bypass_delay_sync_grp TIG;
INST "*/*/*/gt0_txresetfsm_i/*run_phase_alignment_int" TNM = tx_run_phase_alignment_grp;
INST "*/*/*/gt0_txresetfsm_i/*run_phase_alignment_int_*" TNM = tx_phase_alignment_grp;
TIMESPEC TS_TX_PHASE_ALIGNMENT = FROM tx_run_phase_alignment_grp TO tx_phase_alignment_grp TIG;
INST "*/*/*/gt0_txresetfsm_i/*tx_fsm_reset_done_int" TNM = tx_fsm_reset_done_int_grp;
INST "*/*/*/gt0_txresetfsm_i/*tx_fsm_reset_done_int_*" TNM = tx_fsm_reset_done_grp;
TIMESPEC TS_TX_FSM_RESET_DONE = FROM tx_fsm_reset_done_int_grp TO tx_fsm_reset_done_grp TIG;
INST "*/*/*/gt0_txresetfsm_i/TXRESETDONE*" TNM = tx_reset_done_int_grp;
INST "*/*/*/gt0_txresetfsm_i/*txresetdone_*" TNM = tx_reset_done_grp;
TIMESPEC TS_TX_RESET_DONE = FROM tx_reset_done_int_grp TO tx_reset_done_grp TIG;
INST "*/*/*/gt0_rxresetfsm_i/time_out_wait_bypass" TNM = rx_time_out_wait_bypass_delay_grp;
INST "*/*/*/gt0_rxresetfsm_i/time_out_wait_bypass_*" TNM = rx_time_out_wait_bypass_delay_sync_grp;
TIMESPEC TS_RX_TIME_OUT_WAIT_SYNC = FROM rx_time_out_wait_bypass_delay_grp TO rx_time_out_wait_bypass_delay_sync_grp TIG;
INST "*/*/*/gt0_rxresetfsm_i/*run_phase_alignment_int" TNM = rx_run_phase_alignment_grp;
INST "*/*/*/gt0_rxresetfsm_i/*run_phase_alignment_int_*" TNM = rx_phase_alignment_grp;
TIMESPEC TS_RX_PHASE_ALIGNMENT = FROM rx_run_phase_alignment_grp TO rx_phase_alignment_grp TIG;
INST "*/*/*/gt0_rxresetfsm_i/*rx_fsm_reset_done_int" TNM = rx_fsm_reset_done_int_grp;
INST "*/*/*/gt0_rxresetfsm_i/*rx_fsm_reset_done_int_*" TNM = rx_fsm_reset_done_grp;
TIMESPEC TS_RX_FSM_RESET_DONE = FROM rx_fsm_reset_done_int_grp TO rx_fsm_reset_done_grp TIG;
INST "*/*/*/gt0_rxresetfsm_i/RXRESETDONE*" TNM = rx_reset_done_int_grp;
INST "*/*/*/gt0_rxresetfsm_i/*rxresetdone_*" TNM = rx_reset_done_grp;
TIMESPEC TS_RX_RESET_DONE = FROM rx_reset_done_int_grp TO rx_reset_done_grp TIG;
INST "*/*/sync_block_data_valid/data_sync" TNM = data_valid_reg_delay_grp;
INST "*/*/*ata_valid*" TNM = data_valid_delay_grp_2;
TIMESPEC TS_TX_DATA_VALID_opt = FROM data_valid_delay_grp_2 TO data_valid_reg_delay_grp TIG;
#***********************************************************
# The following constraints target the GMII implemented in *
# the Example Design. *
#***********************************************************
# If the GMII is intended to be an internal interface, *
# the GMII signals can be connected directly to user *
# logic and all of the following constraints in this file *
# should be removed. *
# *
# If the GMII is intended to be an external interface, *
# all of the following constraints in this file should be *
# maintained. *
#***********************************************************
#-----------------------------------------------------------
# GMII IOSTANDARD Constraints: please select an I/O -
# Standard (LVTTL is suggested). -
#-----------------------------------------------------------
INST "gmii_txd<?>" IOSTANDARD = LVCMOS33;
INST "gmii_tx_en" IOSTANDARD = LVCMOS33;
INST "gmii_tx_er" IOSTANDARD = LVCMOS33;
INST "gmii_rxd<?>" IOSTANDARD = LVCMOS33;
INST "gmii_rx_dv" IOSTANDARD = LVCMOS33;
INST "gmii_rx_er" IOSTANDARD = LVCMOS33;
INST "gmii_tx_clk" IOSTANDARD = LVCMOS33;
INST "gmii_rx_clk" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------
# Lock down the GMII Tx signals to the same bank for low -
# skew. This is an example placement only. -
#-----------------------------------------------------------
#-----------------------------------------------------------
# To Adjust GMII Tx Input Setup/Hold Timing -
#-----------------------------------------------------------
# These constraints will be set at a later date when device speed files have matured
#INST "delay_gmii_tx_en" IDELAY_VALUE = 0;
#INST "delay_gmii_tx_er" IDELAY_VALUE = 0;
#INST "gmii_data_bus[7].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[6].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[5].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[4].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[3].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[2].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[1].delay_gmii_txd" IDELAY_VALUE = 0;
#INST "gmii_data_bus[0].delay_gmii_txd" IDELAY_VALUE = 0;
#-----------------------------------------------------------
# To check (analyze) GMII Tx Input Setup/Hold Timing -
#-----------------------------------------------------------
INST "gmii_txd*" TNM = IN_GMII;
INST "gmii_tx_en" TNM = IN_GMII;
INST "gmii_tx_er" TNM = IN_GMII;
# This check will be enabled at a later date when device speed files have matured
#TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_tx_clk";
#-----------------------------------------------------------
# Fast Skew maximises output setup and hold timing -
#-----------------------------------------------------------
INST "gmii_rxd<?>" SLEW = FAST;
INST "gmii_rx_dv" SLEW = FAST;
INST "gmii_rx_er" SLEW = FAST;
INST "gmii_rx_clk" SLEW = FAST;
#-----------------------------------------------------------
# GMII Transmitter Constraints: place flip-flops in IOB -
#-----------------------------------------------------------
INST "gmii_txd_iff*" IOB = true;
INST "gmii_tx_en_iff" IOB = true;
INST "gmii_tx_er_iff" IOB = true;
#-----------------------------------------------------------
# GMII Receiver Constraints: place flip-flops in IOB -
#-----------------------------------------------------------
INST "gmii_rxd_obuf*" IOB = true;
INST "gmii_rx_dv_obuf" IOB = true;
INST "gmii_rx_er_obuf" IOB = true;
#-----------------------------------------------------------
# GMII Clock period Constraints: please do not relax -
#-----------------------------------------------------------
# Describe the GMII Tx clock at the input pads
NET "gmii_tx_clk" TNM_NET = "gmii_tx_clk";
TIMESPEC "ts_gmii_tx_clk" = PERIOD "gmii_tx_clk" 8000 ps HIGH 50 %;
#-----------------------------------------------------------
# GMII Tx Elastic Buffer Constraints -
#-----------------------------------------------------------
# Identify clock domain crossing registers
INST "tx_elastic_buffer_inst/rd_addrgray*" TNM = "rd_graycode";
INST "tx_elastic_buffer_inst/wr_addrgray*" TNM = "wr_graycode";
# Control Gray Code delay and skew across clock boundary
TIMESPEC "ts_tx_skew_control1" = FROM "rd_graycode" TO "FFS" 6 ns DATAPATHONLY;
TIMESPEC "ts_tx_skew_control2" = FROM "wr_graycode" TO "FFS" 6 ns DATAPATHONLY;
# Constrain between Distributed Memory (output data) and the 1st set of flip-flops
INST "tx_elastic_buffer_inst/txd_fifo_reg1*" TNM = "TX_FIFO_SAMPLE";
INST "tx_elastic_buffer_inst/tx_en_fifo_reg1" TNM = "TX_FIFO_SAMPLE";
INST "tx_elastic_buffer_inst/tx_er_fifo_reg1" TNM = "TX_FIFO_SAMPLE";
TIMESPEC "ts_tx_rams_to_ffs" = FROM "RAMS" TO "TX_FIFO_SAMPLE" 6 ns DATAPATHONLY;
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_example_design.v
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_example_design.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This is the top level verilog example design for the
// Ethernet SGMII core. The block level wrapper for the
// core is instantiated and the tranceiver clock circuitry is
// created. Additionally, the I/O of the GMII-style
// interface is provided with IOB flip-flops (infered)
// which enables this example design to be implemented
// using the Xilinx tools.
//
// * Please refer to the Getting Started User Guide for
// details of the example design file hierarchy.
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// The module declaration for the example design
//------------------------------------------------------------------------------
module gige_sfp_mdio_example_design
(
// An independent clock source used as the reference clock for an
// IDELAYCTRL (if present) and for the main GT transceiver reset logic.
// This example design assumes that this is of frequency 200MHz.
input independent_clock,
// Tranceiver Interface
//---------------------
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
// GMII Interface (client MAC <=> PCS)
//------------------------------------
input gmii_tx_clk, // Transmit clock from client MAC.
output gmii_rx_clk, // Receive clock to client MAC.
input [7:0] gmii_txd, // Transmit data from client MAC.
input gmii_tx_en, // Transmit control signal from client MAC.
input gmii_tx_er, // Transmit control signal from client MAC.
output [7:0] gmii_rxd, // Received Data to client MAC.
output gmii_rx_dv, // Received control signal to client MAC.
output gmii_rx_er, // Received control signal to client MAC.
// Management: MDIO Interface
//---------------------------
input mdc, // Management Data Clock
input mdio_i, // Management Data In
output mdio_o, // Management Data Out
output mdio_t, // Management Data Tristate
input [4:0] phyad, // Port address for MDIO.
input [4:0] configuration_vector, // Alternative to MDIO interface.
input configuration_valid, // Validation signal for Config vector
// General IO's
//-------------
output reg [15:0] status_vector, // Core status.
input reset, // Asynchronous reset for entire core.
input signal_detect // Input from PMD to indicate presence of optical input.
);
//----------------------------------------------------------------------------
// internal signals used in this top level example design.
//----------------------------------------------------------------------------
// clock generation signals for tranceiver
wire gtrefclk; // gtrefclk routed through an IBUFG.
wire txoutclk; // txoutclk from GT transceiver.
wire txoutclk_bufg; // txoutclk from GT transceiver routed onto global routing.
wire resetdone; // To indicate that the GT transceiver has completed its reset cycle
wire mmcm_locked; // MMCM Locked signal.
wire mmcm_reset; // MMCM reset signal.
wire clkfbout; // MMCM feedback clock
wire clkout0; // MMCM clock0 output (62.5MHz).
wire clkout1; // MMCM clock1 output (125MHz).
wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks
wire userclk2; // 125MHz clock for core reference clock.
(* ASYNC_REG = "TRUE" *)
reg [3:0] pma_reset_pipe; // flip-flop pipeline for reset duration stretch
wire pma_reset; // Synchronous transcevier PMA reset
// An independent clock source used as the reference clock for an
// IDELAYCTRL (if present) and for the main GT transceiver reset logic.
wire independent_clock_bufg;
// Signals used for an IDELAYCTRL
wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL clock domain.
reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse.
reg idelayctrl_reset; // The reset pulse for the IDELAYCTRL.
// GMII signals
wire gmii_tx_clk_bufio; // gmii_tx_clk routed through an BUFIO.
wire gmii_tx_clk_bufr; // gmii_tx_clk_ibuf routed through a BUFR.
wire [7:0] gmii_txd_delay; // Internal gmii_txd signal after IDELAY.
wire gmii_tx_en_delay; // Internal gmii_tx_en signal after IDELAY.
wire gmii_tx_er_delay; // Internal gmii_tx_er signal after IDELAY.
wire gmii_isolate; // internal gmii_isolate signal.
reg [7:0] gmii_txd_iff; // gmii_txd signal for input IOB flip-flop.
reg gmii_tx_en_iff; // gmii_tx_en signal for input IOB flip-flop.
reg gmii_tx_er_iff; // gmii_tx_er signal for input IOB flip-flop.
reg [7:0] gmii_txd_reg; // internal gmii_txd signal.
reg gmii_tx_en_reg; // internal gmii_tx_en signal.
reg gmii_tx_er_reg; // internal gmii_tx_er signal.
wire [7:0] gmii_txd_fifo; // gmii_txd signal after Tx Elastic Buffer.
wire gmii_tx_en_fifo; // gmii_tx_en signal after Tx Elastic Buffer.
wire gmii_tx_er_fifo; // gmii_tx_er signal after Tx Elastic Buffer.
wire [7:0] gmii_rxd_int; // internal gmii_rxd signal.
wire gmii_rx_dv_int; // internal gmii_rx_dv signal.
wire gmii_rx_er_int; // internal gmii_rx_er signal.
wire gmii_rx_clk_obuf; // gmii_rx_clk registered in IOBs prior to an OBUF.
reg [7:0] gmii_rxd_obuf; // gmii_rxd registered in IOBs prior to an OBUF.
reg gmii_rx_dv_obuf; // gmii_rx_dv registered in IOBs prior to an OBUF.
reg gmii_rx_er_obuf; // gmii_rx_er registered in IOBs prior to an OBUF.
// Extra registers to ease IOB placement
wire [15:0] status_vector_int;
//---------------------------------------------------------------------------
// An independent clock source used as the reference clock for an
// IDELAYCTRL (if present) and for the main GT transceiver reset logic.
//---------------------------------------------------------------------------
// Route independent_clock input through a BUFG
BUFG bufg_independent_clock (
.I (independent_clock),
.O (independent_clock_bufg)
);
//---------------------------------------------------------------------------
// Instantiate an IDELAYCTRL and its reset circuitry
//---------------------------------------------------------------------------
// Instantiate the IDELAY Controller.
IDELAYCTRL dlyctrl
(
.RDY (),
.REFCLK (independent_clock_bufg),
.RST (idelayctrl_reset)
);
// Create a synchronous reset in the IDELAYCTRL clock domain.
gige_sfp_mdio_reset_sync idelayctrl_reset_gen (
.clk (independent_clock_bufg),
.reset_in (reset),
.reset_out (idelayctrl_reset_sync)
);
// Reset circuitry for the IDELAYCTRL reset.
// The IDELAYCTRL must experience a pulse which is at least 50 ns in
// duration. This is ten clock cycles of the 200MHz independent_clock.
// Here we drive the reset pulse for 12 clock cycles.
always @(posedge independent_clock_bufg)
begin
if (idelayctrl_reset_sync) begin
idelay_reset_cnt <= 4'b0000;
idelayctrl_reset <= 1'b1;
end
else begin
case (idelay_reset_cnt)
4'b0000 : idelay_reset_cnt <= 4'b0001;
4'b0001 : idelay_reset_cnt <= 4'b0010;
4'b0010 : idelay_reset_cnt <= 4'b0011;
4'b0011 : idelay_reset_cnt <= 4'b0100;
4'b0100 : idelay_reset_cnt <= 4'b0101;
4'b0101 : idelay_reset_cnt <= 4'b0110;
4'b0110 : idelay_reset_cnt <= 4'b0111;
4'b0111 : idelay_reset_cnt <= 4'b1000;
4'b1000 : idelay_reset_cnt <= 4'b1001;
4'b1001 : idelay_reset_cnt <= 4'b1010;
4'b1010 : idelay_reset_cnt <= 4'b1011;
4'b1011 : idelay_reset_cnt <= 4'b1100;
default : idelay_reset_cnt <= 4'b1100;
endcase
if (idelay_reset_cnt === 4'b1100) begin
idelayctrl_reset <= 1'b0;
end
else begin
idelayctrl_reset <= 1'b1;
end
end
end
//---------------------------------------------------------------------------
// Transceiver Clock Management
//---------------------------------------------------------------------------
// Clock circuitry for the Transceiver uses a differential input clock.
// gtrefclk is routed to the tranceiver.
IBUFDS_GTE2 ibufds_gtrefclk (
.I (gtrefclk_p),
.IB (gtrefclk_n),
.CEB (1'b0),
.O (gtrefclk),
.ODIV2 ()
);
// Route txoutclk input through a BUFG
BUFG bufg_txoutclk (
.I (txoutclk),
.O (txoutclk_bufg)
);
// The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
// routed to an MMCM module where it is used to create phase and frequency
// related 62.5MHz and 125MHz clock sources
MMCME2_ADV # (
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (16.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (16),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.5),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (16.0),
.REF_JITTER1 (0.010)
) mmcm_adv_inst (
// Output clocks
.CLKFBOUT (clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (clkout0),
.CLKOUT0B (),
.CLKOUT1 (clkout1),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (txoutclk_bufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_locked),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_reset)
);
assign mmcm_reset = reset||!resetdone;
// This 62.5MHz clock is placed onto global clock routing and is then used
// for tranceiver TXUSRCLK/RXUSRCLK.
BUFG bufg_userclk (
.I (clkout1),
.O (userclk)
);
// This 125MHz clock is placed onto global clock routing and is then used
// to clock all Ethernet core logic.
BUFG bufg_userclk2 (
.I (clkout0),
.O (userclk2)
);
//---------------------------------------------------------------------------
// Transceiver PMA reset circuitry
//---------------------------------------------------------------------------
always@(posedge independent_clock_bufg or posedge reset)
if (reset == 1'b1)
pma_reset_pipe <= 4'b1111;
else
pma_reset_pipe <= {pma_reset_pipe[2:0], reset};
assign pma_reset = pma_reset_pipe[3];
//----------------------------------------------------------------------------
// Instantiate the Core Block (core wrapper).
//----------------------------------------------------------------------------
gige_sfp_mdio_block core_wrapper
(
.gtrefclk (gtrefclk),
.txp (txp),
.txn (txn),
.rxp (rxp),
.rxn (rxn),
.txoutclk (txoutclk),
.resetdone (resetdone),
.mmcm_locked (mmcm_locked),
.userclk (userclk),
.userclk2 (userclk2),
.independent_clock_bufg(independent_clock_bufg),
.pma_reset (pma_reset),
.gmii_txd (gmii_txd_fifo),
.gmii_tx_en (gmii_tx_en_fifo),
.gmii_tx_er (gmii_tx_er_fifo),
.gmii_rxd (gmii_rxd_int),
.gmii_rx_dv (gmii_rx_dv_int),
.gmii_rx_er (gmii_rx_er_int),
.gmii_isolate (gmii_isolate),
.mdc (mdc),
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
.phyad (phyad),
.configuration_vector (configuration_vector),
.configuration_valid (configuration_valid),
.status_vector (status_vector_int),
.reset (reset),
.signal_detect (signal_detect)
);
//---------------------------------------------------------------------------
// GMII transmitter clock logic
//---------------------------------------------------------------------------
// Route gmii_tx_clk from PAD through a BUFIO Buffer
BUFIO receive_gmii_tx_clk (
.I (gmii_tx_clk),
.O (gmii_tx_clk_bufio)
);
// Route gmii_tx_clk through a BUFR onto regional clock routing
BUFR drive_tx_clk (
.I (gmii_tx_clk),
.CE (1'b1),
.CLR (1'b0),
.O (gmii_tx_clk_bufr)
);
//---------------------------------------------------------------------------
// GMII transmitter data logic
//---------------------------------------------------------------------------
// An IOBDELAY is used with Series-7 devices to meet the GMII input
// setup and hold specifications. The data is delayed so to compensate for
// the clock routing delay so that the GMII input data will be correctly
// sampled at the IOB flip-flops
// Please modify the value of the IOBDELAY according to your design.
// The value in this file will be overridden with the value in the
// UCF. For more information, please refer to the User Guide.
// The tap delay values can also be adjusted to compensate for PCB routing
// deskew.
// IODELAY for GMII_TXD
genvar i;
generate for (i=0; i<8; i=i+1)
begin : gmii_data_bus
IODELAYE1 # (
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0)
) delay_gmii_txd (
.IDATAIN (gmii_txd[i]),
.ODATAIN (1'b0),
.DATAOUT (gmii_txd_delay[i]),
.DATAIN (1'b0),
.CNTVALUEIN (5'b0),
.CNTVALUEOUT (),
.CLKIN (1'b0),
.CINVCTRL (1'b0),
.T (1'b1),
.C (1'b0),
.CE (1'b0),
.INC (1'b0),
.RST (1'b0)
);
end
endgenerate
// IODELAY for GMII_TX_EN
IODELAYE1 # (
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0)
) delay_gmii_tx_en (
.IDATAIN (gmii_tx_en),
.ODATAIN (1'b0),
.DATAOUT (gmii_tx_en_delay),
.DATAIN (1'b0),
.CNTVALUEIN (5'b0),
.CNTVALUEOUT (),
.CLKIN (1'b0),
.CINVCTRL (1'b0),
.T (1'b1),
.C (1'b0),
.CE (1'b0),
.INC (1'b0),
.RST (1'b0)
);
// IODELAY for GMII_TX_ER
IODELAYE1 # (
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0)
) delay_gmii_tx_er (
.IDATAIN (gmii_tx_er),
.ODATAIN (1'b0),
.DATAOUT (gmii_tx_er_delay),
.DATAIN (1'b0),
.CNTVALUEIN (5'b0),
.CNTVALUEOUT (),
.CLKIN (1'b0),
.CINVCTRL (1'b0),
.T (1'b1),
.C (1'b0),
.CE (1'b0),
.INC (1'b0),
.RST (1'b0)
);
// Drive input GMII through IOB input flip-flops (inferred).
always @ (posedge gmii_tx_clk_bufio)
begin
gmii_txd_iff <= gmii_txd_delay;
gmii_tx_en_iff <= gmii_tx_en_delay;
gmii_tx_er_iff <= gmii_tx_er_delay;
end
// Reclock onto regional clock routing
always @ (posedge gmii_tx_clk_bufr)
begin
gmii_txd_reg <= gmii_txd_iff;
gmii_tx_en_reg <= gmii_tx_en_iff;
gmii_tx_er_reg <= gmii_tx_er_iff;
end
// Component Instantiation for the Transmitter Elastic Buffer
gige_sfp_mdio_tx_elastic_buffer tx_elastic_buffer_inst
(
.reset (reset),
.gmii_tx_clk_wr (gmii_tx_clk_bufr),
.gmii_txd_wr (gmii_txd_reg),
.gmii_tx_en_wr (gmii_tx_en_reg),
.gmii_tx_er_wr (gmii_tx_er_reg),
.gmii_tx_clk_rd (userclk2),
.gmii_txd_rd (gmii_txd_fifo),
.gmii_tx_en_rd (gmii_tx_en_fifo),
.gmii_tx_er_rd (gmii_tx_er_fifo)
);
//---------------------------------------------------------------------------
// GMII receiver clock logic
//---------------------------------------------------------------------------
// This instantiates a DDR output register. This is a nice way to
// drive the GMII output clock since the clock-to-PAD delay will the
// same as that of data driven from an IOB Ouput flip-flop. This is
// set to produce an inverted clock w.r.t. userclk2 so that clock
// rising edge appears in the centre of GMII data.
ODDR rx_clk_ddr_iob (
.Q (gmii_rx_clk_obuf),
.C (userclk2),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.R (1'b0),
.S (1'b0)
);
// Finally the clock is driven onto the PAD from an Output Buffer.
OBUFT drive_gmii_gtx_clk (
.I (gmii_rx_clk_obuf),
.O (gmii_rx_clk),
.T (gmii_isolate)
);
//---------------------------------------------------------------------------
// GMII receiver data logic
//---------------------------------------------------------------------------
// Drive Rx GMII signals through IOB output flip-flops (inferred).
always @ (posedge userclk2)
begin
gmii_rxd_obuf <= gmii_rxd_int;
gmii_rx_dv_obuf <= gmii_rx_dv_int;
gmii_rx_er_obuf <= gmii_rx_er_int;
end
// drive GMII Rx signals through output PADS.
OBUFT rx_data_valid (
.I (gmii_rx_dv_obuf),
.O (gmii_rx_dv),
.T (gmii_isolate)
);
OBUFT rx_data_error (
.I (gmii_rx_er_obuf),
.O (gmii_rx_er),
.T (gmii_isolate)
);
genvar j;
generate for (j=0; j<8; j=j+1)
begin : rx_data_bus
OBUFT rx_data_bits (
.I (gmii_rxd_obuf[j]),
.O (gmii_rxd[j]),
.T (gmii_isolate));
end
endgenerate
//---------------------------------------------------------------------------
// Extra registers to ease IOB placement
//---------------------------------------------------------------------------
always @ (posedge userclk2)
begin
status_vector <= status_vector_int;
end
endmodule // gige_sfp_mdio_example_design
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_mod.v
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_mod.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This package holds the top level component declaration
// for the Ethernet 1000BASE-X PCS/PMA core.
module gige_sfp_mdio
(
// Core <=> tranceiver Interface
//------------------------------
output mgt_rx_reset, // tranceiver connection: reset for the receiver half of the tranceiver
output mgt_tx_reset, // tranceiver connection: reset for the transmitter half of the tranceiver
input userclk, // Routed to TXUSERCLK and RXUSERCLK of Transceiver.
input userclk2, // Routed to TXUSERCLK2 and RXUSERCLK2 of Transceiver.
input dcm_locked, // LOCKED signal from DCM.
input [1:0] rxbufstatus, // tranceiver connection: Elastic Buffer Status.
input [0:0] rxchariscomma, // tranceiver connection: Comma detected in RXDATA.
input [0:0] rxcharisk, // tranceiver connection: K character received (or extra data bit) in RXDATA.
input [2:0] rxclkcorcnt, // tranceiver connection: Indicates clock correction.
input [7:0] rxdata, // tranceiver connection: Data after 8B/10B decoding.
input [0:0] rxdisperr, // tranceiver connection: Disparity-error in RXDATA.
input [0:0] rxnotintable, // tranceiver connection: Non-existent 8B/10 code indicated.
input [0:0] rxrundisp, // tranceiver connection: Running Disparity of RXDATA (or extra data bit).
input txbuferr, // tranceiver connection: TX Buffer error (overflow or underflow).
output powerdown, // tranceiver connection: Powerdown the tranceiver
output txchardispmode, // tranceiver connection: Set running disparity for current byte.
output txchardispval, // tranceiver connection: Set running disparity value.
output txcharisk, // tranceiver connection: K character transmitted in TXDATA.
output [7:0] txdata, // tranceiver connection: Data for 8B/10B encoding.
output enablealign, // Allow the transceivers to serially realign to a comma character.
// GMII Interface (MAC <=> PCS)
//-----------------------------
input [7:0] gmii_txd, // Transmit data from client MAC.
input gmii_tx_en, // Transmit control signal from client MAC.
input gmii_tx_er, // Transmit control signal from client MAC.
output [7:0] gmii_rxd, // Received Data to client MAC.
output gmii_rx_dv, // Received control signal to client MAC.
output gmii_rx_er, // Received control signal to client MAC.
output gmii_isolate, // Tristate control to electrically isolate GMII.
// MDIO Interface
//---------------
input mdc, // Management Data Clock
input mdio_in, // Management Data In
output mdio_out, // Management Data Out
output mdio_tri, // Management Data Tristate
input [4:0] phyad, // Port address to for MDIO to recognise.
input [4:0] configuration_vector, // Alternative to MDIO interface.
input configuration_valid, // Validation signal for Config vector
// General IO's
//-------------
output [15:0] status_vector, // Core status.
input reset, // Asynchronous reset for entire core.
input signal_detect // Input from PMD to indicate presence of optical input.
);
endmodule // gige_sfp_mdio
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_reset_sync.v
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_reset_sync.v
// Author : Xilinx, Inc.
//------------------------------------------------------------------------------
// Description: Both flip-flops have the same asynchronous reset signal.
// Together the flops create a minimum of a 1 clock period
// duration pulse which is used for synchronous reset.
//
// The flops are placed, using RLOCs, into the same slice.
//------------------------------------------------------------------------------
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
`timescale 1ps/1ps
module gige_sfp_mdio_reset_sync #(
parameter INITIALISE = 2'b11
)
(
input reset_in,
input clk,
output reset_out
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *)
wire reset_stage1;
(* shreg_extract = "no", ASYNC_REG = "TRUE" *)
wire reset_stage2;
FDP #(
.INIT (INITIALISE[0])
) reset_sync1 (
.C (clk),
.PRE(reset_in),
.D (1'b0),
.Q (reset_stage1)
);
FDP #(
.INIT (INITIALISE[1])
) reset_sync2 (
.C (clk),
.PRE(reset_in),
.D (reset_stage1),
.Q (reset_stage2)
);
assign reset_out = reset_stage2;
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_sync_block.v
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_sync_block.vhd
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// Description: Used on signals crossing from one clock domain to
// another, this is a flip-flop pair, with both flops
// placed together with RLOCs into the same slice. Thus
// the routing delay between the two is minimum to safe-
// guard against metastability issues.
//------------------------------------------------------------------------------
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
`timescale 1ps / 1ps
module gige_sfp_mdio_sync_block #(
parameter INITIALISE = 2'b00
)
(
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync1;
wire data_sync2;
(* shreg_extract = "no", ASYNC_REG = "TRUE", RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[0])
) data_sync (
.C (clk),
.D (data_in),
.Q (data_sync1)
);
(* shreg_extract = "no", RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[1])
) data_sync_reg (
.C (clk),
.D (data_sync1),
.Q (data_sync2)
);
assign data_out = data_sync2;
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/gige_sfp_mdio_tx_elastic_buffer.v
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//------------------------------------------------------------------------------
// File : gige_sfp_mdio_tx_elastic_buffer.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This is the Transmitter Elastic Buffer for the design
// example of the Ethernet 1000BASE-X PCS/PMA or SGMII
// core.
//
// The FIFO is created from Distributed Memory and is of
// depth 16 words.
//
// When the write clock is a few parts per million faster
// than the read clock, the occupancy of the FIFO will
// increase and Idles should be removed. A MAC transmitter
// should always insert a minimum of 12 Idles in a single
// Inter-Packet Gap. The IEEE802.3 specification allows
// for up to 4 Idles to be lost within the system (eg. due
// to clock correction) so that a minimum of 8 Idles should
// always be presented to a MAC receiver. Consequently the
// logic in this example design will only remove a single
// Idle per minimum Inter-Packet Gap. This leaves clock
// correction potential for other components in the overall
// system.
//
// When the read clock is a few parts per million faster
// than the write clock, the occupancy of the FIFO will
// decrease and Idles should be inserted. The logic in
// this example design will always insert as many idles as
// necessary in every Inter-frame Gap period to restore the
// FIFO occupancy.
//
// Because the Idle insertion logic is stronger than the
// Idle removal logic, the bias in this example design is
// to keep the occupancy of the FIFO low. This allows more
// overhead for the FIFO to fill up during heavy bursts of
// traffic.
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// Module declaration.
//------------------------------------------------------------------------------
module gige_sfp_mdio_tx_elastic_buffer
(
input reset, // Asynchronous Reset
// Signals received from the input gmii_tx_clk_wr domain.
//------------------------------------------------------
input gmii_tx_clk_wr, // Write clock domain.
input [7:0] gmii_txd_wr, // gmii_txd synchronous to gmii_tx_clk_wr.
input gmii_tx_en_wr, // gmii_tx_en synchronous to gmii_tx_clk_wr.
input gmii_tx_er_wr, // gmii_tx_er synchronous to gmii_tx_clk_wr.
// Signals transfered onto the new gmii_tx_clk_rd domain.
//-------------------------------------------------------
input gmii_tx_clk_rd, // Read clock domain.
output [7:0] gmii_txd_rd, // gmii_txd synchronous to gmii_tx_clk_rd.
output gmii_tx_en_rd, // gmii_tx_en synchronous to gmii_tx_clk_rd.
output gmii_tx_er_rd // gmii_tx_er synchronous to gmii_tx_clk_rd.
);
//----------------------------------------------------------------------------
// Signal declarations
//----------------------------------------------------------------------------
wire [3:0] lower_threshold; // FIFO occupancy should be kept at 6 or above.
wire [3:0] upper_threshold; // FIFO occupancy should be kept at 9 or below.
// create a synchronous reset in the write clock domain
wire reset_wr;
// create a synchronous reset in the read clock domain
wire reset_rd;
reg [7:0] gmii_txd_wr_reg; // Registered version of gmii_txd_wr.
reg gmii_tx_en_wr_reg; // Registered version of gmii_tx_en_wr.
reg gmii_tx_er_wr_reg; // Registered version of gmii_tx_er_wr.
reg wr_enable; // write enable for FIFO.
reg rd_enable; // read enable for FIFO.
wire nearly_full; // FIFO is getting full.
wire nearly_empty; // FIFO is running empty.
reg [3:0] wr_addr_plus2; // Always ahead of the FIFO write address by 2.
reg [3:0] wr_addr_plus1; // Always ahead of the FIFO write address by 1.
reg [3:0] wr_addr; // FIFO write address.
reg [3:0] wr_addrgray; // FIFO write address converted to Gray Code.
wire [3:0] wag_readsync; // wr_addrgray Registered on read clock for the 2nd time.
wire [3:0] wr_addrbin; // wag_readsync converted back to binary - on READ clock.
reg [3:0] rd_addr_plus2; // Always ahead of the FIFO read address by 2.
reg [3:0] rd_addr_plus1; // Always ahead of the FIFO read address by 1.
reg [3:0] rd_addr; // FIFO read address.
reg [3:0] rd_addrgray; // FIFO read address converted to Gray Code.
wire [3:0] rag_writesync; // rd_addrgray Registered on write clock for the 2nd time.
wire [3:0] rd_addrbin; // rag_writesync converted back to binary - on WRITE clock.
wire tx_en_fifo; // gmii_tx_en_wr read out of FIFO.
wire tx_er_fifo; // gmii_tx_er_wr read out of FIFO.
wire [7:0] txd_fifo; // gmii_txd_wr read out of FIFO.
reg tx_en_fifo_reg1; // Registered version of tx_en_fifo.
reg tx_er_fifo_reg1; // Registered version of tx_er_fifo.
reg [7:0] txd_fifo_reg1; // Registered version of txd_fifo.
reg tx_en_fifo_reg2; // Registered version of tx_en_fifo_reg1.
reg tx_er_fifo_reg2; // Registered version of tx_er_fifo_reg1.
reg [7:0] txd_fifo_reg2; // Registered version of txd_fifo_reg1.
reg [3:0] wr_occupancy; // The occupancy of the FIFO in write clock domain.
reg [3:0] rd_occupancy; // The occupancy of the FIFO in read clock domain.
wire wr_idle; // Detect an Idle written into the FIFO in the write clock domain.
wire rd_idle; // Detect an Idle read out of the FIFO in the read clock domain.
reg [3:0] ipg_count; // Count the Inter-Packet Gap period.
reg allow_idle_removal; // Allow the removal of a single Idle.
// Assign the Upper and Lower thresholds for the FIFO. These are used
// to determine the nearly_full and nearly_empty signals.
// FIFO occupancy should be kept at 6 or above.
assign lower_threshold = 4'b0110;
// FIFO occupancy should be kept at 9 or below.
assign upper_threshold = 4'b1001;
//------------------------------------------------------------------------------
// FIFO write logic (Idles are removed as necessary).
//------------------------------------------------------------------------------
// Create a synchronous reset in the write clock domain.
gige_sfp_mdio_reset_sync gen_wr_reset (
.clk (gmii_tx_clk_wr),
.reset_in (reset),
.reset_out (reset_wr)
);
// Reclock the GMII Tx inputs.
always @(posedge gmii_tx_clk_wr)
begin : reclock_gmii
if (reset_wr == 1'b1) begin
gmii_txd_wr_reg <= 8'b0;
gmii_tx_en_wr_reg <= 1'b0;
gmii_tx_er_wr_reg <= 1'b0;
end
else begin
gmii_txd_wr_reg <= gmii_txd_wr;
gmii_tx_en_wr_reg <= gmii_tx_en_wr;
gmii_tx_er_wr_reg <= gmii_tx_er_wr;
end
end // reclock_gmii
// Detect Idles (Normal inter-frame encodings as desribed in
// IEEE802.3 table 35-2)
assign wr_idle = (
// 1st type of Idle.
(gmii_tx_en_wr == 1'b0 && gmii_tx_er_wr == 1'b0)
||
// 2nd type of Idle.
(gmii_tx_en_wr == 1'b0 && gmii_tx_er_wr == 1'b1
&& gmii_txd_wr == 8'b0)
) ? 1'b1 : 1'b0;
// Create a counter to count from 0 to 8. When the counter reaches 8
// it is reset to 0 and a pulse is generated (allow_idle_removal).
// allow_idle_removal is therefore high for a single clock cycle once
// every 9 clock periods. This is used to ensure that the Idle
// removal logic will only ever remove a single idle from a minimum
// transmitter interframe gap (12 idles). This leaves clock
// correction potential for other components in the overall system
// (the IEEE802.3 spec allows for a total of 4 idles to be lost
// between a MAC transmitter and a MAC receiver).
always @(posedge gmii_tx_clk_wr)
begin : idle_removal_control
if (reset_wr == 1'b1) begin
ipg_count <= 4'b0;
allow_idle_removal <= 1'b0;
end
else begin
if (ipg_count[3] == 1'b1) begin
ipg_count <= 4'b0;
allow_idle_removal <= 1'b1;
end
else begin
ipg_count <= ipg_count + 4'b1;
allow_idle_removal <= 1'b0;
end
end
end // idle_removal_control
// Create the FIFO write enable. This is not asserted when Idles are
// to be removed.
always @(posedge gmii_tx_clk_wr)
begin : gen_wr_enable
if (reset_wr == 1'b1)
wr_enable <= 1'b0;
else begin
if (wr_idle == 1'b1 && allow_idle_removal == 1'b1
&& nearly_full == 1'b1) // remove 1 Idle.
wr_enable <= 1'b0;
else
wr_enable <= 1'b1;
end
end // gen_wr_enable
// Create the FIFO write address pointer. Note that wr_addr_plus2
// will be converted to gray code and passed across the async clock
// boundary.
always @(posedge gmii_tx_clk_wr)
begin : gen_wr_addr
if (reset_wr == 1'b1) begin
wr_addr_plus2 <= 4'b0010;
wr_addr_plus1 <= 4'b0001;
wr_addr <= 4'b0000;
end
else if (wr_enable == 1'b1) begin
wr_addr_plus2 <= wr_addr_plus2 + 4'b0001;
wr_addr_plus1 <= wr_addr_plus2;
wr_addr <= wr_addr_plus1;
end
end // gen_wr_addr
//------------------------------------------------------------------------------
// Build FIFO out of distributed RAM.
//------------------------------------------------------------------------------
genvar i;
generate for (i=0; i<8; i=i+1)
begin : gen_txd_fifo_bus
RAM16X1D gen_txd_fifo_bit
(
.D(gmii_txd_wr_reg[i]),
.WE(wr_enable),
.WCLK(gmii_tx_clk_wr),
.A0(wr_addr[0]),
.A1(wr_addr[1]),
.A2(wr_addr[2]),
.A3(wr_addr[3]),
.DPRA0(rd_addr[0]),
.DPRA1(rd_addr[1]),
.DPRA2(rd_addr[2]),
.DPRA3(rd_addr[3]),
.SPO(),
.DPO(txd_fifo[i])
);
end
endgenerate
RAM16X1D gen_tx_en_fifo
(
.D(gmii_tx_en_wr_reg),
.WE(wr_enable),
.WCLK(gmii_tx_clk_wr),
.A0(wr_addr[0]),
.A1(wr_addr[1]),
.A2(wr_addr[2]),
.A3(wr_addr[3]),
.DPRA0(rd_addr[0]),
.DPRA1(rd_addr[1]),
.DPRA2(rd_addr[2]),
.DPRA3(rd_addr[3]),
.SPO(),
.DPO(tx_en_fifo)
);
RAM16X1D gen_tx_er_fifo
(
.D(gmii_tx_er_wr_reg),
.WE(wr_enable),
.WCLK(gmii_tx_clk_wr),
.A0(wr_addr[0]),
.A1(wr_addr[1]),
.A2(wr_addr[2]),
.A3(wr_addr[3]),
.DPRA0(rd_addr[0]),
.DPRA1(rd_addr[1]),
.DPRA2(rd_addr[2]),
.DPRA3(rd_addr[3]),
.SPO(),
.DPO(tx_er_fifo)
);
//------------------------------------------------------------------------------
// FIFO read logic (Idles are repeated as necessary).
//------------------------------------------------------------------------------
// Create a synchronous reset in the read clock domain.
gige_sfp_mdio_reset_sync gen_rd_reset (
.clk (gmii_tx_clk_rd),
.reset_in (reset),
.reset_out (reset_rd)
);
// Register the FIFO outputs.
always @(posedge gmii_tx_clk_rd)
begin : drive_new_gmii
if (reset_rd == 1'b1) begin
txd_fifo_reg1 <= 8'b0;
tx_en_fifo_reg1 <= 1'b0;
tx_er_fifo_reg1 <= 1'b0;
txd_fifo_reg2 <= 8'b0;
tx_en_fifo_reg2 <= 1'b0;
tx_er_fifo_reg2 <= 1'b0;
end
else begin
txd_fifo_reg1 <= txd_fifo;
tx_en_fifo_reg1 <= tx_en_fifo;
tx_er_fifo_reg1 <= tx_er_fifo;
txd_fifo_reg2 <= txd_fifo_reg1;
tx_en_fifo_reg2 <= tx_en_fifo_reg1;
tx_er_fifo_reg2 <= tx_er_fifo_reg1;
end
end // drive_new_gmii
// Route GMII outputs, now synchronous to gmii_tx_clk_rd.
assign gmii_txd_rd = txd_fifo_reg2;
assign gmii_tx_en_rd = tx_en_fifo_reg2;
assign gmii_tx_er_rd = tx_er_fifo_reg2;
// Detect Idles (Normal inter-frame encodings as desribed in
// IEEE802.3 table 35-2)
assign rd_idle = (
// 1st type of Idle.
(tx_en_fifo_reg1 == 1'b0 && tx_er_fifo_reg1 == 1'b0)
||
// 2nd type of Idle.
(tx_en_fifo_reg1 == 1'b0 && tx_er_fifo_reg1 == 1'b1
&& txd_fifo_reg1 == 8'b0)
) ? 1'b1 : 1'b0;
// Create the FIFO read enable. This is not asserted when Idles are
// to be repeated.
always @(posedge gmii_tx_clk_rd)
begin : gen_rd_enable
if (reset_rd == 1'b1)
rd_enable <= 1'b0;
else begin
if (rd_idle == 1'b1 // Detect an Idle
&& nearly_empty == 1'b1) // when FIFO is running empty.
// Repeat the Idle by freezing read pointer of FIFO (as
// many times as necessary).
rd_enable <= 1'b0;
else
rd_enable <= 1'b1;
end
end // gen_rd_enable
// Create the FIFO read address pointer. Note that rd_addr_plus2
// will be converted to gray code and passed across the async clock
// boundary.
always @(posedge gmii_tx_clk_rd)
begin : gen_rd_addr
if (reset_rd == 1'b1) begin
rd_addr_plus2 <= 4'b0010;
rd_addr_plus1 <= 4'b0001;
rd_addr <= 4'b0000;
end
else if (rd_enable == 1'b1) begin
rd_addr_plus2 <= rd_addr_plus2 + 4'b0001;
rd_addr_plus1 <= rd_addr_plus2;
rd_addr <= rd_addr_plus1;
end
end // gen_rd_addr
//------------------------------------------------------------------------------
// Create nearly_full threshold in write clock domain.
//------------------------------------------------------------------------------
// Please refer to Xilinx Application Note 131 for a complete
// description of this logic.
// Convert Binary Read Pointer to Gray Code.
always @(posedge gmii_tx_clk_rd)
begin : rd_addrgray_bits
if (reset_rd == 1'b1)
rd_addrgray <= 4'b0;
else begin
rd_addrgray[3] <= rd_addr_plus2[3];
rd_addrgray[2] <= rd_addr_plus2[3] ^ rd_addr_plus2[2];
rd_addrgray[1] <= rd_addr_plus2[2] ^ rd_addr_plus2[1];
rd_addrgray[0] <= rd_addr_plus2[1] ^ rd_addr_plus2[0];
end
end // rd_addrgray_bits
// Register rd_addrgray on gmii_tx_clk_wr. By reclocking the gray
// code, the worst case senario is that the reclocked value is only
// in error by -1, since only 1 bit at a time changes between gray
// code increment.
genvar j;
generate for (j=0; j<4; j=j+1)
begin : reclock_rd_addrgray
gige_sfp_mdio_sync_block sync_rd_addrgray
(
.clk (gmii_tx_clk_wr),
.data_in (rd_addrgray[j]),
.data_out (rag_writesync[j])
);
end
endgenerate
// Convert rag_writesync Gray Code read address back to binary.
// This has crossed clock domains from gmii_tx_clk_rd to
// gmii_tx_clk_wr.
assign rd_addrbin[3] = rag_writesync[3];
assign rd_addrbin[2] = rag_writesync[3] ^ rag_writesync[2];
assign rd_addrbin[1] = rag_writesync[3] ^ rag_writesync[2]
^ rag_writesync[1];
assign rd_addrbin[0] = rag_writesync[3] ^ rag_writesync[2]
^ rag_writesync[1] ^ rag_writesync[0];
// Determine the occupancy of the FIFO. One clock of latency is
// created here by registering wr_occupancy.
always @(posedge gmii_tx_clk_wr)
begin : gen_wr_occupancy
wr_occupancy <= wr_addr - rd_addrbin;
end // gen_wr_occupancy
// Set nearly_full flag if FIFO occupancy is greater than
// upper_threshold.
assign nearly_full = (wr_occupancy > upper_threshold) ? 1'b1 : 1'b0;
//------------------------------------------------------------------------------
// Create nearly_empty threshold logic in read clock domain.
//------------------------------------------------------------------------------
// Please refer to Xilinx Application Note 131 for a complete
// description of this logic.
// Convert Binary Write Pointer to Gray Code.
always @(posedge gmii_tx_clk_wr)
begin : wr_addrgray_bits
if (reset_wr == 1'b1)
wr_addrgray <= 4'b0;
else begin
wr_addrgray[3] <= wr_addr_plus2[3];
wr_addrgray[2] <= wr_addr_plus2[3] ^ wr_addr_plus2[2];
wr_addrgray[1] <= wr_addr_plus2[2] ^ wr_addr_plus2[1];
wr_addrgray[0] <= wr_addr_plus2[1] ^ wr_addr_plus2[0];
end
end // wr_addrgray_bits
// Register wr_addrgray on gmii_tx_clk_rd. By reclocking the gray
// code, the worst case senario is that the reclocked value is only
// in error by -1, since only 1 bit at a time changes between gray
// code increment.
genvar k;
generate for (k=0; k<4; k=k+1)
begin : reclock_wr_addrgray
gige_sfp_mdio_sync_block sync_wr_addrgray
(
.clk (gmii_tx_clk_rd),
.data_in (wr_addrgray[k]),
.data_out (wag_readsync[k])
);
end
endgenerate
// Convert wag_readsync Gray Code write address back to binary.
// This has crossed clock domains from gmii_tx_clk_wr to
// gmii_tx_clk_rd.
assign wr_addrbin[3] = wag_readsync[3];
assign wr_addrbin[2] = wag_readsync[3] ^ wag_readsync[2];
assign wr_addrbin[1] = wag_readsync[3] ^ wag_readsync[2]
^ wag_readsync[1];
assign wr_addrbin[0] = wag_readsync[3] ^ wag_readsync[2]
^ wag_readsync[1] ^ wag_readsync[0];
// Determine the occupancy of the FIFO. One clock of latency is
// created here by registering rd_occupancy.
always @(posedge gmii_tx_clk_rd)
begin : gen_rd_occupancy
rd_occupancy <= wr_addrbin - rd_addr;
end // gen_rd_occupancy
// Set nearly_empty flag if FIFO occupancy is less than
// lower_threshold.
assign nearly_empty = (rd_occupancy < lower_threshold) ? 1'b1 : 1'b0;
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.v
Executable
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///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : gige_sfp_mdio_gtwizard.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module GTWIZARD (a GT Wrapper)
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`default_nettype wire
`timescale 1ns / 1ps
`define DLY #1
//***************************** Entity Declaration ****************************
(* CORE_GENERATION_INFO = "gige_sfp_mdio_GTWIZARD,gtwizard_v2_4,{protocol_file=gigabit_ethernet_CC}" *) module gige_sfp_mdio_GTWIZARD #
(
// Simulation attributes
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset
parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
parameter PMA_RSV_IN = 32'h00018480,
parameter SIM_VERSION = "4.0"
)
(
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
input [8:0] GT0_DRPADDR_IN,
input GT0_DRPCLK_IN,
input [15:0] GT0_DRPDI_IN,
output [15:0] GT0_DRPDO_OUT,
input GT0_DRPEN_IN,
output GT0_DRPRDY_OUT,
input GT0_DRPWE_IN,
//_________________________________________________________________________
//_________________________________________________________________________
//GT0 (X0Y4)
//____________________________CHANNEL PORTS________________________________
//----------------------- Channel - Ref Clock Ports ------------------------
input GT0_GTREFCLK0_IN,
//------------------------------ Channel PLL -------------------------------
output GT0_CPLLFBCLKLOST_OUT,
output GT0_CPLLLOCK_OUT,
input GT0_CPLLLOCKDETCLK_IN,
output GT0_CPLLREFCLKLOST_OUT,
input GT0_CPLLRESET_IN,
//----------------------------- Eye Scan Ports -----------------------------
output GT0_EYESCANDATAERROR_OUT,
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] GT0_LOOPBACK_IN,
input [1:0] GT0_RXPD_IN,
input [1:0] GT0_TXPD_IN,
//----------------------------- Receive Ports ------------------------------
input GT0_RXUSERRDY_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] GT0_RXCHARISCOMMA_OUT,
output [1:0] GT0_RXCHARISK_OUT,
output [1:0] GT0_RXDISPERR_OUT,
output [1:0] GT0_RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] GT0_RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
input GT0_RXMCOMMAALIGNEN_IN,
input GT0_RXPCOMMAALIGNEN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
input GT0_GTRXRESET_IN,
output [15:0] GT0_RXDATA_OUT,
output GT0_RXOUTCLK_OUT,
input GT0_RXPCSRESET_IN,
input GT0_RXPMARESET_IN,
input GT0_RXUSRCLK_IN,
input GT0_RXUSRCLK2_IN,
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
input GT0_RXDFEAGCHOLD_IN,
input GT0_RXDFELPMRESET_IN,
output [6:0] GT0_RXMONITOROUT_OUT,
input [1:0] GT0_RXMONITORSEL_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input GT0_GTXRXN_IN,
input GT0_GTXRXP_IN,
output GT0_RXCDRLOCK_OUT,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input GT0_RXBUFRESET_IN,
output [2:0] GT0_RXBUFSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
output GT0_RXRESETDONE_OUT,
//----------------------------- Transmit Ports -----------------------------
input GT0_TXUSERRDY_IN,
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [1:0] GT0_TXCHARDISPMODE_IN,
input [1:0] GT0_TXCHARDISPVAL_IN,
input [1:0] GT0_TXCHARISK_IN,
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
output [1:0] GT0_TXBUFSTATUS_OUT,
//---------------- Transmit Ports - TX Data Path interface -----------------
input GT0_GTTXRESET_IN,
input [15:0] GT0_TXDATA_IN,
output GT0_TXOUTCLK_OUT,
output GT0_TXOUTCLKFABRIC_OUT,
output GT0_TXOUTCLKPCS_OUT,
input GT0_TXPCSRESET_IN,
input GT0_TXUSRCLK_IN,
input GT0_TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output GT0_GTXTXN_OUT,
output GT0_GTXTXP_OUT,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
output GT0_TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input GT0_TXELECIDLE_IN,
//____________________________COMMON PORTS________________________________
//-------------------- Common Block - Ref Clock Ports ---------------------
input GT0_GTREFCLK0_COMMON_IN,
//----------------------- Common Block - QPLL Ports ------------------------
output GT0_QPLLLOCK_OUT,
input GT0_QPLLLOCKDETCLK_IN,
output GT0_QPLLREFCLKLOST_OUT,
input GT0_QPLLRESET_IN
);
//***************************** Parameter Declarations ************************
parameter QPLL_FBDIV_TOP = 16;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
wire gt0_qplloutclk_i;
wire gt0_qplloutrefclk_i;
wire gt0_qpllclk_i;
wire gt0_qpllrefclk_i;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
assign gt0_qpllclk_i = gt0_qplloutclk_i;
assign gt0_qpllrefclk_i = gt0_qplloutrefclk_i;
//------------------------- GT Instances -------------------------------
//_________________________________________________________________________
//_________________________________________________________________________
//GT0 (X0Y4)
gige_sfp_mdio_GTWIZARD_GT #
(
// Simulation attributes
.GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION),
.RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN),
.PCS_RSVD_ATTR_IN (48'h000000000000),
.PMA_RSV_IN (PMA_RSV_IN)
)
gt0_GTWIZARD_i
(
//-------------------------------- Channel ---------------------------------
.QPLLCLK_IN (gt0_qpllclk_i),
.QPLLREFCLK_IN (gt0_qpllrefclk_i),
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
.DRPADDR_IN (GT0_DRPADDR_IN),
.DRPCLK_IN (GT0_DRPCLK_IN),
.DRPDI_IN (GT0_DRPDI_IN),
.DRPDO_OUT (GT0_DRPDO_OUT),
.DRPEN_IN (GT0_DRPEN_IN),
.DRPRDY_OUT (GT0_DRPRDY_OUT),
.DRPWE_IN (GT0_DRPWE_IN),
//----------------------- Channel - Ref Clock Ports ------------------------
.GTREFCLK0_IN (GT0_GTREFCLK0_IN),
//------------------------------ Channel PLL -------------------------------
.CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT),
.CPLLLOCK_OUT (GT0_CPLLLOCK_OUT),
.CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN),
.CPLLREFCLKLOST_OUT (GT0_CPLLREFCLKLOST_OUT),
.CPLLRESET_IN (GT0_CPLLRESET_IN),
//----------------------------- Eye Scan Ports -----------------------------
.EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT),
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK_IN (GT0_LOOPBACK_IN),
.RXPD_IN (GT0_RXPD_IN),
.TXPD_IN (GT0_TXPD_IN),
//----------------------------- Receive Ports ------------------------------
.RXUSERRDY_IN (GT0_RXUSERRDY_IN),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT),
.RXCHARISK_OUT (GT0_RXCHARISK_OUT),
.RXDISPERR_OUT (GT0_RXDISPERR_OUT),
.RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN),
.RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN),
//----------------- Receive Ports - RX Data Path interface -----------------
.GTRXRESET_IN (GT0_GTRXRESET_IN),
.RXDATA_OUT (GT0_RXDATA_OUT),
.RXOUTCLK_OUT (GT0_RXOUTCLK_OUT),
.RXPCSRESET_IN (GT0_RXPCSRESET_IN),
.RXPMARESET_IN (GT0_RXPMARESET_IN),
.RXUSRCLK_IN (GT0_RXUSRCLK_IN),
.RXUSRCLK2_IN (GT0_RXUSRCLK2_IN),
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
.RXDFEAGCHOLD_IN (GT0_RXDFEAGCHOLD_IN),
.RXDFELPMRESET_IN (GT0_RXDFELPMRESET_IN),
.RXMONITOROUT_OUT (GT0_RXMONITOROUT_OUT),
.RXMONITORSEL_IN (GT0_RXMONITORSEL_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GTXRXN_IN (GT0_GTXRXN_IN),
.GTXRXP_IN (GT0_GTXRXP_IN),
.RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET_IN (GT0_RXBUFRESET_IN),
.RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.RXRESETDONE_OUT (GT0_RXRESETDONE_OUT),
//----------------------------- Transmit Ports -----------------------------
.TXUSERRDY_IN (GT0_TXUSERRDY_IN),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN),
.TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN),
.TXCHARISK_IN (GT0_TXCHARISK_IN),
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
.TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GTTXRESET_IN (GT0_GTTXRESET_IN),
.TXDATA_IN (GT0_TXDATA_IN),
.TXOUTCLK_OUT (GT0_TXOUTCLK_OUT),
.TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT),
.TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT),
.TXPCSRESET_IN (GT0_TXPCSRESET_IN),
.TXUSRCLK_IN (GT0_TXUSRCLK_IN),
.TXUSRCLK2_IN (GT0_TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GTXTXN_OUT (GT0_GTXTXN_OUT),
.GTXTXP_OUT (GT0_GTXTXP_OUT),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.TXRESETDONE_OUT (GT0_TXRESETDONE_OUT),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXELECIDLE_IN (GT0_TXELECIDLE_IN)
);
//_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION (SIM_VERSION),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt0_qplloutclk_i),
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_ground_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (GT0_QPLLRESET_IN),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.xco
Executable
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@@ -0,0 +1,593 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Sat Nov 10 18:03:36 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:gtwizard:2.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7v585t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1761
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT 7_Series_FPGAs_Transceivers_Wizard xilinx.com:ip:gtwizard:2.4
# END Select
# BEGIN Parameters
CSET advanced_clocking=false
CSET component_name=gige_sfp_mdio_GTWIZARD
CSET gt0_pll0_fbdiv=1
CSET gt0_pll0_fbdiv_45=4
CSET gt0_pll0_refclk_div=1
CSET gt0_pll0_rxout_div=0
CSET gt0_pll0_txout_div=0
CSET gt0_pll1_fbdiv=1
CSET gt0_pll1_fbdiv_45=4
CSET gt0_pll1_refclk_div=1
CSET gt0_pll1_rxout_div=0
CSET gt0_pll1_txout_div=0
CSET gt0_val=true
CSET gt0_val_agc_mode=Auto
CSET gt0_val_align_comma_double=false
CSET gt0_val_align_comma_enable=0001111111
CSET gt0_val_align_comma_word=Two_Byte_Boundaries
CSET gt0_val_align_mcomma_det=true
CSET gt0_val_align_mcomma_value=1010000011
CSET gt0_val_align_pcomma_det=true
CSET gt0_val_align_pcomma_value=0101111100
CSET gt0_val_cb=false
CSET gt0_val_cc=true
CSET gt0_val_cc_seq_periodicity=5000
CSET gt0_val_chan_bond_max_skew=1
CSET gt0_val_chan_bond_seq_1_1=00000000
CSET gt0_val_chan_bond_seq_1_1_disp=false
CSET gt0_val_chan_bond_seq_1_1_k=false
CSET gt0_val_chan_bond_seq_1_1_mask=false
CSET gt0_val_chan_bond_seq_1_2=00000000
CSET gt0_val_chan_bond_seq_1_2_disp=false
CSET gt0_val_chan_bond_seq_1_2_k=false
CSET gt0_val_chan_bond_seq_1_2_mask=false
CSET gt0_val_chan_bond_seq_1_3=00000000
CSET gt0_val_chan_bond_seq_1_3_disp=false
CSET gt0_val_chan_bond_seq_1_3_k=false
CSET gt0_val_chan_bond_seq_1_3_mask=false
CSET gt0_val_chan_bond_seq_1_4=00000000
CSET gt0_val_chan_bond_seq_1_4_disp=false
CSET gt0_val_chan_bond_seq_1_4_k=false
CSET gt0_val_chan_bond_seq_1_4_mask=false
CSET gt0_val_chan_bond_seq_2_1=00000000
CSET gt0_val_chan_bond_seq_2_1_disp=false
CSET gt0_val_chan_bond_seq_2_1_k=false
CSET gt0_val_chan_bond_seq_2_1_mask=false
CSET gt0_val_chan_bond_seq_2_2=00000000
CSET gt0_val_chan_bond_seq_2_2_disp=false
CSET gt0_val_chan_bond_seq_2_2_k=false
CSET gt0_val_chan_bond_seq_2_2_mask=false
CSET gt0_val_chan_bond_seq_2_3=00000000
CSET gt0_val_chan_bond_seq_2_3_disp=false
CSET gt0_val_chan_bond_seq_2_3_k=false
CSET gt0_val_chan_bond_seq_2_3_mask=false
CSET gt0_val_chan_bond_seq_2_4=00000000
CSET gt0_val_chan_bond_seq_2_4_disp=false
CSET gt0_val_chan_bond_seq_2_4_k=false
CSET gt0_val_chan_bond_seq_2_4_mask=false
CSET gt0_val_chan_bond_seq_2_use=false
CSET gt0_val_chan_bond_seq_len=1
CSET gt0_val_clk_cor_seq_1_1=10111100
CSET gt0_val_clk_cor_seq_1_1_disp=false
CSET gt0_val_clk_cor_seq_1_1_k=true
CSET gt0_val_clk_cor_seq_1_1_mask=false
CSET gt0_val_clk_cor_seq_1_2=01010000
CSET gt0_val_clk_cor_seq_1_2_disp=false
CSET gt0_val_clk_cor_seq_1_2_k=false
CSET gt0_val_clk_cor_seq_1_2_mask=false
CSET gt0_val_clk_cor_seq_1_3=00000000
CSET gt0_val_clk_cor_seq_1_3_disp=false
CSET gt0_val_clk_cor_seq_1_3_k=false
CSET gt0_val_clk_cor_seq_1_3_mask=false
CSET gt0_val_clk_cor_seq_1_4=00000000
CSET gt0_val_clk_cor_seq_1_4_disp=false
CSET gt0_val_clk_cor_seq_1_4_k=false
CSET gt0_val_clk_cor_seq_1_4_mask=false
CSET gt0_val_clk_cor_seq_2_1=10111100
CSET gt0_val_clk_cor_seq_2_1_disp=false
CSET gt0_val_clk_cor_seq_2_1_k=true
CSET gt0_val_clk_cor_seq_2_1_mask=false
CSET gt0_val_clk_cor_seq_2_2=10110101
CSET gt0_val_clk_cor_seq_2_2_disp=false
CSET gt0_val_clk_cor_seq_2_2_k=false
CSET gt0_val_clk_cor_seq_2_2_mask=false
CSET gt0_val_clk_cor_seq_2_3=00000000
CSET gt0_val_clk_cor_seq_2_3_disp=false
CSET gt0_val_clk_cor_seq_2_3_k=false
CSET gt0_val_clk_cor_seq_2_3_mask=false
CSET gt0_val_clk_cor_seq_2_4=00000000
CSET gt0_val_clk_cor_seq_2_4_disp=false
CSET gt0_val_clk_cor_seq_2_4_k=false
CSET gt0_val_clk_cor_seq_2_4_mask=false
CSET gt0_val_clk_cor_seq_2_use=true
CSET gt0_val_clk_cor_seq_len=2
CSET gt0_val_comma_preset=K28.5
CSET gt0_val_cpll_fbdiv=4
CSET gt0_val_cpll_fbdiv_45=5
CSET gt0_val_cpll_refclk_div=1
CSET gt0_val_cpll_rxout_div=4
CSET gt0_val_cpll_txout_div=4
CSET gt0_val_dec_mcomma_detect=true
CSET gt0_val_dec_pcomma_detect=true
CSET gt0_val_dec_valid_comma_only=false
CSET gt0_val_decoding=8B/10B
CSET gt0_val_dfe_mode=DFE-Auto
CSET gt0_val_drp=true
CSET gt0_val_drp_clock=100
CSET gt0_val_encoding=8B/10B
CSET gt0_val_max_cb_level=7
CSET gt0_val_no_rx=false
CSET gt0_val_no_tx=false
CSET gt0_val_oob=false
CSET gt0_val_pcs_pcie_en=false
CSET gt0_val_pd_trans_time_from_p2=60
CSET gt0_val_pd_trans_time_non_p2=25
CSET gt0_val_pd_trans_time_to_p2=100
CSET gt0_val_port_cominitdet=false
CSET gt0_val_port_comsasdet=false
CSET gt0_val_port_comwakedet=false
CSET gt0_val_port_cpllpd=false
CSET gt0_val_port_loopback=true
CSET gt0_val_port_phystatus=false
CSET gt0_val_port_pll0pd=false
CSET gt0_val_port_pll1pd=false
CSET gt0_val_port_qpllpd=false
CSET gt0_val_port_rxbufreset=true
CSET gt0_val_port_rxbufstatus=true
CSET gt0_val_port_rxbyteisaligned=false
CSET gt0_val_port_rxbyterealign=false
CSET gt0_val_port_rxcdrhold=false
CSET gt0_val_port_rxchariscomma=true
CSET gt0_val_port_rxcharisk=true
CSET gt0_val_port_rxcommadet=false
CSET gt0_val_port_rxdfeagcovrden=false
CSET gt0_val_port_rxdfereset=true
CSET gt0_val_port_rxelecidle=false
CSET gt0_val_port_rxlpmen=false
CSET gt0_val_port_rxlpmhfovrden=false
CSET gt0_val_port_rxlpmlfklovrden=false
CSET gt0_val_port_rxmcommaalignen=true
CSET gt0_val_port_rxoutclk=true
CSET gt0_val_port_rxpcommaalignen=true
CSET gt0_val_port_rxpcsreset=true
CSET gt0_val_port_rxpmareset=true
CSET gt0_val_port_rxpolarity=false
CSET gt0_val_port_rxpowerdown=true
CSET gt0_val_port_rxqpien=false
CSET gt0_val_port_rxqpisenn=false
CSET gt0_val_port_rxqpisenp=false
CSET gt0_val_port_rxrate=false
CSET gt0_val_port_rxslide=false
CSET gt0_val_port_rxstartofseq=false
CSET gt0_val_port_rxstatus=false
CSET gt0_val_port_rxsysclksel=false
CSET gt0_val_port_rxvalid=false
CSET gt0_val_port_tx8b10bbypass=false
CSET gt0_val_port_txbufstatus=true
CSET gt0_val_port_txchardispmode=true
CSET gt0_val_port_txchardispval=true
CSET gt0_val_port_txcomfinish=false
CSET gt0_val_port_txcominit=false
CSET gt0_val_port_txcomsas=false
CSET gt0_val_port_txcomwake=false
CSET gt0_val_port_txdetectrx=false
CSET gt0_val_port_txelecidle=true
CSET gt0_val_port_txinhibit=false
CSET gt0_val_port_txoutclk=true
CSET gt0_val_port_txpcsreset=true
CSET gt0_val_port_txpmareset=false
CSET gt0_val_port_txpolarity=false
CSET gt0_val_port_txpowerdown=true
CSET gt0_val_port_txprbsforceerr=false
CSET gt0_val_port_txprbssel=false
CSET gt0_val_port_txqpibiasen=false
CSET gt0_val_port_txqpisenn=false
CSET gt0_val_port_txqpisenp=false
CSET gt0_val_port_txqpistrongpdown=false
CSET gt0_val_port_txqpiweakpup=false
CSET gt0_val_port_txrate=false
CSET gt0_val_port_txsysclksel=false
CSET gt0_val_ppm_offset=100
CSET gt0_val_prbs_detector=false
CSET gt0_val_protocol_file=gigabit_ethernet_CC
CSET gt0_val_qpll_fbdiv=16
CSET gt0_val_qpll_refclk_div=1
CSET gt0_val_rx_buffer_bypass_mode=Auto
CSET gt0_val_rx_cm_trim=100
CSET gt0_val_rx_data_width=16
CSET gt0_val_rx_int_datawidth=20
CSET gt0_val_rx_line_rate=1.25
CSET gt0_val_rx_refclk=REFCLK1_Q0
CSET gt0_val_rx_reference_clock=125.000
CSET gt0_val_rx_termination_voltage=GND
CSET gt0_val_rxbuf_en=true
CSET gt0_val_rxcomma_deten=true
CSET gt0_val_rxoutclk_source=false
CSET gt0_val_rxprbs_err_loopback=false
CSET gt0_val_rxslide_mode=OFF
CSET gt0_val_rxusrclk=RXOUTCLK
CSET gt0_val_sata_e_idle_val=4
CSET gt0_val_sata_rx_burst_val=4
CSET gt0_val_tx_buffer_bypass_mode=Auto
CSET gt0_val_tx_data_width=16
CSET gt0_val_tx_int_datawidth=20
CSET gt0_val_tx_line_rate=1.25
CSET gt0_val_tx_refclk=REFCLK1_Q0
CSET gt0_val_tx_reference_clock=125.000
CSET gt0_val_txbuf_en=true
CSET gt0_val_txdiff_emph_mode=Custom
CSET gt0_val_txdiffctrl=false
CSET gt0_val_txmaincursor=false
CSET gt0_val_txoutclk_source=true
CSET gt0_val_txpostcursor=false
CSET gt0_val_txprecursor=false
CSET gt0_val_txusrclk=TXOUTCLK
CSET gt10_val=false
CSET gt10_val_rx_refclk=REFCLK1_Q2
CSET gt10_val_tx_refclk=REFCLK1_Q2
CSET gt11_val=false
CSET gt11_val_rx_refclk=REFCLK1_Q2
CSET gt11_val_tx_refclk=REFCLK1_Q2
CSET gt12_val=false
CSET gt12_val_rx_refclk=REFCLK1_Q3
CSET gt12_val_tx_refclk=REFCLK1_Q3
CSET gt13_val=false
CSET gt13_val_rx_refclk=REFCLK1_Q3
CSET gt13_val_tx_refclk=REFCLK1_Q3
CSET gt14_val=false
CSET gt14_val_rx_refclk=REFCLK1_Q3
CSET gt14_val_tx_refclk=REFCLK1_Q3
CSET gt15_val=false
CSET gt15_val_rx_refclk=REFCLK1_Q3
CSET gt15_val_tx_refclk=REFCLK1_Q3
CSET gt16_val=false
CSET gt16_val_rx_refclk=REFCLK1_Q4
CSET gt16_val_tx_refclk=REFCLK1_Q4
CSET gt17_val=false
CSET gt17_val_rx_refclk=REFCLK1_Q4
CSET gt17_val_tx_refclk=REFCLK1_Q4
CSET gt18_val=false
CSET gt18_val_rx_refclk=REFCLK1_Q4
CSET gt18_val_tx_refclk=REFCLK1_Q4
CSET gt19_val=false
CSET gt19_val_rx_refclk=REFCLK1_Q4
CSET gt19_val_tx_refclk=REFCLK1_Q4
CSET gt1_val=false
CSET gt1_val_rx_refclk=REFCLK1_Q0
CSET gt1_val_tx_refclk=REFCLK1_Q0
CSET gt20_val=false
CSET gt20_val_rx_refclk=REFCLK1_Q5
CSET gt20_val_tx_refclk=REFCLK1_Q5
CSET gt21_val=false
CSET gt21_val_rx_refclk=REFCLK1_Q5
CSET gt21_val_tx_refclk=REFCLK1_Q5
CSET gt22_val=false
CSET gt22_val_rx_refclk=REFCLK1_Q5
CSET gt22_val_tx_refclk=REFCLK1_Q5
CSET gt23_val=false
CSET gt23_val_rx_refclk=REFCLK1_Q5
CSET gt23_val_tx_refclk=REFCLK1_Q5
CSET gt24_val=false
CSET gt24_val_rx_refclk=REFCLK1_Q6
CSET gt24_val_tx_refclk=REFCLK1_Q6
CSET gt25_val=false
CSET gt25_val_rx_refclk=REFCLK1_Q6
CSET gt25_val_tx_refclk=REFCLK1_Q6
CSET gt26_val=false
CSET gt26_val_rx_refclk=REFCLK1_Q6
CSET gt26_val_tx_refclk=REFCLK1_Q6
CSET gt27_val=false
CSET gt27_val_rx_refclk=REFCLK1_Q6
CSET gt27_val_tx_refclk=REFCLK1_Q6
CSET gt28_val=false
CSET gt28_val_rx_refclk=REFCLK1_Q7
CSET gt28_val_tx_refclk=REFCLK1_Q7
CSET gt29_val=false
CSET gt29_val_rx_refclk=REFCLK1_Q7
CSET gt29_val_tx_refclk=REFCLK1_Q7
CSET gt2_val=false
CSET gt2_val_rx_refclk=REFCLK1_Q0
CSET gt2_val_tx_refclk=REFCLK1_Q0
CSET gt30_val=false
CSET gt30_val_rx_refclk=REFCLK1_Q7
CSET gt30_val_tx_refclk=REFCLK1_Q7
CSET gt31_val=false
CSET gt31_val_rx_refclk=REFCLK1_Q7
CSET gt31_val_tx_refclk=REFCLK1_Q7
CSET gt32_val=false
CSET gt32_val_rx_refclk=REFCLK1_Q8
CSET gt32_val_tx_refclk=REFCLK1_Q8
CSET gt33_val=false
CSET gt33_val_rx_refclk=REFCLK1_Q8
CSET gt33_val_tx_refclk=REFCLK1_Q8
CSET gt34_val=false
CSET gt34_val_rx_refclk=REFCLK1_Q8
CSET gt34_val_tx_refclk=REFCLK1_Q8
CSET gt35_val=false
CSET gt35_val_rx_refclk=REFCLK1_Q8
CSET gt35_val_tx_refclk=REFCLK1_Q8
CSET gt36_val=false
CSET gt36_val_rx_refclk=REFCLK1_Q9
CSET gt36_val_tx_refclk=REFCLK1_Q9
CSET gt37_val=false
CSET gt37_val_rx_refclk=REFCLK1_Q9
CSET gt37_val_tx_refclk=REFCLK1_Q9
CSET gt38_val=false
CSET gt38_val_rx_refclk=REFCLK1_Q9
CSET gt38_val_tx_refclk=REFCLK1_Q9
CSET gt39_val=false
CSET gt39_val_rx_refclk=REFCLK1_Q9
CSET gt39_val_tx_refclk=REFCLK1_Q9
CSET gt3_val=false
CSET gt3_val_rx_refclk=REFCLK1_Q0
CSET gt3_val_tx_refclk=REFCLK1_Q0
CSET gt40_val=false
CSET gt40_val_rx_refclk=REFCLK1_Q10
CSET gt40_val_tx_refclk=REFCLK1_Q10
CSET gt41_val=false
CSET gt41_val_rx_refclk=REFCLK1_Q10
CSET gt41_val_tx_refclk=REFCLK1_Q10
CSET gt42_val=false
CSET gt42_val_rx_refclk=REFCLK1_Q10
CSET gt42_val_tx_refclk=REFCLK1_Q10
CSET gt43_val=false
CSET gt43_val_rx_refclk=REFCLK1_Q10
CSET gt43_val_tx_refclk=REFCLK1_Q10
CSET gt44_val=false
CSET gt44_val_rx_refclk=REFCLK1_Q11
CSET gt44_val_tx_refclk=REFCLK1_Q11
CSET gt45_val=false
CSET gt45_val_rx_refclk=REFCLK1_Q11
CSET gt45_val_tx_refclk=REFCLK1_Q11
CSET gt46_val=false
CSET gt46_val_rx_refclk=REFCLK1_Q11
CSET gt46_val_tx_refclk=REFCLK1_Q11
CSET gt47_val=false
CSET gt47_val_rx_refclk=REFCLK1_Q11
CSET gt47_val_tx_refclk=REFCLK1_Q11
CSET gt4_val=false
CSET gt4_val_rx_refclk=REFCLK1_Q1
CSET gt4_val_tx_refclk=REFCLK1_Q1
CSET gt5_val=false
CSET gt5_val_rx_refclk=REFCLK1_Q1
CSET gt5_val_tx_refclk=REFCLK1_Q1
CSET gt6_val=false
CSET gt6_val_rx_refclk=REFCLK1_Q1
CSET gt6_val_tx_refclk=REFCLK1_Q1
CSET gt7_val=false
CSET gt7_val_rx_refclk=REFCLK1_Q1
CSET gt7_val_tx_refclk=REFCLK1_Q1
CSET gt8_val=false
CSET gt8_val_rx_refclk=REFCLK1_Q2
CSET gt8_val_tx_refclk=REFCLK1_Q2
CSET gt9_val=false
CSET gt9_val_rx_refclk=REFCLK1_Q2
CSET gt9_val_tx_refclk=REFCLK1_Q2
CSET gt_column=right_column
CSET gt_row=top_row
CSET gt_type=GTX
CSET gt_val_drp=false
CSET gt_val_drp_clock=60
CSET gt_val_rx_pll=CPLL
CSET gt_val_tx_pll=CPLL
CSET gtz0_val_data_width=160
CSET gtz0_val_encoding=100GBASER_MODE
CSET gtz0_val_no_rx=false
CSET gtz0_val_no_tx=false
CSET gtz0_val_port_corecntl=false
CSET gtz0_val_port_loopback=false
CSET gtz0_val_port_pllrecalen=false
CSET gtz0_val_port_refsel=false
CSET gtz0_val_port_rxbitslip=false
CSET gtz0_val_port_rxen=false
CSET gtz0_val_port_rxfibreset=false
CSET gtz0_val_port_rxfifostatus=false
CSET gtz0_val_port_rxpolarity=false
CSET gtz0_val_port_rxprbs=false
CSET gtz0_val_port_rxratesel=false
CSET gtz0_val_port_rxsignalok=false
CSET gtz0_val_port_txattnctrl=false
CSET gtz0_val_port_txen=false
CSET gtz0_val_port_txeqpostctrl=false
CSET gtz0_val_port_txeqprectrl=false
CSET gtz0_val_port_txfibreset=false
CSET gtz0_val_port_txfifostatus=false
CSET gtz0_val_port_txoutputen=false
CSET gtz0_val_port_txpolarity=false
CSET gtz0_val_port_txprbs=false
CSET gtz0_val_port_txratesel=false
CSET gtz0_val_port_txslewctrl=false
CSET gtz0_val_protocol_file=Start_from_scratch
CSET gtz0_val_refclk_source=REFCLK0
CSET gtz0_val_reference_clock=322.266
CSET gtz0_val_rx_line_rate=25.78125
CSET gtz0_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz0_val_rxusrclk_source=RXUSRCLK0
CSET gtz0_val_tx_line_rate=25.78125
CSET gtz0_val_txoutclk_source=TX_FIFO_CLK
CSET gtz0_val_txusrclk_source=TXUSRCLK0
CSET gtz1_val_data_width=160
CSET gtz1_val_encoding=100GBASER_MODE
CSET gtz1_val_no_rx=false
CSET gtz1_val_no_tx=false
CSET gtz1_val_protocol_file=Start_from_scratch
CSET gtz1_val_refclk_source=REFCLK0
CSET gtz1_val_reference_clock=322.266
CSET gtz1_val_rx_line_rate=25.78125
CSET gtz1_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz1_val_rxusrclk_source=RXUSRCLK0
CSET gtz1_val_tx_line_rate=25.78125
CSET gtz1_val_txoutclk_source=TX_FIFO_CLK
CSET gtz1_val_txusrclk_source=TXUSRCLK0
CSET gtz2_val_data_width=160
CSET gtz2_val_encoding=100GBASER_MODE
CSET gtz2_val_no_rx=false
CSET gtz2_val_no_tx=false
CSET gtz2_val_protocol_file=Start_from_scratch
CSET gtz2_val_refclk_source=REFCLK0
CSET gtz2_val_reference_clock=322.266
CSET gtz2_val_rx_line_rate=25.78125
CSET gtz2_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz2_val_rxusrclk_source=RXUSRCLK0
CSET gtz2_val_tx_line_rate=25.78125
CSET gtz2_val_txoutclk_source=TX_FIFO_CLK
CSET gtz2_val_txusrclk_source=TXUSRCLK0
CSET gtz3_val_data_width=160
CSET gtz3_val_encoding=100GBASER_MODE
CSET gtz3_val_no_rx=false
CSET gtz3_val_no_tx=false
CSET gtz3_val_protocol_file=Start_from_scratch
CSET gtz3_val_refclk_source=REFCLK0
CSET gtz3_val_reference_clock=322.266
CSET gtz3_val_rx_line_rate=25.78125
CSET gtz3_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz3_val_rxusrclk_source=RXUSRCLK0
CSET gtz3_val_tx_line_rate=25.78125
CSET gtz3_val_txoutclk_source=TX_FIFO_CLK
CSET gtz3_val_txusrclk_source=TXUSRCLK0
CSET gtz4_val_data_width=160
CSET gtz4_val_encoding=100GBASER_MODE
CSET gtz4_val_no_rx=false
CSET gtz4_val_no_tx=false
CSET gtz4_val_protocol_file=Start_from_scratch
CSET gtz4_val_refclk_source=REFCLK0
CSET gtz4_val_reference_clock=322.266
CSET gtz4_val_rx_line_rate=25.78125
CSET gtz4_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz4_val_rxusrclk_source=RXUSRCLK0
CSET gtz4_val_tx_line_rate=25.78125
CSET gtz4_val_txoutclk_source=TX_FIFO_CLK
CSET gtz4_val_txusrclk_source=TXUSRCLK0
CSET gtz5_val_data_width=160
CSET gtz5_val_encoding=100GBASER_MODE
CSET gtz5_val_no_rx=false
CSET gtz5_val_no_tx=false
CSET gtz5_val_protocol_file=Start_from_scratch
CSET gtz5_val_refclk_source=REFCLK0
CSET gtz5_val_reference_clock=322.266
CSET gtz5_val_rx_line_rate=25.78125
CSET gtz5_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz5_val_rxusrclk_source=RXUSRCLK0
CSET gtz5_val_tx_line_rate=25.78125
CSET gtz5_val_txoutclk_source=TX_FIFO_CLK
CSET gtz5_val_txusrclk_source=TXUSRCLK0
CSET gtz6_val_data_width=160
CSET gtz6_val_encoding=100GBASER_MODE
CSET gtz6_val_no_rx=false
CSET gtz6_val_no_tx=false
CSET gtz6_val_protocol_file=Start_from_scratch
CSET gtz6_val_refclk_source=REFCLK0
CSET gtz6_val_reference_clock=322.266
CSET gtz6_val_rx_line_rate=25.78125
CSET gtz6_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz6_val_rxusrclk_source=RXUSRCLK0
CSET gtz6_val_tx_line_rate=25.78125
CSET gtz6_val_txoutclk_source=TX_FIFO_CLK
CSET gtz6_val_txusrclk_source=TXUSRCLK0
CSET gtz7_val_data_width=160
CSET gtz7_val_encoding=100GBASER_MODE
CSET gtz7_val_no_rx=false
CSET gtz7_val_no_tx=false
CSET gtz7_val_protocol_file=Start_from_scratch
CSET gtz7_val_refclk_source=REFCLK0
CSET gtz7_val_reference_clock=322.266
CSET gtz7_val_rx_line_rate=25.78125
CSET gtz7_val_rxoutclk_source=RX_FIFO_CLK
CSET gtz7_val_rxusrclk_source=RXUSRCLK0
CSET gtz7_val_tx_line_rate=25.78125
CSET gtz7_val_txoutclk_source=TX_FIFO_CLK
CSET gtz7_val_txusrclk_source=TXUSRCLK0
CSET gtz_selection=GTZ0
CSET identical_config=true
CSET identical_protocol_file=gigabit_ethernet_CC
CSET identical_val_no_rx=false
CSET identical_val_no_tx=false
CSET identical_val_rx_line_rate=1.25
CSET identical_val_rx_reference_clock=125.000
CSET identical_val_tx_line_rate=1.25
CSET identical_val_tx_reference_clock=125.000
CSET octal0_val=true
CSET octal0_val_drpclk_source=DRPCLK0
CSET octal0_val_identical_config=true
CSET octal0_val_identical_no_rx=false
CSET octal0_val_identical_no_tx=false
CSET octal0_val_identical_protocol_file=Start_from_scratch
CSET octal0_val_identical_reference_clock=322.266
CSET octal0_val_identical_rx_line_rate=25.78125
CSET octal0_val_identical_tx_line_rate=25.78125
CSET octal0_val_master_slave=false
CSET octal0_val_multi_channel_mode=OFF
CSET octal0_val_rxoutclk0_source=RXOUTCLK_LANE0
CSET octal0_val_rxoutclk1_source=RXOUTCLK_LANE0
CSET octal0_val_rxoutclk2_source=RXOUTCLK_LANE0
CSET octal0_val_rxoutclk3_source=RXOUTCLK_LANE0
CSET octal0_val_rxusrclk0_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk1_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk2_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk3_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk4_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk5_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk6_source=OCTAL0_RXOUTCLK0
CSET octal0_val_rxusrclk7_source=OCTAL0_RXOUTCLK0
CSET octal0_val_txoutclk0_source=TXOUTCLK_LANE0
CSET octal0_val_txoutclk1_source=TXOUTCLK_LANE0
CSET octal0_val_txusrclk0_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk1_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk2_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk3_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk4_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk5_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk6_source=OCTAL0_TXOUTCLK0
CSET octal0_val_txusrclk7_source=OCTAL0_TXOUTCLK0
CSET octal1_val=false
CSET pcie_cb_en=false
CSET pcie_cb_mode=One_Hop
CSET pcie_lpm_dfe=DFE
CSET pcie_sync_mode=false
CSET silicon_version=no_silicon_version_loaded
CSET use_gtz0=true
CSET use_gtz1=true
CSET use_gtz2=true
CSET use_gtz3=true
CSET use_gtz4=true
CSET use_gtz5=true
CSET use_gtz6=true
CSET use_gtz7=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-10-26T12:38:11Z
# END Extra information
GENERATE
# CRC: c923bc4d
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v
Executable
+763
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@@ -0,0 +1,763 @@
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : GT Wizard
// / / Filename : gige_sfp_mdio_gtwizard_gt.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module GTWIZARD_GT (a GT Wrapper)
// Generated by Xilinx GT Wizard
//
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`default_nettype wire
`timescale 1ns / 1ps
//***************************** Entity Declaration ****************************
module gige_sfp_mdio_GTWIZARD_GT #
(
// Simulation attributes
parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset;
parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
parameter PMA_RSV_IN = 32'h00018480,
parameter PCS_RSVD_ATTR_IN = 48'h000000000000,
parameter SIM_VERSION = "4.0"
)
(
//-------------------------------- Channel ---------------------------------
input QPLLCLK_IN,
input QPLLREFCLK_IN,
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
input [8:0] DRPADDR_IN,
input DRPCLK_IN,
input [15:0] DRPDI_IN,
output [15:0] DRPDO_OUT,
input DRPEN_IN,
output DRPRDY_OUT,
input DRPWE_IN,
//----------------------- Channel - Ref Clock Ports ------------------------
input GTREFCLK0_IN,
//------------------------------ Channel PLL -------------------------------
output CPLLFBCLKLOST_OUT,
output CPLLLOCK_OUT,
input CPLLLOCKDETCLK_IN,
output CPLLREFCLKLOST_OUT,
input CPLLRESET_IN,
//----------------------------- Eye Scan Ports -----------------------------
output EYESCANDATAERROR_OUT,
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] LOOPBACK_IN,
input [1:0] RXPD_IN,
input [1:0] TXPD_IN,
//----------------------------- Receive Ports ------------------------------
input RXUSERRDY_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] RXCHARISCOMMA_OUT,
output [1:0] RXCHARISK_OUT,
output [1:0] RXDISPERR_OUT,
output [1:0] RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
input RXMCOMMAALIGNEN_IN,
input RXPCOMMAALIGNEN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
input GTRXRESET_IN,
output [15:0] RXDATA_OUT,
output RXOUTCLK_OUT,
input RXPCSRESET_IN,
input RXPMARESET_IN,
input RXUSRCLK_IN,
input RXUSRCLK2_IN,
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
input RXDFEAGCHOLD_IN,
input RXDFELPMRESET_IN,
output [6:0] RXMONITOROUT_OUT,
input [1:0] RXMONITORSEL_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input GTXRXN_IN,
input GTXRXP_IN,
output RXCDRLOCK_OUT,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input RXBUFRESET_IN,
output [2:0] RXBUFSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
output RXRESETDONE_OUT,
//----------------------------- Transmit Ports -----------------------------
input TXUSERRDY_IN,
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [1:0] TXCHARDISPMODE_IN,
input [1:0] TXCHARDISPVAL_IN,
input [1:0] TXCHARISK_IN,
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
output [1:0] TXBUFSTATUS_OUT,
//---------------- Transmit Ports - TX Data Path interface -----------------
input GTTXRESET_IN,
input [15:0] TXDATA_IN,
output TXOUTCLK_OUT,
output TXOUTCLKFABRIC_OUT,
output TXOUTCLKPCS_OUT,
input TXPCSRESET_IN,
input TXUSRCLK_IN,
input TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output GTXTXN_OUT,
output GTXTXP_OUT,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
output TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input TXELECIDLE_IN
);
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//RX Datapath signals
wire [63:0] rxdata_i;
wire [5:0] rxchariscomma_float_i;
wire [5:0] rxcharisk_float_i;
wire [5:0] rxdisperr_float_i;
wire [5:0] rxnotintable_float_i;
wire [5:0] rxrundisp_float_i;
//TX Datapath signals
wire [63:0] txdata_i;
wire [5:0] txkerr_float_i;
wire [5:0] txrundisp_float_i;
//
//********************************* Main Body of Code**************************
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
//------------------- GT Datapath byte mapping -----------------
assign RXDATA_OUT = rxdata_i[15:0];
assign txdata_i = {tied_to_ground_vec_i[47:0],TXDATA_IN};
//------------------------- GT Instantiations --------------------------
GTXE2_CHANNEL #
(
//_______________________ Simulation-Only Attributes __________________
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP (GT_SIM_GTRESET_SPEEDUP),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_VERSION (SIM_VERSION),
//----------------RX Byte and Word Alignment Attributes---------------
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b0001111111),
.ALIGN_COMMA_WORD (2),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.SHOW_REALIGN_COMMA ("TRUE"),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
//----------------RX 8B/10B Decoder Attributes---------------
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
//----------------------RX Clock Correction Attributes----------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CLK_COR_SEQ_2_USE ("TRUE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (36),
.CLK_COR_MIN_LAT (33),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_LEN (2),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_1_1 (10'b0110111100),
.CLK_COR_SEQ_1_2 (10'b0001010000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_CORRECT_USE ("TRUE"),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0110111100),
.CLK_COR_SEQ_2_2 (10'b0010110101),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
//----------------------RX Channel Bonding Attributes----------------------
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_LEN (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
//-------------------------RX Margin Analysis Attributes----------------------------
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("FALSE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
.ES_QUAL_MASK (80'h00000000000000000000),
.ES_SDATA_MASK (80'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
//-----------------------FPGA RX Interface Attributes-------------------------
.RX_DATA_WIDTH (20),
//-------------------------PMA Attributes----------------------------
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (PMA_RSV_IN),
.PMA_RSV2 (16'h2050),
.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RX_BIAS_CFG (12'b000000000100),
.DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DEBUG_CFG (12'b000000000000),
.RX_OS_CFG (13'b0000010000000),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
.TST_RSV (32'h00000000),
.RX_CLK25_DIV (5),
.TX_CLK25_DIV (5),
.UCODEER_CLR (1'b0),
//-------------------------PCI Express Attributes----------------------------
.PCS_PCIE_EN ("FALSE"),
//-------------------------PCS Attributes----------------------------
.PCS_RSVD_ATTR (PCS_RSVD_ATTR_IN),
//-----------RX Buffer Attributes------------
.RXBUF_ADDR_MODE ("FULL"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RX_BUFFER_CFG (6'b000000),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_THRESH_OVFLW (61),
.RXBUF_THRESH_OVRD ("FALSE"),
.RXBUF_THRESH_UNDFLW (8),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
//---------------------CDR Attributes-------------------------
//For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
//For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h03000023ff10200020
.RXCDR_CFG (72'h03000023ff40080020),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
//-----------------RX Initialization and Reset Attributes-------------------
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXISCANRESET_TIME (5'b00001),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (5'b00011),
//-----------------RX OOB Signaling Attributes-------------------
.RXOOB_CFG (7'b0000110),
//-----------------------RX Gearbox Attributes---------------------------
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
//-----------------------PRBS Detection Attribute-----------------------
.RXPRBS_ERR_LOOPBACK (1'b0),
//-----------Power-Down Attributes----------
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h19),
.PD_TRANS_TIME_TO_P2 (8'h64),
//-----------RX OOB Signaling Attributes----------
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
//-----------RX Fabric Clock Output Control Attributes----------
.TRANS_TIME_RATE (8'h0E),
//------------TX Buffer Attributes----------------
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
.TXPH_CFG (16'h0780),
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
//-----------------------FPGA TX Interface Attributes-------------------------
.TX_DATA_WIDTH (20),
//-----------------------TX Configurable Driver Attributes-------------------------
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_DRIVE_MODE ("DIRECT"),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
//-----------------------TX Gearbox Attributes--------------------------
.TXGEARBOX_EN ("FALSE"),
//-----------------------TX Initialization and Reset Attributes--------------------------
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (5'b00001),
//-----------------------TX Receiver Detection Attributes--------------------------
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
//--------------------------CPLL Attributes----------------------------
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (4),
.CPLL_FBDIV_45 (5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.RXOUT_DIV (4),
.TXOUT_DIV (4),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
//------------RX Initialization and Reset Attributes-------------
.RXDFELPMRESET_TIME (7'b0001111),
//------------RX Equalizer Attributes-------------
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
//-----------------------Power-Down Attributes-------------------------
.RX_CLKMUX_PD (1'b1),
.TX_CLKMUX_PD (1'b1),
//-----------------------FPGA RX Interface Attribute-------------------------
.RX_INT_DATAWIDTH (0),
//-----------------------FPGA TX Interface Attribute-------------------------
.TX_INT_DATAWIDTH (0),
//----------------TX Configurable Driver Attributes---------------
.TX_QPI_STATUS_EN (1'b0),
//-----------------------RX Equalizer Attributes--------------------------
.RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2_IN),
.RX_DFE_XYD_CFG (13'b0000000000000),
//-----------------------TX Configurable Driver Attributes--------------------------
.TX_PREDRIVER_MODE (1'b0)
)
gtxe2_i
(
//-------------------------------- Channel ---------------------------------
.CFGRESET (tied_to_ground_i),
.CLKRSVD (4'b0000),
.DMONITOROUT (),
.GTRESETSEL (tied_to_ground_i),
.GTRSVD (16'b0000000000000000),
.QPLLCLK (QPLLCLK_IN),
.QPLLREFCLK (QPLLREFCLK_IN),
.RESETOVRD (tied_to_ground_i),
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
.DRPADDR (DRPADDR_IN),
.DRPCLK (DRPCLK_IN),
.DRPDI (DRPDI_IN),
.DRPDO (DRPDO_OUT),
.DRPEN (DRPEN_IN),
.DRPRDY (DRPRDY_OUT),
.DRPWE (DRPWE_IN),
//----------------------- Channel - Ref Clock Ports ------------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GTREFCLK0_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTREFCLKMONITOR (),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//------------------------------ Channel PLL -------------------------------
.CPLLFBCLKLOST (CPLLFBCLKLOST_OUT),
.CPLLLOCK (CPLLLOCK_OUT),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_IN),
.CPLLLOCKEN (tied_to_vcc_i),
.CPLLPD (tied_to_ground_i),
.CPLLREFCLKLOST (CPLLREFCLKLOST_OUT),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (CPLLRESET_IN),
//----------------------------- Eye Scan Ports -----------------------------
.EYESCANDATAERROR (EYESCANDATAERROR_OUT),
.EYESCANMODE (tied_to_ground_i),
.EYESCANRESET (tied_to_ground_i),
.EYESCANTRIGGER (tied_to_ground_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK (LOOPBACK_IN),
.RXPD (RXPD_IN),
.TXPD (TXPD_IN),
//--------------------------- PCS Reserved Ports ---------------------------
.PCSRSVDIN (16'b0000000000000000),
.PCSRSVDIN2 (5'b00000),
.PCSRSVDOUT (),
//--------------------------- PMA Reserved Ports ---------------------------
.PMARSVDIN (5'b00000),
.PMARSVDIN2 (5'b00000),
//----------------------------- Receive Ports ------------------------------
.RXQPIEN (tied_to_ground_i),
.RXQPISENN (),
.RXQPISENP (),
.RXSYSCLKSEL (2'b00),
.RXUSERRDY (RXUSERRDY_IN),
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
.RXDATAVALID (),
.RXGEARBOXSLIP (tied_to_ground_i),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RX8B10BEN (tied_to_vcc_i),
.RXCHARISCOMMA ({rxchariscomma_float_i,RXCHARISCOMMA_OUT}),
.RXCHARISK ({rxcharisk_float_i,RXCHARISK_OUT}),
.RXDISPERR ({rxdisperr_float_i,RXDISPERR_OUT}),
.RXNOTINTABLE ({rxnotintable_float_i,RXNOTINTABLE_OUT}),
//----------------- Receive Ports - Channel Bonding Ports ------------------
.RXCHANBONDSEQ (),
.RXCHBONDEN (tied_to_ground_i),
.RXCHBONDI (5'b00000),
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
.RXCHBONDMASTER (tied_to_ground_i),
.RXCHBONDO (),
.RXCHBONDSLAVE (tied_to_ground_i),
//----------------- Receive Ports - Channel Bonding Ports -----------------
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT (RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCOMMADET (),
.RXCOMMADETEN (tied_to_vcc_i),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_IN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_IN),
.RXSLIDE (tied_to_ground_i),
//--------------------- Receive Ports - PRBS Detection ---------------------
.RXPRBSCNTRESET (tied_to_ground_i),
.RXPRBSERR (),
.RXPRBSSEL (tied_to_ground_vec_i[2:0]),
//----------------- Receive Ports - RX Data Path interface -----------------
.GTRXRESET (GTRXRESET_IN),
.RXDATA (rxdata_i),
.RXOUTCLK (RXOUTCLK_OUT),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (3'b010),
.RXPCSRESET (RXPCSRESET_IN),
.RXPMARESET (RXPMARESET_IN),
.RXUSRCLK (RXUSRCLK_IN),
.RXUSRCLK2 (RXUSRCLK2_IN),
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
.RXDFEAGCHOLD (RXDFEAGCHOLD_IN),
.RXDFEAGCOVRDEN (tied_to_ground_i),
.RXDFECM1EN (tied_to_ground_i),
.RXDFELFHOLD (tied_to_ground_i),
.RXDFELFOVRDEN (tied_to_vcc_i),
.RXDFELPMRESET (RXDFELPMRESET_IN),
.RXDFETAP2HOLD (tied_to_ground_i),
.RXDFETAP2OVRDEN (tied_to_ground_i),
.RXDFETAP3HOLD (tied_to_ground_i),
.RXDFETAP3OVRDEN (tied_to_ground_i),
.RXDFETAP4HOLD (tied_to_ground_i),
.RXDFETAP4OVRDEN (tied_to_ground_i),
.RXDFETAP5HOLD (tied_to_ground_i),
.RXDFETAP5OVRDEN (tied_to_ground_i),
.RXDFEUTHOLD (tied_to_ground_i),
.RXDFEUTOVRDEN (tied_to_ground_i),
.RXDFEVPHOLD (tied_to_ground_i),
.RXDFEVPOVRDEN (tied_to_ground_i),
.RXDFEVSEN (tied_to_ground_i),
.RXDFEXYDEN (tied_to_ground_i),
.RXDFEXYDHOLD (tied_to_ground_i),
.RXDFEXYDOVRDEN (tied_to_ground_i),
.RXMONITOROUT (RXMONITOROUT_OUT),
.RXMONITORSEL (RXMONITORSEL_IN),
.RXOSHOLD (tied_to_ground_i),
.RXOSOVRDEN (tied_to_ground_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GTXRXN (GTXRXN_IN),
.GTXRXP (GTXRXP_IN),
.RXCDRFREQRESET (tied_to_ground_i),
.RXCDRHOLD (tied_to_ground_i),
.RXCDRLOCK (RXCDRLOCK_OUT),
.RXCDROVRDEN (tied_to_ground_i),
.RXCDRRESET (tied_to_ground_i),
.RXCDRRESETRSV (tied_to_ground_i),
.RXELECIDLE (),
.RXELECIDLEMODE (2'b11),
.RXLPMHFHOLD (tied_to_ground_i),
.RXLPMHFOVRDEN (tied_to_ground_i),
.RXLPMLFHOLD (tied_to_ground_i),
.RXLPMLFKLOVRDEN (tied_to_ground_i),
.RXOOBRESET (tied_to_ground_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET (RXBUFRESET_IN),
.RXBUFSTATUS (RXBUFSTATUS_OUT),
.RXDDIEN (tied_to_ground_i),
.RXDLYBYPASS (tied_to_vcc_i),
.RXDLYEN (tied_to_ground_i),
.RXDLYOVRDEN (tied_to_ground_i),
.RXDLYSRESET (tied_to_ground_i),
.RXDLYSRESETDONE (),
.RXPHALIGN (tied_to_ground_i),
.RXPHALIGNDONE (),
.RXPHALIGNEN (tied_to_ground_i),
.RXPHDLYPD (tied_to_ground_i),
.RXPHDLYRESET (tied_to_ground_i),
.RXPHMONITOR (),
.RXPHOVRDEN (tied_to_ground_i),
.RXPHSLIPMONITOR (),
.RXSTATUS (),
//---------------------- Receive Ports - RX Equalizer ----------------------
.RXLPMEN (tied_to_ground_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.RXRATE (tied_to_ground_vec_i[2:0]),
.RXRATEDONE (),
.RXRESETDONE (RXRESETDONE_OUT),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.PHYSTATUS (),
.RXVALID (),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.RXPOLARITY (tied_to_ground_i),
//------------------- Receive Ports - RX Ports for SATA --------------------
.RXCOMINITDET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
//----------------------------- Transmit Ports -----------------------------
.SETERRSTATUS (tied_to_ground_i),
.TSTIN (20'b11111111111111111111),
.TSTOUT (),
.TXPHDLYTSTCLK (tied_to_ground_i),
.TXPOSTCURSOR (5'b00000),
.TXPOSTCURSORINV (tied_to_ground_i),
.TXPRECURSOR (tied_to_ground_vec_i[4:0]),
.TXPRECURSORINV (tied_to_ground_i),
.TXQPIBIASEN (tied_to_ground_i),
.TXQPISENN (),
.TXQPISENP (),
.TXQPISTRONGPDOWN (tied_to_ground_i),
.TXQPIWEAKPUP (tied_to_ground_i),
.TXSYSCLKSEL (2'b00),
.TXUSERRDY (TXUSERRDY_IN),
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
.TXGEARBOXREADY (),
.TXHEADER (tied_to_ground_vec_i[2:0]),
.TXSEQUENCE (tied_to_ground_vec_i[6:0]),
.TXSTARTSEQ (tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TX8B10BBYPASS (tied_to_ground_vec_i[7:0]),
.TX8B10BEN (tied_to_vcc_i),
.TXCHARDISPMODE ({tied_to_ground_vec_i[5:0],TXCHARDISPMODE_IN}),
.TXCHARDISPVAL ({tied_to_ground_vec_i[5:0],TXCHARDISPVAL_IN}),
.TXCHARISK ({tied_to_ground_vec_i[5:0],TXCHARISK_IN}),
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
.TXBUFSTATUS (TXBUFSTATUS_OUT),
.TXDLYBYPASS (tied_to_vcc_i),
.TXDLYEN (tied_to_ground_i),
.TXDLYHOLD (tied_to_ground_i),
.TXDLYOVRDEN (tied_to_ground_i),
.TXDLYSRESET (tied_to_ground_i),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (tied_to_ground_i),
.TXPHALIGN (tied_to_ground_i),
.TXPHALIGNDONE (),
.TXPHALIGNEN (tied_to_ground_i),
.TXPHDLYPD (tied_to_ground_i),
.TXPHDLYRESET (tied_to_ground_i),
.TXPHINIT (tied_to_ground_i),
.TXPHINITDONE (),
.TXPHOVRDEN (tied_to_ground_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GTTXRESET (GTTXRESET_IN),
.TXDATA (txdata_i),
.TXOUTCLK (TXOUTCLK_OUT),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_OUT),
.TXOUTCLKPCS (TXOUTCLKPCS_OUT),
.TXOUTCLKSEL (3'b100),
.TXPCSRESET (TXPCSRESET_IN),
.TXPMARESET (tied_to_ground_i),
.TXUSRCLK (TXUSRCLK_IN),
.TXUSRCLK2 (TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GTXTXN (GTXTXN_OUT),
.GTXTXP (GTXTXP_OUT),
.TXBUFDIFFCTRL (3'b100),
.TXDIFFCTRL (4'b1010),
.TXDIFFPD (tied_to_ground_i),
.TXINHIBIT (tied_to_ground_i),
.TXMAINCURSOR (7'b0000000),
.TXPDELECIDLEMODE (tied_to_ground_i),
.TXPISOPD (tied_to_ground_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.TXRATE (tied_to_ground_vec_i[2:0]),
.TXRATEDONE (),
.TXRESETDONE (TXRESETDONE_OUT),
//------------------- Transmit Ports - TX PRBS Generator -------------------
.TXPRBSFORCEERR (tied_to_ground_i),
.TXPRBSSEL (tied_to_ground_vec_i[2:0]),
//------------------ Transmit Ports - TX Polarity Control ------------------
.TXPOLARITY (tied_to_ground_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXDEEMPH (tied_to_ground_i),
.TXDETECTRX (tied_to_ground_i),
.TXELECIDLE (TXELECIDLE_IN),
.TXMARGIN (tied_to_ground_vec_i[2:0]),
.TXSWING (tied_to_ground_i),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.TXCOMFINISH (),
.TXCOMINIT (tied_to_ground_i),
.TXCOMSAS (tied_to_ground_i),
.TXCOMWAKE (tied_to_ground_i)
);
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_init.v
Executable
+617
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@@ -0,0 +1,617 @@
//------------------------------------------------------------------------------
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : gige_sfp_mdio_gtwizard_init.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
// Description : This module instantiates the modules required for
// reset and initialisation of the Transceiver
//
// Module GTWIZARD_init
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
`define DLY #1
//***********************************Entity Declaration************************
module gige_sfp_mdio_GTWIZARD_init #
(
parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // Simulation setting for GT SecureIP model
parameter EXAMPLE_SIMULATION = 0, // Set to 1 for simulation
parameter EQ_MODE = "DFE",
parameter EXAMPLE_USE_CHIPSCOPE = 0 // Set to 1 to use Chipscope to drive resets
)
(
input SYSCLK_IN,
input SOFT_RESET_IN,
output GT0_TX_FSM_RESET_DONE_OUT,
output GT0_RX_FSM_RESET_DONE_OUT,
input GT0_DATA_VALID_IN,
//_________________________________________________________________________
//GT0 (X1Y4)
//____________________________CHANNEL PORTS________________________________
//----------------------- Channel - Ref Clock Ports ------------------------
input GT0_GTREFCLK0_IN,
//------------------------------ Channel PLL -------------------------------
output GT0_CPLLFBCLKLOST_OUT,
output GT0_CPLLLOCK_OUT,
input GT0_CPLLLOCKDETCLK_IN,
input GT0_CPLLRESET_IN,
//----------------------------- Eye Scan Ports -----------------------------
output GT0_EYESCANDATAERROR_OUT,
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] GT0_LOOPBACK_IN,
input [1:0] GT0_RXPD_IN,
input [1:0] GT0_TXPD_IN,
//----------------------------- Receive Ports ------------------------------
input GT0_RXUSERRDY_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] GT0_RXCHARISCOMMA_OUT,
output [1:0] GT0_RXCHARISK_OUT,
output [1:0] GT0_RXDISPERR_OUT,
output [1:0] GT0_RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] GT0_RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
input GT0_RXMCOMMAALIGNEN_IN,
input GT0_RXPCOMMAALIGNEN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
input GT0_GTRXRESET_IN,
output [15:0] GT0_RXDATA_OUT,
output GT0_RXOUTCLK_OUT,
input GT0_RXUSRCLK_IN,
input GT0_RXUSRCLK2_IN,
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
input GT0_RXDFELPMRESET_IN,
output [6:0] GT0_RXMONITOROUT_OUT,
input [1:0] GT0_RXMONITORSEL_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input GT0_GTXRXN_IN,
input GT0_GTXRXP_IN,
output GT0_RXCDRLOCK_OUT,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input GT0_RXBUFRESET_IN,
output [2:0] GT0_RXBUFSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
output GT0_RXRESETDONE_OUT,
//----------------------------- Transmit Ports -----------------------------
input GT0_TXUSERRDY_IN,
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [1:0] GT0_TXCHARDISPMODE_IN,
input [1:0] GT0_TXCHARDISPVAL_IN,
input [1:0] GT0_TXCHARISK_IN,
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
output [1:0] GT0_TXBUFSTATUS_OUT,
//---------------- Transmit Ports - TX Data Path interface -----------------
input GT0_GTTXRESET_IN,
input [15:0] GT0_TXDATA_IN,
output GT0_TXOUTCLK_OUT,
output GT0_TXOUTCLKFABRIC_OUT,
output GT0_TXOUTCLKPCS_OUT,
input GT0_TXUSRCLK_IN,
input GT0_TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output GT0_GTXTXN_OUT,
output GT0_GTXTXP_OUT,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
output GT0_TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input GT0_TXELECIDLE_IN,
//____________________________COMMON PORTS________________________________
//-------------------- Common Block - Ref Clock Ports ---------------------
input GT0_GTREFCLK0_COMMON_IN,
//----------------------- Common Block - QPLL Ports ------------------------
output GT0_QPLLLOCK_OUT,
input GT0_QPLLLOCKDETCLK_IN,
input GT0_QPLLRESET_IN
);
//***********************************Parameter Declarations********************
parameter STABLE_CLOCK_PERIOD = 5; //Period of the stable clock driving this state-machine, unit is [ns]
//Typical CDRLOCK Time is 50,000UI, as per DS183
parameter RX_CDRLOCK_TIME = (EXAMPLE_SIMULATION == 1) ? 1000 : 50000/1.25;
integer WAIT_TIME_CDRLOCK = RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;
parameter integer LPM_ADAPT_LOCK_TIMER = (EXAMPLE_SIMULATION == 1) ? 5 : (13*100)/1.25;
parameter integer DFE_ADAPT_LOCK_TIMER = (13*100)/1.25;
//-------------------------- GT Wrapper Wires ------------------------------
wire gt0_cpllreset_i;
wire gt0_cpllreset_t;
wire gt0_cpllrefclklost_i;
wire gt0_cplllock_i;
wire gt0_txresetdone_i;
wire gt0_rxresetdone_i;
wire gt0_gttxreset_i;
wire gt0_gttxreset_t;
wire gt0_gtrxreset_i;
wire gt0_gtrxreset_t;
wire gt0_txpcsreset_i;
wire gt0_rxpcsreset_i;
wire gt0_rxpmareset_i;
wire gt0_rxdfelpmreset_i;
wire gt0_txuserrdy_i;
wire gt0_txuserrdy_t;
wire gt0_rxuserrdy_i;
wire gt0_rxuserrdy_t;
wire gt0_rxdfeagchold_i;
wire gt0_rxdfelfhold_i;
wire gt0_rxlpmlfhold_i;
wire gt0_rxlpmhfhold_i;
wire [8:0] gt0_drpaddr_i;
wire [15:0] gt0_drpdi_i;
wire [15:0] gt0_drpdo_o;
wire gt0_drpen_i;
wire gt0_drpwe_i;
wire gt0_drprdy_o;
wire [8:0] gt0_drpaddr_int;
wire [15:0] gt0_drpdi_int;
wire [15:0] gt0_drpdo_int;
wire gt0_drpen_int;
wire gt0_drpwe_int;
wire gt0_drprdy_int;
wire [6:0] gt0_rxmonitorout_o;
wire [1:0] gt0_rxmonitorsel_i;
wire gt0_adapt_done;
wire gt0_qpllreset_i;
wire gt0_qpllreset_t;
wire gt0_qpllrefclklost_i;
wire gt0_qplllock_i;
//------------------------------- Global Signals -----------------------------
wire tied_to_ground_i;
wire tied_to_vcc_i;
wire gt0_rxoutclk_i;
wire gt0_rxoutclk_i_buf;
wire gt0_rxoutclk_i_bufmr;
wire gt0_recclk_stable_i;
wire gt0_recclk_mon_i;
wire gt0_recclk_monitor_restart_i;
integer rx_cdrlock_counter= 0;
reg rx_cdrlocked;
wire gt0_gttxreset_gt;
wire gt0_gtrxreset_gt;
//**************************** Main Body of Code *******************************
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_vcc_i = 1'b1;
assign gt0_gttxreset_gt = gt0_gttxreset_t || GT0_GTTXRESET_IN;
assign gt0_gtrxreset_gt = gt0_gtrxreset_t || GT0_GTRXRESET_IN;
// Place the Rx recovered clock on a Global Clock Buffer (it may be possible
// to switch this for a BUFHCE)
BUFG rxrecclkbufg (
.I (gt0_rxoutclk_i),
.O (gt0_rxoutclk_i_buf)
);
// ----------------------------- The GT Wrapper -----------------------------
// Use the instantiation template in the example directory to add the GT wrapper to your design.
// In this example, the wrapper is wired up for basic operation with a frame generator and frame
// checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
// enabled, bonding should occur after alignment.
gige_sfp_mdio_GTWIZARD #
(
.WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP)
)
GTWIZARD_i
(
//_____________________________________________________________________
//_____________________________________________________________________
//GT0 (X1Y4)
//-------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
.GT0_DRPADDR_IN (9'b0),
.GT0_DRPCLK_IN (1'b0),
.GT0_DRPDI_IN (16'b0),
.GT0_DRPDO_OUT (),
.GT0_DRPEN_IN (1'b0),
.GT0_DRPRDY_OUT (),
.GT0_DRPWE_IN (1'b0),
//----------------------- Channel - Ref Clock Ports ------------------------
.GT0_GTREFCLK0_IN (GT0_GTREFCLK0_IN),
//------------------------------ Channel PLL -------------------------------
.GT0_CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT),
.GT0_CPLLLOCK_OUT (gt0_cplllock_i),
.GT0_CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN),
.GT0_CPLLREFCLKLOST_OUT (gt0_cpllrefclklost_i),
.GT0_CPLLRESET_IN (gt0_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT0_EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT0_LOOPBACK_IN (GT0_LOOPBACK_IN),
.GT0_RXPD_IN (GT0_RXPD_IN),
.GT0_TXPD_IN (GT0_TXPD_IN),
//----------------------------- Receive Ports ------------------------------
.GT0_RXUSERRDY_IN (gt0_rxuserrdy_i),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.GT0_RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT),
.GT0_RXCHARISK_OUT (GT0_RXCHARISK_OUT),
.GT0_RXDISPERR_OUT (GT0_RXDISPERR_OUT),
.GT0_RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT0_RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT0_RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN),
.GT0_RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT0_GTRXRESET_IN (gt0_gtrxreset_gt),
.GT0_RXDATA_OUT (GT0_RXDATA_OUT),
.GT0_RXOUTCLK_OUT (gt0_rxoutclk_i),
.GT0_RXPCSRESET_IN (gt0_rxpcsreset_i),
.GT0_RXPMARESET_IN (gt0_rxpmareset_i),
.GT0_RXUSRCLK_IN (GT0_RXUSRCLK_IN),
.GT0_RXUSRCLK2_IN (GT0_RXUSRCLK2_IN),
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
.GT0_RXDFEAGCHOLD_IN (gt0_rxdfeagchold_i),
.GT0_RXDFELPMRESET_IN (gt0_rxdfelpmreset_i),
.GT0_RXMONITOROUT_OUT (gt0_rxmonitorout_o),
.GT0_RXMONITORSEL_IN (2'b0),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT0_GTXRXN_IN (GT0_GTXRXN_IN),
.GT0_GTXRXP_IN (GT0_GTXRXP_IN),
.GT0_RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT0_RXBUFRESET_IN (GT0_RXBUFRESET_IN),
.GT0_RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT0_RXRESETDONE_OUT (gt0_rxresetdone_i),
//----------------------------- Transmit Ports -----------------------------
.GT0_TXUSERRDY_IN (gt0_txuserrdy_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.GT0_TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN),
.GT0_TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN),
.GT0_TXCHARISK_IN (GT0_TXCHARISK_IN),
//---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
.GT0_TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT0_GTTXRESET_IN (gt0_gttxreset_gt),
.GT0_TXDATA_IN (GT0_TXDATA_IN),
.GT0_TXOUTCLK_OUT (GT0_TXOUTCLK_OUT),
.GT0_TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT),
.GT0_TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT),
.GT0_TXPCSRESET_IN (gt0_txpcsreset_i),
.GT0_TXUSRCLK_IN (GT0_TXUSRCLK_IN),
.GT0_TXUSRCLK2_IN (GT0_TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT0_GTXTXN_OUT (GT0_GTXTXN_OUT),
.GT0_GTXTXP_OUT (GT0_GTXTXP_OUT),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT0_TXRESETDONE_OUT (gt0_txresetdone_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.GT0_TXELECIDLE_IN (GT0_TXELECIDLE_IN),
//____________________________COMMON PORTS________________________________
//-------------------- Common Block - Ref Clock Ports ---------------------
.GT0_GTREFCLK0_COMMON_IN (GT0_GTREFCLK0_COMMON_IN),
//----------------------- Common Block - QPLL Ports ------------------------
.GT0_QPLLLOCK_OUT (gt0_qplllock_i),
.GT0_QPLLLOCKDETCLK_IN (GT0_QPLLLOCKDETCLK_IN),
.GT0_QPLLREFCLKLOST_OUT (gt0_qpllrefclklost_i),
.GT0_QPLLRESET_IN (gt0_qpllreset_i)
);
assign gt0_rxpcsreset_i = tied_to_ground_i;
assign gt0_txpcsreset_i = tied_to_ground_i;
assign gt0_rxpmareset_i = tied_to_ground_i;
assign gt0_rxdfelpmreset_i = tied_to_ground_i;
assign GT0_CPLLLOCK_OUT = gt0_cplllock_i;
assign GT0_TXRESETDONE_OUT = gt0_txresetdone_i;
assign GT0_RXRESETDONE_OUT = gt0_rxresetdone_i;
assign GT0_RXOUTCLK_OUT = gt0_rxoutclk_i_buf;
assign GT0_QPLLLOCK_OUT = gt0_qplllock_i;
generate
if (EXAMPLE_USE_CHIPSCOPE == 1)
begin : chipscope
assign gt0_cpllreset_i = GT0_CPLLRESET_IN;
assign gt0_gttxreset_i = GT0_GTTXRESET_IN;
assign gt0_gtrxreset_i = GT0_GTRXRESET_IN;
assign gt0_txuserrdy_i = GT0_TXUSERRDY_IN;
assign gt0_rxuserrdy_i = GT0_RXUSERRDY_IN;
assign gt0_qpllreset_i = GT0_QPLLRESET_IN;
end
endgenerate
generate
if (EXAMPLE_USE_CHIPSCOPE == 0)
begin : no_chipscope
assign gt0_cpllreset_i = gt0_cpllreset_t;
assign gt0_gttxreset_i = gt0_gttxreset_t;
assign gt0_gtrxreset_i = gt0_gtrxreset_t;
assign gt0_txuserrdy_i = gt0_txuserrdy_t;
assign gt0_rxuserrdy_i = gt0_rxuserrdy_t;
assign gt0_qpllreset_i = gt0_qpllreset_t;
end
endgenerate
gige_sfp_mdio_TX_STARTUP_FSM #
(
.GT_TYPE ("GTX"), //GTX or GTH or GTP
.STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), // Period of the stable clock driving this state-machine, unit is [ns]
.RETRY_COUNTER_BITWIDTH (8),
.TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must
.RX_QPLL_USED ("FALSE"), // share these two generic values
.PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
gt0_txresetfsm_i
(
.STABLE_CLOCK (SYSCLK_IN),
.TXUSERCLK (GT0_TXUSRCLK_IN),
.SOFT_RESET (SOFT_RESET_IN),
.QPLLREFCLKLOST (tied_to_ground_i),
.CPLLREFCLKLOST (gt0_cpllrefclklost_i),
.QPLLLOCK (tied_to_vcc_i),
.CPLLLOCK (gt0_cplllock_i),
.TXRESETDONE (gt0_txresetdone_i),
.MMCM_LOCK (tied_to_vcc_i),
.GTTXRESET (gt0_gttxreset_t),
.MMCM_RESET (),
.QPLL_RESET (),
.CPLL_RESET (gt0_cpllreset_t),
.TX_FSM_RESET_DONE (GT0_TX_FSM_RESET_DONE_OUT),
.TXUSERRDY (gt0_txuserrdy_t),
.RUN_PHALIGNMENT (),
.RESET_PHALIGNMENT (),
.PHALIGNMENT_DONE (tied_to_vcc_i),
.RETRY_COUNTER ()
);
gige_sfp_mdio_RX_STARTUP_FSM #
(
.EXAMPLE_SIMULATION (EXAMPLE_SIMULATION),
.GT_TYPE ("GTX"), //GTX or GTH or GTP
.EQ_MODE (EQ_MODE), //Rx Equalization Mode - Set to DFE or LPM
.STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), //Period of the stable clock driving this state-machine, unit is [ns]
.RETRY_COUNTER_BITWIDTH (8),
.TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must
.RX_QPLL_USED ("FALSE"), // share these two generic values
.PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
gt0_rxresetfsm_i
(
.STABLE_CLOCK (SYSCLK_IN),
.RXUSERCLK (GT0_RXUSRCLK_IN),
.SOFT_RESET (SOFT_RESET_IN),
.QPLLREFCLKLOST (tied_to_ground_i),
.CPLLREFCLKLOST (gt0_cpllrefclklost_i),
.QPLLLOCK (tied_to_vcc_i),
.CPLLLOCK (gt0_cplllock_i),
.RXRESETDONE (gt0_rxresetdone_i),
.MMCM_LOCK (tied_to_vcc_i),
.RECCLK_STABLE (gt0_recclk_stable_i),
.RECCLK_MONITOR_RESTART (gt0_recclk_monitor_restart_i),
.DATA_VALID (GT0_DATA_VALID_IN),
.TXUSERRDY (tied_to_vcc_i),
.GTRXRESET (gt0_gtrxreset_t),
.MMCM_RESET (),
.QPLL_RESET (),
.CPLL_RESET (),
.RX_FSM_RESET_DONE (GT0_RX_FSM_RESET_DONE_OUT),
.RXUSERRDY (gt0_rxuserrdy_t),
.RUN_PHALIGNMENT (),
.RESET_PHALIGNMENT (),
.PHALIGNMENT_DONE (tied_to_vcc_i),
.RXDFEAGCHOLD (gt0_rxdfeagchold_i),
.RXDFELFHOLD (gt0_rxdfelfhold_i),
.RXLPMLFHOLD (gt0_rxlpmlfhold_i),
.RXLPMHFHOLD (gt0_rxlpmhfhold_i),
.RETRY_COUNTER ()
);
//generate
//if (EQ_MODE=="DFE")
//GTWIZARD_ADAPT_TOP_DFE #
// (
// .AGC_TIMER (DFE_ADAPT_LOCK_TIMER)
// )
//gt0_adapt_dfe_i
// (
// .EN(1'b1),
// .CTLE3_COMP_EN(1'b1),
// .GTRXRESET(gt0_gtrxreset_i), //reset going to the GT, coming from either chipscope or TB
// .RXPMARESET(gt0_rxpmareset_i),//tied to ground, going to GT
// .RXDFELPMRESET(gt0_rxdfelpmreset_i),//tied to groun, going to GT
// .DCLK(GT0_DRPCLK_IN),
// .DO(gt0_drpdo_int),
// .DRDY(gt0_drprdy_int),
// .DADDR(gt0_drpaddr_int),//out 8:0
// .DI(gt0_drpdi_int), //out
// .DEN(gt0_drpen_int), //out
// .DWE(gt0_drpwe_int), //out
// .RXMONITOR(gt0_rxmonitorout_o),
// .RXMONITORSEL(gt0_rxmonitorsel_i), //out
// .AGCHOLD(gt0_rxdfeagchold_i),//out
// .KLHOLD(), //out
// .KHHOLD(),//out
// .DONE(gt0_adapt_done),//out
// .DEBUG()//out
// );
//else if (EQ_MODE=="LPM")
//GTWIZARD_ADAPT_TOP_LPM #
// (
// .TIMER (LPM_ADAPT_LOCK_TIMER)
// )
//gt0_adapt_lpm_i
// (
// .EN(1'b1),
// .GTRXRESET(gt0_gtrxreset_i), //reset going to the GT, coming from either chipscope or TB
// .RXPMARESET(gt0_rxpmareset_i),//tied to ground, going to GT
// .RXDFELPMRESET(gt0_rxdfelpmreset_i),//tied to groun, going to GT
// .DCLK(GT0_DRPCLK_IN),
// .DO(gt0_drpdo_int),
// .DRDY(gt0_drprdy_int),
// .DADDR(gt0_drpaddr_int),
// .DI(gt0_drpdi_int),
// .DEN(gt0_drpen_int),
// .DWE(gt0_drpwe_int),
// .KLHOLD(),
// .KHHOLD(),
// .DONE(gt0_adapt_done),
// .DEBUG()
// );
//endgenerate
//
// assign gt0_drpaddr_i = gt0_adapt_done ? GT0_DRPADDR_IN : gt0_drpaddr_int;
// assign gt0_drpdi_i = gt0_adapt_done ? GT0_DRPDI_IN : gt0_drpdi_int;
// assign gt0_drpen_i = gt0_adapt_done ? GT0_DRPEN_IN : gt0_drpen_int;
// assign gt0_drpwe_i = gt0_adapt_done ? GT0_DRPWE_IN : gt0_drpwe_int;
// assign GT0_DRPDO_OUT = gt0_adapt_done ? gt0_drpdo_o : 16'b0;
// assign GT0_DRPRDY_OUT = gt0_adapt_done ? gt0_drprdy_o : 1'b0;
//
// assign gt0_drpdo_int = gt0_drpdo_o;
// assign gt0_drprdy_int = gt0_drprdy_o;
//
always @(posedge SYSCLK_IN)
begin
if(gt0_gtrxreset_i)
begin
rx_cdrlocked <= `DLY 1'b0;
rx_cdrlock_counter <= `DLY 0;
end
else if (rx_cdrlock_counter == WAIT_TIME_CDRLOCK)
begin
rx_cdrlocked <= `DLY 1'b1;
rx_cdrlock_counter <= `DLY rx_cdrlock_counter;
end
else
rx_cdrlock_counter <= `DLY rx_cdrlock_counter + 1;
end
//The Recovered Clock Monitor can be used, only when the
//Reference Clock frequency matches the Recovered Clock Frequency.
//For all other cases, CDR Lock time of 50,000UI is used as an
//indicator for Recovered Clock stable
gige_sfp_mdio_RECCLK_MONITOR #
(
.COUNTER_UPPER_VALUE (15), //ppm counter. For 2^20 cntr.
.GCLK_COUNTER_UPPER_VALUE (15), //ppm counter. For 2^20 cntr.
.CLOCK_PULSES (5000),
.EXAMPLE_SIMULATION (EXAMPLE_SIMULATION)
)
gt0_rx_recclk_mon_i
(
.GT_RST (gt0_gtrxreset_i),
.REF_CLK (GT0_GTREFCLK0_IN),
.RX_REC_CLK0 (gt0_rxoutclk_i_buf),
.SYSTEM_CLK (SYSCLK_IN),
.PLL_LK_DET (tied_to_vcc_i),
.RECCLK_STABLE (gt0_recclk_mon_i),
.EXEC_RESTART (gt0_recclk_monitor_restart_i)
);
assign gt0_recclk_stable_i = rx_cdrlocked;
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_recclk_monitor.v
Executable
+410
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@@ -0,0 +1,410 @@
//////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : recclk_monitor.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Description : This module is the ppm monitor between the
// GT RxRecClk and the reference clock
//
// This module will declare that the Rx RECCLK is stable if the
// recovered clock is within +/-5000PPM of the reference clock.
//
//
// There are 3 counters running on local clocks for both
// recovered clocks and one for the reference clock. The
// COUNTER_UPPER_VALUE parameter is the width of these
// counters. The PPM offset is checked when these counters
// roll over.
//
// There is also a counter running on the system clock.
// This can be running at a much lower frequency and is
// running on a BUFG.
//
// To set the parameters correctly here is what you need to
// do. Lets assume taht the reference and recovered
// clocks are running at 156MHz and the system clock is
// running at 50MHz.
//
// To ensure that the interval is long enough we want to
// to make the COUNTER_UPPER_VALUE to be reasonable. The
// CLOCK_PULSES is the number of sytem clock cycles we can
// expect to be off based on these frequencies:
//
// Example: Rec Clk and Ref Clk 156MHz, System clock 50MHz
// PPM Offset to tolerate +/- 5000PPM
//
// COUNTER_UPPER_VALUE = 15 -> 2^15 counter = 32768
// GCLK_COUNTER_UPPER_VALUE = 15 -> 2^15 counter = 32768
//
// PPM OFFSET = 5000 => 32768 * 5000/1000000 = 164
//
// Now we are using the system clock to do the
// calculations, therfore we need to scale the PPM_OFFSET
// accordingly.
//
// CLOCK_PULSES = PPM_OFFSET * sysclk_freq/refclk_freq
// = 164 * 50/156 = 52
//
//
// When the counters are checked if they are off by less
// than 52, we can delcare that the particular RECCLK is
// stable.
//
// All FFs that have the _meta are metastability FFs and
// can be ignored from a timing perspective. The following
// constraint can be added to the UCF to ensure that they
// are ignored:
//
// INST "*_meta" TNM = "METASTABILITY_FFS";
// TIMESPEC "TS_METASTABILITY" = FROM FFS TO "METASTABILITY_FFS" TIG;
//
// Module gige_sfp_mdio_RECCLK_MONITOR
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*******************************************************************************
`timescale 1ns / 1ps
`define DLY #1
module gige_sfp_mdio_RECCLK_MONITOR #
(
parameter COUNTER_UPPER_VALUE = 20, //ppm counter. For 2^20 counter.
parameter GCLK_COUNTER_UPPER_VALUE = 20, //ppm counter. For 2^20 counter.
parameter CLOCK_PULSES = 5000,
parameter EXAMPLE_SIMULATION = 0
)
(
input wire GT_RST, // Active high async reset.
input wire REF_CLK,
input wire RX_REC_CLK0,
input wire SYSTEM_CLK,
input wire PLL_LK_DET,
output wire RECCLK_STABLE,
output reg EXEC_RESTART
);
//===============================================================================
// Register/Wire declaration
//===============================================================================
localparam WAIT_FOR_LOCK = 6'b00_0001;
localparam REFCLK_EVENT = 6'b00_0010;
localparam CALC_PPM_DIFF = 6'b00_0100;
localparam CHECK_SIGN = 6'b00_1000;
localparam COMP_CNTR = 6'b01_0000;
localparam RESTART = 6'b10_0000;
reg [COUNTER_UPPER_VALUE -1 :0] ref_clk_cnt;
reg [COUNTER_UPPER_VALUE -1 :0] rec_clk0_cnt;
reg [2:1] rec_clk0_msb;
reg [2:1] ref_clk_msb;
reg rec_clk_0_msb_meta /*synthesis syn_keep = 1 */;
reg ref_clk_msb_meta /*synthesis syn_keep = 1 */;
reg [GCLK_COUNTER_UPPER_VALUE -1 :0] sys_clk_counter;
reg [GCLK_COUNTER_UPPER_VALUE -1 :0] rec_clk0_compare_cnt_latch;
reg [GCLK_COUNTER_UPPER_VALUE -1 :0] ref_clk_compare_cnt_latch;
reg g_clk_rst_meta /*synthesis syn_keep = 1 */;
reg g_clk_rst_sync;
reg gt_pll_locked_meta /*synthesis syn_keep = 1 */;
reg gt_pll_locked_sync;
reg reset_logic_rec0_meta /*synthesis syn_keep = 1 */;
reg reset_logic_rec0_sync;
reg reset_logic_ref_meta /*synthesis syn_keep = 1 */;
reg reset_logic_ref_sync;
reg [5:0] state;
reg rec_clk0_edge_event;
reg [1:0] ref_clk_edge_event;
reg [GCLK_COUNTER_UPPER_VALUE -1 : 0] ppm0;
reg recclk_stable0_int;
reg recclk_stable0;
reg [3:0] reset_logic;
wire rec_clk0_edge;
wire ref_clk_edge;
reg [1:0] ref_clk_edge_rt;
wire g_clk_rst;
//===============================================================================
// Main Logic
//===============================================================================
always @ (posedge RX_REC_CLK0) begin
reset_logic_rec0_meta <= `DLY reset_logic[3];
reset_logic_rec0_sync <= `DLY reset_logic_rec0_meta;
end
always @ (posedge RX_REC_CLK0) begin
if (reset_logic_rec0_sync) begin
rec_clk0_cnt <= `DLY 'h0;
end
else begin
rec_clk0_cnt <= `DLY rec_clk0_cnt +1;
end
end
always @ (posedge REF_CLK) begin
reset_logic_ref_meta <= `DLY reset_logic[3];
reset_logic_ref_sync <= `DLY reset_logic_ref_meta;
end
always @ (posedge REF_CLK) begin
if (reset_logic_ref_sync)
ref_clk_cnt <= `DLY 'h0;
else begin
ref_clk_cnt <= `DLY ref_clk_cnt +1;
end
end
//===============================================================================
// PPM Monitor
//===============================================================================
/*
We will also need 3 counters running on a global clock, one corresponding to each of the local counters. For this example I will use a 50MHz clock, but it can be anything. We use the global clock to sample the 20th bit of the local counter, it has to be sampled twice for metastability. Whenever we detect a falling edge on that signal, it means that the counter has rolled over. We use this to latch the current count value to FFs and reset the counter. Now you have the amount of time it took to count ~1M clock cycles. In an ideal world, this would be 6.7ms or 335,602 50MHz clock periods. You would do the same for the reference clock and then you could compare both counts and ensure that the difference is less than 1,678 (33.55us), if its not then you know you have exceeded your PPM limit. All the counts could be set as parameters and could easily be adjusted based on the global clock frequency and the PPM offset required.
*/
// Synchronize reset to global Clock domain
always @ (posedge SYSTEM_CLK) begin
g_clk_rst_meta <= `DLY GT_RST;
g_clk_rst_sync <= `DLY g_clk_rst_meta;
gt_pll_locked_meta <= `DLY PLL_LK_DET;
gt_pll_locked_sync <= `DLY gt_pll_locked_meta;
end
assign g_clk_rst = g_clk_rst_sync;
assign gt_pll_locked = gt_pll_locked_sync;
generate
if (EXAMPLE_SIMULATION==0 )
begin : HW_CIRCUITRY
// Main FSM
always @ (posedge SYSTEM_CLK)
begin
if (g_clk_rst) begin
state <= `DLY WAIT_FOR_LOCK;
ppm0 <= `DLY {GCLK_COUNTER_UPPER_VALUE-1 {1'b1}};
recclk_stable0 <= `DLY 1'b0;
EXEC_RESTART <= `DLY 1'b0;
end
else begin
EXEC_RESTART <= `DLY 1'b0;
case (state)
WAIT_FOR_LOCK: begin
if (gt_pll_locked) begin
if (ref_clk_edge_event == 2'b01) state <= `DLY REFCLK_EVENT;
else state <= `DLY WAIT_FOR_LOCK;
end
else begin
state <= `DLY WAIT_FOR_LOCK;
end
end
REFCLK_EVENT: begin
if (ref_clk_edge_event == 2'b11) begin // two reference couter periods
state <= `DLY CALC_PPM_DIFF;
end
else begin
state <= `DLY REFCLK_EVENT;
end
end
CALC_PPM_DIFF: begin
if (rec_clk0_edge_event) begin
ppm0 <= `DLY rec_clk0_compare_cnt_latch + ref_clk_compare_cnt_latch;
end
state <= `DLY CHECK_SIGN;
end
CHECK_SIGN: begin
//check the sign bit - if 1'b1, then convert to binary.
if (ppm0[GCLK_COUNTER_UPPER_VALUE-1]) ppm0 <= `DLY ~ppm0 +1;
state <= `DLY COMP_CNTR;
end
COMP_CNTR: begin
if (ppm0 < CLOCK_PULSES)
recclk_stable0 <= `DLY 1'b1;
else
recclk_stable0 <= `DLY 1'b0;
state <= `DLY RESTART;
end
RESTART: begin
state <= `DLY WAIT_FOR_LOCK;
EXEC_RESTART <= `DLY 1'b1;
end
default: begin
state <= `DLY WAIT_FOR_LOCK;
ppm0 <= `DLY {GCLK_COUNTER_UPPER_VALUE-1 {1'b1}};
recclk_stable0 <= `DLY 1'b0;
end
endcase
end
end
// On clock roll-over, latch counter value once and event occurance.
always @ (posedge SYSTEM_CLK)
begin
if (reset_logic[3]) begin
rec_clk0_edge_event <= `DLY 1'b0;
ref_clk_edge_event <= `DLY 2'b00;
rec_clk0_compare_cnt_latch <= `DLY 'h0;
ref_clk_compare_cnt_latch <= `DLY 'h0;
ref_clk_edge_rt <= `DLY 2'b00;
end
else begin
if (rec_clk0_edge & (~rec_clk0_edge_event) ) begin
rec_clk0_edge_event <= `DLY 1'b1;
rec_clk0_compare_cnt_latch <= `DLY sys_clk_counter;
end
if (ref_clk_edge) begin
ref_clk_edge_event <= `DLY {ref_clk_edge_event,1'b1};
//only latch it the first time around
if (~ref_clk_edge_event[0])
ref_clk_compare_cnt_latch <= `DLY sys_clk_counter;
end
ref_clk_edge_rt <= `DLY {ref_clk_edge_rt[0],ref_clk_edge};
//take the 2's complement number after we latched it
if ((ref_clk_edge_event == 2'b01) && (ref_clk_edge_rt==2'b01))
ref_clk_compare_cnt_latch <= `DLY (~ref_clk_compare_cnt_latch) +1;
end
end
// increment clock counters'
always @ (posedge SYSTEM_CLK)
begin
if (reset_logic[3]) begin
sys_clk_counter <= `DLY {GCLK_COUNTER_UPPER_VALUE{1'b0}};
end
else begin
sys_clk_counter <= `DLY sys_clk_counter + 1;
end
end
always @ (posedge SYSTEM_CLK)
begin
if (reset_logic[3]) begin
rec_clk_0_msb_meta <= `DLY 1'b0;
ref_clk_msb_meta <= `DLY 1'b0;
rec_clk0_msb <= `DLY 2'b00;
ref_clk_msb <= `DLY 2'b00;
end
else begin // double flop msb count bit to system clock domain
rec_clk_0_msb_meta <= `DLY rec_clk0_cnt[COUNTER_UPPER_VALUE-1];
rec_clk0_msb <= `DLY {rec_clk0_msb[1],rec_clk_0_msb_meta};
ref_clk_msb_meta <= `DLY ref_clk_cnt[COUNTER_UPPER_VALUE-1];
ref_clk_msb <= `DLY {ref_clk_msb[1],ref_clk_msb_meta};
end
end
//falling edge detect
assign rec_clk0_edge = (rec_clk0_msb[2] && ~rec_clk0_msb[1]);
assign ref_clk_edge = (ref_clk_msb[2] && ~ref_clk_msb[1]);
// Manage counter reset/restart
always @ (posedge SYSTEM_CLK)
begin
if (g_clk_rst) begin
reset_logic <= `DLY 'hf;
end
else begin
if (state == RESTART) reset_logic <= `DLY 4'b1111;
else reset_logic <= `DLY reset_logic << 1;
end
end
assign RECCLK_STABLE = recclk_stable0;
end
endgenerate
generate
if (EXAMPLE_SIMULATION == 1)
begin:sim
//This Generate-branch is ONLY FOR SIMULATION and is not implemented in HW.
//The whole purpose of this shortcut-branch is to avoid huge simulation-
//times.
always @(posedge SYSTEM_CLK)
begin
if( GT_RST)
recclk_stable0_int <= `DLY 1'b0;
else
recclk_stable0_int <= `DLY PLL_LK_DET;
end
assign RECCLK_STABLE = recclk_stable0_int;
end
endgenerate
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v
Executable
+727
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@@ -0,0 +1,727 @@
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : gige_sfp_mdio_rx_startup_fsm.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Description : This module performs RX reset and initialization.
//
//
//
// Module gige_sfp_mdio_rx_startup_fsm
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*****************************************************************************
`timescale 1ns / 1ps
`define DLY #1
module gige_sfp_mdio_RX_STARTUP_FSM #
(
parameter EXAMPLE_SIMULATION = 0, // Set to 1 for Simulation
parameter GT_TYPE = "GTX",
parameter EQ_MODE = "DFE", //Rx Equalization Mode - Set to DFE or LPM
parameter STABLE_CLOCK_PERIOD = 8, //Period of the stable clock driving this state-machine, unit is [ns]
parameter RETRY_COUNTER_BITWIDTH = 8,
parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must
parameter RX_QPLL_USED = "FALSE", // share these two generic values
parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
(
input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB
//or reference-clock present at startup.
input wire RXUSERCLK, //RXUSERCLK as used in the design
input wire SOFT_RESET, //User Reset, can be pulled any time
input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost
input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost
input wire QPLLLOCK, //Lock Detect from the QPLL of the GT
input wire CPLLLOCK, //Lock Detect from the CPLL of the GT
input wire RXRESETDONE,
input wire MMCM_LOCK,
input wire RECCLK_STABLE,
input wire RECCLK_MONITOR_RESTART,
input wire DATA_VALID,
input wire TXUSERRDY, //TXUSERRDY from GT
output reg GTRXRESET = 1'b0,
output reg MMCM_RESET = 1'b1,
output reg QPLL_RESET = 1'b0, //Reset QPLL (only if RX usese QPLL)
output reg CPLL_RESET = 1'b0, //Reset CPLL (only if RX usese CPLL)
output RX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished.
output reg RXUSERRDY = 1'b0,
output wire RUN_PHALIGNMENT,
input wire PHALIGNMENT_DONE,
output reg RESET_PHALIGNMENT = 1'b0,
output reg RXDFEAGCHOLD = 1'b0,
output reg RXDFELFHOLD = 1'b0,
output reg RXLPMLFHOLD = 1'b0,
output reg RXLPMHFHOLD = 1'b0,
output wire [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of
// Retries it took to get the transceiver up and running
);
//Interdependencies:
// * Timing depends on the frequency of the stable clock. Hence counters-sizes
// are calculated at design-time based on the Generics
//
// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
// => signal which PLL has been reset
// *
localparam [3:0]
INIT = 4'b0000,
ASSERT_ALL_RESETS = 4'b0001,
RELEASE_PLL_RESET = 4'b0010,
VERIFY_RECCLK_STABLE = 4'b0011,
RELEASE_MMCM_RESET = 4'b0100,
WAIT_RESET_DONE = 4'b0101,
DO_PHASE_ALIGNMENT = 4'b0110,
MONITOR_DATA_VALID = 4'b0111,
FSM_DONE = 4'b1000;
reg [3:0] rx_state = INIT;
//This function decides how many clock-cycle need to be waited until
// a time-out occurs for bypassing the TX-Buffer
function [12:0] get_max_wait_bypass;
input manual_mode;
reg [12:0] max_wait_cnt;
begin
if (manual_mode == "TRUE")
max_wait_cnt = 5000;
else
max_wait_cnt = 3100;
get_max_wait_bypass = max_wait_cnt;
end
endfunction
localparam MMCM_LOCK_CNT_MAX = 1024;
localparam STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration
localparam WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration
localparam WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin
localparam WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD; //2 ms time-out
localparam WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD; //100 us time-out
localparam WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD; //500 us time-out
localparam WAIT_TIMEOUT_1us = 1000 / STABLE_CLOCK_PERIOD; //1 us time-out
localparam WAIT_TIMEOUT_100us = 100000 / STABLE_CLOCK_PERIOD; //100us time-out
integer WAIT_TIME_ADAPT = (37000000 /1.25)/STABLE_CLOCK_PERIOD;
reg [7:0] init_wait_count = 0;
reg init_wait_done = 1'b0;
reg pll_reset_asserted = 1'b0;
reg rx_fsm_reset_done_int = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg rx_fsm_reset_done_int_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg rx_fsm_reset_done_int_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg rx_fsm_reset_done_int_s3 = 1'b0;
localparam MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1;
reg [7:0] retry_counter_int = 0;
reg [18:0] time_out_counter = 0;
reg [1:0] recclk_mon_restart_count = 0 ;
reg recclk_mon_count_reset = 0;
reg reset_time_out = 1'b0;
reg time_out_2ms = 1'b0; //--\Flags that the various time-out points
reg time_tlock_max = 1'b0; //--|have been reached.
reg time_out_500us = 1'b0; //--|
reg time_out_1us = 1'b0; //--|
reg time_out_100us = 1'b0; //--/
reg check_tlock_max = 1'b0;
reg [9:0] mmcm_lock_count = 1'b0;
reg mmcm_lock_int = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg [3:0] mmcm_lock_reclocked = 1'b0;
reg run_phase_alignment_int = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s3 = 1'b0;
localparam MAX_WAIT_BYPASS = 5000;//5000 RXUSRCLK cycles is the max time for Multi Lane designs
reg [12:0] wait_bypass_count = 0;
reg time_out_wait_bypass = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s3 = 1'b0;
wire refclk_lost;
(* ASYNC_REG = "TRUE" *)
reg rxresetdone_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg rxresetdone_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg rxresetdone_s3 = 1'b0;
integer adapt_count = 0;
reg time_out_adapt = 1'b0;
reg adapt_count_reset = 1'b0;
//Alias section, signals used within this module mapped to output ports:
assign RETRY_COUNTER = retry_counter_int;
assign RUN_PHALIGNMENT = run_phase_alignment_int;
assign RX_FSM_RESET_DONE = rx_fsm_reset_done_int;
always @(posedge STABLE_CLOCK)
begin
// The counter starts running when configuration has finished and
// the clock is stable. When its maximum count-value has been reached,
// the 500 ns from Answer Record 43482 have been passed.
if (init_wait_count == WAIT_MAX)
init_wait_done <= `DLY 1'b1;
else
init_wait_count <= `DLY init_wait_count + 1;
end
always @(posedge STABLE_CLOCK)
begin
//This counter monitors, how many retries the CDR Lock Detection
//runs. If during startup too many retries are necessary, the whole
//initialisation-process of the transceivers gets restarted.
if (recclk_mon_count_reset == 1)
recclk_mon_restart_count <= `DLY 0;
else if (RECCLK_MONITOR_RESTART == 1)
begin
if (recclk_mon_restart_count == 3)
recclk_mon_restart_count <= `DLY 0;
else
recclk_mon_restart_count <= `DLY recclk_mon_restart_count + 1;
end
end
generate
if(EXAMPLE_SIMULATION == 1)
begin
always @(posedge STABLE_CLOCK)
begin
time_out_adapt <= `DLY 1'b1;
end
end
else
begin
always @(posedge STABLE_CLOCK)
begin
if (adapt_count_reset == 1'b1)
begin
adapt_count <= `DLY 0;
time_out_adapt <= `DLY 1'b0;
end
else
begin
if (adapt_count >= WAIT_TIME_ADAPT)
time_out_adapt <= `DLY 1'b1;
else
adapt_count <= `DLY adapt_count + 1;
end
end
end
endgenerate
always @(posedge STABLE_CLOCK)
begin
// One common large counter for generating three time-out signals.
// Intermediate time-outs are derived from calculated values, based
// on the period of the provided clock.
if (reset_time_out == 1)
begin
time_out_counter <= `DLY 0;
time_out_2ms <= `DLY 1'b0;
time_tlock_max <= `DLY 1'b0;
time_out_500us <= `DLY 1'b0;
time_out_1us <= `DLY 1'b0;
time_out_100us <= `DLY 1'b0;
end
else
begin
if (time_out_counter == WAIT_TIMEOUT_2ms)
time_out_2ms <= `DLY 1'b1;
else
time_out_counter <= `DLY time_out_counter + 1;
if (time_out_counter > WAIT_TLOCK_MAX && check_tlock_max == 1)
begin
time_tlock_max <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_500us)
begin
time_out_500us <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_1us)
begin
time_out_1us <= `DLY 1'b1;
end
if (time_out_counter == WAIT_TIMEOUT_100us)
begin
time_out_100us <= `DLY 1'b1;
end
end
end
always @(posedge RXUSERCLK)
begin
//The lock-signal from the MMCM is not immediately used but
//enabling a counter. Only when the counter hits its maximum,
//the MMCM is considered as "really" locked.
//The counter avoids that the FSM already starts on only a
//coarse lock of the MMCM (=toggling of the LOCK-signal).
if (MMCM_LOCK == 1'b0)
begin
mmcm_lock_count <= `DLY 0;
mmcm_lock_int <= `DLY 1'b0;
end
else
begin
if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1)
mmcm_lock_count <= `DLY mmcm_lock_count + 1;
else
mmcm_lock_int <= `DLY 1'b1;
end
end
always @(posedge STABLE_CLOCK)
//Reclocking onto the FSM-clock.
begin
if (MMCM_LOCK == 1'b0)
//The reset-signal is here on purpose. This avoids
//getting the shift-register targetted to an SRL.
//The reason for this is that an SRL will not help
//on the cross-clock domain but "real" Flip-flops will.
mmcm_lock_reclocked <= `DLY 4'b0000;
else
begin
mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int;
mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1];
end
end
//Clock Domain Crossing
always @(posedge RXUSERCLK)
begin
run_phase_alignment_int_s1 <= `DLY run_phase_alignment_int;
run_phase_alignment_int_s2 <= `DLY run_phase_alignment_int_s1;
run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2;
rx_fsm_reset_done_int_s1 <= `DLY rx_fsm_reset_done_int;
rx_fsm_reset_done_int_s2 <= `DLY rx_fsm_reset_done_int_s1;
rx_fsm_reset_done_int_s3 <= `DLY rx_fsm_reset_done_int_s2;
end
always @(posedge STABLE_CLOCK)
begin
time_out_wait_bypass_s1 <= `DLY time_out_wait_bypass;
time_out_wait_bypass_s2 <= `DLY time_out_wait_bypass_s1;
time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2;
rxresetdone_s1 <= `DLY RXRESETDONE;
rxresetdone_s2 <= `DLY rxresetdone_s1;
rxresetdone_s3 <= `DLY rxresetdone_s2;
end
always @(posedge RXUSERCLK)
begin
if (run_phase_alignment_int_s3 == 1'b0)
begin
wait_bypass_count <= `DLY 0;
time_out_wait_bypass <= `DLY 1'b0;
end
else if ((run_phase_alignment_int_s3 == 1'b1) && (rx_fsm_reset_done_int_s3 == 1'b0))
begin
if (wait_bypass_count == MAX_WAIT_BYPASS - 1)
time_out_wait_bypass <= `DLY 1'b1;
else
wait_bypass_count <= `DLY wait_bypass_count + 1;
end
end
assign refclk_lost = ( RX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 :
( RX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0;
//FSM for resetting the GTX/GTH/GTP in the 7-series.
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
// Following steps are performed:
// 1) After configuration wait for approximately 500 ns as specified in
// answer-record 43482
// 2) Assert all resets on the GT and on an MMCM potentially connected.
// After that wait until a reference-clock has been detected.
// 3) Release the reset to the GT and wait until the GT-PLL has locked.
// 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
// Also get info from the TX-side which PLL has been reset.
// 5) Wait for the RESET_DONE-signal from the GT.
// 6) Signal to start the phase-alignment procedure and wait for it to
// finish.
// 7) Reset-sequence has successfully run through. Signal this to the
// rest of the design by asserting RX_FSM_RESET_DONE.
always @(posedge STABLE_CLOCK)
begin
if (SOFT_RESET == 1'b1 || (rx_state != INIT && rx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1))
begin
rx_state <= `DLY INIT;
RXUSERRDY <= `DLY 1'b0;
GTRXRESET <= `DLY 1'b0;
MMCM_RESET <= `DLY 1'b1;
rx_fsm_reset_done_int <= `DLY 1'b0;
QPLL_RESET <= `DLY 1'b0;
CPLL_RESET <= `DLY 1'b0;
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
retry_counter_int <= `DLY 0;
run_phase_alignment_int <= `DLY 1'b0;
check_tlock_max <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
recclk_mon_count_reset <= `DLY 1'b1;
adapt_count_reset <= `DLY 1'b1;
RXDFEAGCHOLD <= `DLY 1'b0;
RXDFELFHOLD <= `DLY 1'b0;
RXLPMLFHOLD <= `DLY 1'b0;
RXLPMHFHOLD <= `DLY 1'b0;
end
else
begin
case (rx_state)
INIT :
begin
//Initial state after configuration. This state will be left after
//approx. 500 ns and not be re-entered.
if (init_wait_done == 1'b1)
rx_state <= `DLY ASSERT_ALL_RESETS;
end
ASSERT_ALL_RESETS :
begin
//This is the state into which the FSM will always jump back if any
//time-outs will occur.
//The number of retries is reported on the output RETRY_COUNTER. In
//case the transceiver never comes up for some reason, this machine
//will still continue its best and rerun until the FPGA is turned off
//or the transceivers come up correctly.
if (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE")
begin
if (pll_reset_asserted == 1'b0)
begin
QPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
QPLL_RESET <= `DLY 1'b0;
end
else if (RX_QPLL_USED == "FALSE" && TX_QPLL_USED)
begin
if (pll_reset_asserted == 1'b0)
begin
CPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
CPLL_RESET <= `DLY 1'b0;
end
RXUSERRDY <= `DLY 1'b0;
GTRXRESET <= `DLY 1'b1;
MMCM_RESET <= `DLY 1'b1;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
check_tlock_max <= `DLY 1'b0;
recclk_mon_count_reset <= `DLY 1'b1;
adapt_count_reset <= `DLY 1'b1;
if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) ||
(RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted) ||
(RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 ) ||
(RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 )
)
begin
rx_state <= `DLY RELEASE_PLL_RESET;
reset_time_out <= `DLY 1'b1;
end
end
RELEASE_PLL_RESET :
begin
//PLL-Reset of the GTX gets released and the time-out counter
//starts running.
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
if ((RX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) ||
(RX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1))
begin
rx_state <= `DLY VERIFY_RECCLK_STABLE;
reset_time_out <= `DLY 1'b1;
recclk_mon_count_reset <= `DLY 1'b0;
adapt_count_reset <= `DLY 1'b0;
end
if (time_out_2ms == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
VERIFY_RECCLK_STABLE :
begin
//reset_time_out <= `DLY '0';
//Time-out counter is not released in this state as here the FSM
//does not wait for a certain period of time but checks on the number
//of retries in the CDR PPM detector.
GTRXRESET <= `DLY 1'b0;
if (RECCLK_STABLE == 1'b1)
begin
rx_state <= `DLY RELEASE_MMCM_RESET;
reset_time_out <= `DLY 1'b1;
end
if (recclk_mon_restart_count == 2)
begin
//If two retries are performed in the CDR "Lock" (=CDR PPM-detector)
//the whole initialisation-sequence gets restarted.
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
RELEASE_MMCM_RESET :
begin
//Release of the MMCM-reset. Waiting for the MMCM to lock.
reset_time_out <= `DLY 1'b0;
check_tlock_max <= `DLY 1'b1;
MMCM_RESET <= `DLY 1'b0;
if (mmcm_lock_reclocked[0] == 1'b1)
begin
rx_state <= `DLY WAIT_RESET_DONE;
reset_time_out <= `DLY 1'b1;
end
if (time_tlock_max == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
WAIT_RESET_DONE :
begin
//When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
//If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
if(TXUSERRDY)
RXUSERRDY <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (rxresetdone_s3 == 1'b1)
begin
rx_state <= `DLY DO_PHASE_ALIGNMENT;
reset_time_out <= `DLY 1'b1;
end
if (time_out_500us == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
DO_PHASE_ALIGNMENT :
begin
//The direct handling of the signals for the Phase Alignment is done outside
//this state-machine.
RESET_PHALIGNMENT <= `DLY 1'b0;
run_phase_alignment_int <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (PHALIGNMENT_DONE == 1'b1)
begin
rx_state <= `DLY MONITOR_DATA_VALID;
reset_time_out <= `DLY 1'b1;
end
if (time_out_wait_bypass_s3 == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
begin
retry_counter_int <= `DLY retry_counter_int + 1;
end
rx_state <= `DLY ASSERT_ALL_RESETS;
end
end
MONITOR_DATA_VALID :
begin
reset_time_out <= `DLY 1'b0;
if (DATA_VALID == 1'b0 && time_out_100us == 1'b1)
begin
rx_state <= `DLY ASSERT_ALL_RESETS;
rx_fsm_reset_done_int <= `DLY 1'b0;
end
else if (DATA_VALID == 1'b1)
begin
rx_state <= `DLY FSM_DONE;
rx_fsm_reset_done_int <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
end
end
FSM_DONE :
begin
reset_time_out <= `DLY 1'b0;
if (DATA_VALID == 1'b0)
begin
rx_fsm_reset_done_int <= `DLY 1'b0;
reset_time_out <= `DLY 1'b1;
rx_state <= `DLY MONITOR_DATA_VALID;
end
else if(time_out_1us == 1'b1)
rx_fsm_reset_done_int <= `DLY 1'b1;
if(time_out_adapt)
begin
if((GT_TYPE == "GTX" || GT_TYPE == "GTH") && EQ_MODE == "DFE")
begin
RXDFEAGCHOLD <= `DLY 1'b1;
RXDFELFHOLD <= `DLY 1'b1;
end
else if(GT_TYPE == "GTH" && EQ_MODE == "LPM")
begin
RXLPMHFHOLD <= `DLY 1'b1;
RXLPMLFHOLD <= `DLY 1'b1;
end
end
end
endcase
end
end
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_transceiver.v
Executable
+527
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@@ -0,0 +1,527 @@
//------------------------------------------------------------------------------
// Title : Top-level Transceiver GT wrapper for Ethernet
// Project : Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE
// File : gige_sfp_mdio_transceiver.v
// Author : Xilinx
//------------------------------------------------------------------------------
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This is the top-level Transceiver GT wrapper. It
// instantiates the lower-level wrappers produced by
// the Series-7 FPGA Transceiver GT Wrapper Wizard.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gige_sfp_mdio_transceiver (
input encommaalign,
input loopback,
input powerdown,
input usrclk,
input usrclk2,
input data_valid,
input independent_clock,
input txreset,
input [7:0] txdata,
input txchardispmode,
input txchardispval,
input txcharisk,
input rxreset,
output reg rxchariscomma,
output reg rxcharisk,
output reg [2:0] rxclkcorcnt,
output reg [7:0] rxdata,
output reg rxdisperr,
output reg rxnotintable,
output reg rxrundisp,
output reg rxbuferr,
output reg txbuferr,
output plllkdet,
output txoutclk,
output txn,
output txp,
input rxn,
input rxp,
input gtrefclk,
input pmareset,
input mmcm_locked,
output resetdone
);
//----------------------------------------------------------------------------
// Signal declarations
//----------------------------------------------------------------------------
wire cplllock;
wire gt_reset_rx;
wire gt_reset_tx;
wire resetdone_tx;
wire resetdone_rx;
wire pcsreset;
(* KEEP = "TRUE" *) reg data_valid_reg;
wire data_valid_reg2;
wire [2:0] rxbufstatus;
wire [1:0] txbufstatus;
reg [2:0] rxbufstatus_reg;
reg [1:0] txbufstatus_reg;
wire [1:0] rxclkcorcnt_int;
reg txpowerdown_reg = 1'b0;
reg txpowerdown_double = 1'b0;
reg txpowerdown = 1'b0;
wire [1:0] txpowerdown_int;
// signal used to control sampling during bus width conversions
reg toggle;
// signals reclocked onto the 62.5MHz userclk source of the GT transceiver
wire encommaalign_int;
wire txreset_int;
wire rxreset_int;
// Register transmitter signals from the core
reg [7:0] txdata_reg;
reg txchardispmode_reg;
reg txchardispval_reg;
reg txcharisk_reg;
// Signals for data bus width doubling on the transmitter path from the core
// to the GT transceiver
reg [15:0] txdata_double;
reg [1:0] txchardispmode_double;
reg [1:0] txchardispval_double;
reg [1:0] txcharisk_double;
// Double width signals reclocked onto the 62.5MHz userclk source of the GT
// transceiver
reg [15:0] txdata_int;
reg [1:0] txchardispmode_int;
reg [1:0] txchardispval_int;
reg [1:0] txcharisk_int;
// Double width signals output from the GT transceiver on the 62.5MHz clock
// source
wire [1:0] rxchariscomma_int;
wire [1:0] rxcharisk_int;
wire [15:0] rxdata_int;
wire [1:0] rxdisperr_int;
wire [1:0] rxnotintable_int;
wire [1:0] rxrundisp_int;
// Double width signals reclocked on the GT's 62.5MHz clock source
reg [1:0] rxchariscomma_reg;
reg [1:0] rxcharisk_reg;
reg [15:0] rxdata_reg;
reg [1:0] rxdisperr_reg;
reg [1:0] rxnotintable_reg;
reg [1:0] rxrundisp_reg;
reg rxpowerdown_reg = 1'b0;
// Double width signals reclocked onto the 125MHz clock source
reg [1:0] rxchariscomma_double;
reg [1:0] rxcharisk_double;
reg [15:0] rxdata_double;
reg [1:0] rxdisperr_double;
reg [1:0] rxnotintable_double;
reg [1:0] rxrundisp_double;
reg rxpowerdown_double = 1'b0;
reg rxpowerdown = 1'b0;
wire [1:0] rxpowerdown_int;
assign txpowerdown_int = {2{txpowerdown}};
assign rxpowerdown_int = {2{rxpowerdown}};
//---------------------------------------------------------------------------
// The core works from a 125MHz clock source, the GT transceiver fabric
// interface works from a 62.5MHz clock source. The following signals
// sourced by the core therefore need to be reclocked onto the 62.5MHz
// clock
//---------------------------------------------------------------------------
// Reclock encommaalign
gige_sfp_mdio_reset_sync reclock_encommaalign
(
.clk (usrclk),
.reset_in (encommaalign),
.reset_out (encommaalign_int)
);
// Reclock txreset
gige_sfp_mdio_reset_sync reclock_txreset
(
.clk (usrclk),
.reset_in (txreset),
.reset_out (txreset_int)
);
// Reclock rxreset
gige_sfp_mdio_reset_sync reclock_rxreset
(
.clk (usrclk),
.reset_in (rxreset),
.reset_out (rxreset_int)
);
//---------------------------------------------------------------------------
// toggle signal used to control sampling during bus width conversions
//---------------------------------------------------------------------------
always @(posedge usrclk2)
begin
if (txreset) begin
toggle <= 1'b0;
end
else begin
toggle <= !toggle;
end
end
//---------------------------------------------------------------------------
// The core works from a 125MHz clock source, the GT transceiver fabric
// interface works from a 62.5MHz clock source. The following signals
// sourced by the core therefore need to be converted to double width, then
// resampled on the GT's 62.5MHz clock
//---------------------------------------------------------------------------
// Reclock the transmitter signals
always @(posedge usrclk2)
begin
if (txreset) begin
txdata_reg <= 8'b0;
txchardispmode_reg <= 1'b0;
txchardispval_reg <= 1'b0;
txcharisk_reg <= 1'b0;
txpowerdown_reg <= 1'b0;
end
else begin
txdata_reg <= txdata;
txchardispmode_reg <= txchardispmode;
txchardispval_reg <= txchardispval;
txcharisk_reg <= txcharisk;
txpowerdown_reg <= powerdown;
end
end
// Double the data width
always @(posedge usrclk2)
begin
if (txreset) begin
txdata_double <= 16'b0;
txchardispmode_double <= 2'b0;
txchardispval_double <= 2'b0;
txcharisk_double <= 2'b0;
txpowerdown_double <= 1'b0;
end
else begin
if (!toggle) begin
txdata_double[7:0] <= txdata_reg;
txchardispmode_double[0] <= txchardispmode_reg;
txchardispval_double[0] <= txchardispval_reg;
txcharisk_double[0] <= txcharisk_reg;
txdata_double[15:8] <= txdata;
txchardispmode_double[1] <= txchardispmode;
txchardispval_double[1] <= txchardispval;
txcharisk_double[1] <= txcharisk;
end
txpowerdown_double <= txpowerdown_reg;
end
end
// Cross the clock domain
always @(posedge usrclk)
begin
txdata_int <= txdata_double;
txchardispmode_int <= txchardispmode_double;
txchardispval_int <= txchardispval_double;
txcharisk_int <= txcharisk_double;
txbufstatus_reg <= txbufstatus;
txpowerdown <= txpowerdown_double;
end
//---------------------------------------------------------------------------
// The core works from a 125MHz clock source, the GT transceiver fabric
// interface works from a 62.5MHz clock source. The following signals
// sourced by the GT transceiver therefore need to converted to half width
//---------------------------------------------------------------------------
// Sample the double width received data from the GT transsciever on the GT's
// 62.5MHz clock
always @(posedge usrclk)
begin
rxchariscomma_reg <= rxchariscomma_int;
rxcharisk_reg <= rxcharisk_int;
rxdata_reg <= rxdata_int;
rxdisperr_reg <= rxdisperr_int;
rxnotintable_reg <= rxnotintable_int;
rxrundisp_reg <= rxrundisp_int;
rxbufstatus_reg <= rxbufstatus;
rxpowerdown <= rxpowerdown_reg;
end
// Reclock the double width received data from the GT transsciever onto the
// 125MHz clock source. Both clock domains are frequency related and are
// derived from the same MMCM: the Xilinx tools will accont for this.
always @(posedge usrclk2)
begin
if (rxreset) begin
rxchariscomma_double <= 2'b0;
rxcharisk_double <= 2'b0;
rxdata_double <= 16'b0;
rxdisperr_double <= 2'b0;
rxnotintable_double <= 2'b0;
rxrundisp_double <= 2'b0;
rxpowerdown_double <= 1'b0;
end
else if (toggle) begin
rxchariscomma_double <= rxchariscomma_reg;
rxcharisk_double <= rxcharisk_reg;
rxdata_double <= rxdata_reg;
rxdisperr_double <= rxdisperr_reg;
rxnotintable_double <= rxnotintable_reg;
rxrundisp_double <= rxrundisp_reg;
end
rxpowerdown_double <= powerdown;
end
// Halve the bus width
always @(posedge usrclk2)
begin
if (rxreset) begin
rxchariscomma <= 1'b0;
rxcharisk <= 1'b0;
rxdata <= 8'b0;
rxdisperr <= 1'b0;
rxnotintable <= 1'b0;
rxrundisp <= 1'b0;
rxpowerdown_reg <= 1'b0;
end
else begin
if (!toggle) begin
rxchariscomma <= rxchariscomma_double[0];
rxcharisk <= rxcharisk_double[0];
rxdata <= rxdata_double[7:0];
rxdisperr <= rxdisperr_double[0];
rxnotintable <= rxnotintable_double[0];
rxrundisp <= rxrundisp_double[0];
end
else begin
rxchariscomma <= rxchariscomma_double[1];
rxcharisk <= rxcharisk_double[1];
rxdata <= rxdata_double[15:8];
rxdisperr <= rxdisperr_double[1];
rxnotintable <= rxnotintable_double[1];
rxrundisp <= rxrundisp_double[1];
end
rxpowerdown_reg <= rxpowerdown_double;
end
end
//---------------------------------------------------------------------------
// Instantiate the Series-7 GTX
//---------------------------------------------------------------------------
// Direct from the Transceiver Wizard output
gige_sfp_mdio_GTWIZARD_init #
(
.EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE")
)
gtwizard_inst
(
.SYSCLK_IN (independent_clock),
.SOFT_RESET_IN (pmareset),
.GT0_TX_FSM_RESET_DONE_OUT (),
.GT0_RX_FSM_RESET_DONE_OUT (),
.GT0_DATA_VALID_IN (data_valid_reg2),
//----------------------- Channel - Ref Clock Ports //------------------
.GT0_GTREFCLK0_IN (gtrefclk),
//------------------------------ Channel PLL //-------------------------
.GT0_CPLLFBCLKLOST_OUT (),
.GT0_CPLLLOCK_OUT (cplllock),
.GT0_CPLLLOCKDETCLK_IN (independent_clock),
.GT0_CPLLRESET_IN (pmareset),
//----------------------------- Eye Scan Ports //-----------------------
.GT0_EYESCANDATAERROR_OUT (),
//---------------------- Loopback and Powerdown Ports //----------------
.GT0_LOOPBACK_IN (3'b0),
.GT0_RXPD_IN (rxpowerdown_int),
.GT0_TXPD_IN (txpowerdown_int),
//----------------------------- Receive Ports --------------------------
.GT0_RXUSERRDY_IN (mmcm_locked),
//--------------------- Receive Ports - 8b10b Decoder //----------------
.GT0_RXCHARISCOMMA_OUT (rxchariscomma_int),
.GT0_RXCHARISK_OUT (rxcharisk_int),
.GT0_RXDISPERR_OUT (rxdisperr_int),
.GT0_RXNOTINTABLE_OUT (rxnotintable_int),
//----------------- Receive Ports - Clock Correction Ports //-----------
.GT0_RXCLKCORCNT_OUT (rxclkcorcnt_int),
//------------- Receive Ports - Comma Detection and Alignment //--------
.GT0_RXMCOMMAALIGNEN_IN (encommaalign_int),
.GT0_RXPCOMMAALIGNEN_IN (encommaalign_int),
//----------------- Receive Ports - RX Data Path interface //-----------
.GT0_GTRXRESET_IN (gt_reset_rx),
// .GT0_GTRXRESET_IN (rxreset_int),
.GT0_RXDATA_OUT (rxdata_int),
.GT0_RXOUTCLK_OUT (),
.GT0_RXUSRCLK_IN (usrclk),
.GT0_RXUSRCLK2_IN (usrclk),
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
.GT0_RXDFELPMRESET_IN (1'b0),
.GT0_RXMONITOROUT_OUT (),
.GT0_RXMONITORSEL_IN (2'b0),
//----- Receive Ports - RX Driver),OOB signalling),Coupling and Eq.),CDR //
.GT0_GTXRXN_IN (rxn),
.GT0_GTXRXP_IN (rxp),
.GT0_RXCDRLOCK_OUT (),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports //-
.GT0_RXBUFRESET_IN (rxreset_int),
.GT0_RXBUFSTATUS_OUT (rxbufstatus),
//---------------------- Receive Ports - RX PLL Ports //----------------
.GT0_RXRESETDONE_OUT (resetdone_rx),
//----------------------------- Transmit Ports -------------------------
.GT0_TXUSERRDY_IN (mmcm_locked),
//-------------- Transmit Ports - 8b10b Encoder Control Ports //--------
.GT0_TXCHARDISPMODE_IN (txchardispmode_int),
.GT0_TXCHARDISPVAL_IN (txchardispval_int),
.GT0_TXCHARISK_IN (txcharisk_int),
//---------------- Transmit Ports - TX Data Path interface //-----------
.GT0_GTTXRESET_IN (gt_reset_tx),
// .GT0_GTTXRESET_IN (txreset_int),
.GT0_TXDATA_IN (txdata_int),
.GT0_TXOUTCLK_OUT (txoutclk),
.GT0_TXOUTCLKFABRIC_OUT (),
.GT0_TXOUTCLKPCS_OUT (),
//.GT0_TXPCSRESET_IN (pcsreset),
.GT0_TXUSRCLK_IN (usrclk),
.GT0_TXUSRCLK2_IN (usrclk),
//-------------- Transmit Ports - TX Driver and OOB signaling //--------
.GT0_GTXTXN_OUT (txn),
.GT0_GTXTXP_OUT (txp),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment //---
.GT0_TXBUFSTATUS_OUT (txbufstatus),
//--------------------- Transmit Ports - TX PLL Ports //----------------
.GT0_TXRESETDONE_OUT (resetdone_tx),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.GT0_TXELECIDLE_IN (txpowerdown),
//____________________________COMMON PORTS________________________________
//-------------------- Common Block - Ref Clock Ports ---------------------
.GT0_GTREFCLK0_COMMON_IN (gtrefclk),
//----------------------- Common Block - QPLL Ports ------------------------
.GT0_QPLLLOCK_OUT () ,
.GT0_QPLLLOCKDETCLK_IN (independent_clock),
.GT0_QPLLRESET_IN (1'b0)
);
// Hold the transmitter and receiver paths of the GT transceiver in reset
// until the PLL has locked.
assign gt_reset_rx = (rxreset_int & resetdone_rx);
assign gt_reset_tx = (txreset_int & resetdone_tx);
// Output the PLL locked status
assign plllkdet = cplllock;
// Report overall status for both transmitter and receiver reset done signals
assign resetdone = cplllock ;
// reset to PCS part of GT
assign pcsreset = !mmcm_locked;
// temporary
assign rxrundisp_int = 2'b0;
// Decode the GT transceiver buffer status signals
always @(posedge usrclk2)
begin
rxbuferr <= rxbufstatus_reg[2];
txbuferr <= txbufstatus_reg[1];
rxclkcorcnt <= {1'b0, rxclkcorcnt_int};
end
//---------------------------------------------------------------------------
// The core works from a 125MHz clock source userclk2, the init statemachines
// work at 200 MHz.
//---------------------------------------------------------------------------
// Cross the clock domain
always @(posedge usrclk2)
begin
data_valid_reg <= data_valid;
end
gige_sfp_mdio_sync_block sync_block_data_valid
(
.clk (independent_clock),
.data_in (data_valid_reg),
.data_out (data_valid_reg2)
);
endmodule
top/x300/coregen/gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v
Executable
+509
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@@ -0,0 +1,509 @@
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : gige_sfp_mdio_tx_startup_fsm.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Description : This module performs TX reset and initialization.
//
//
//
// Module gige_sfp_mdio_TX_STARTUP_FSM
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*****************************************************************************
`timescale 1ns / 1ps
`define DLY #1
module gige_sfp_mdio_TX_STARTUP_FSM #
(
parameter GT_TYPE = "GTX",
parameter STABLE_CLOCK_PERIOD = 8, // Period of the stable clock driving this state-machine, unit is [ns]
parameter RETRY_COUNTER_BITWIDTH = 8,
parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must
parameter RX_QPLL_USED = "FALSE", // share these two generic values
parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
(
input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB
input wire TXUSERCLK, //TXUSERCLK as used in the design
input wire SOFT_RESET, //User Reset, can be pulled any time
input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost
input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost
input wire QPLLLOCK, //Lock Detect from the QPLL of the GT
input wire CPLLLOCK , //Lock Detect from the CPLL of the GT
input wire TXRESETDONE,
input wire MMCM_LOCK,
output reg GTTXRESET = 1'b0,
output reg MMCM_RESET = 1'b1,
output reg QPLL_RESET = 1'b0, //Reset QPLL
output reg CPLL_RESET = 1'b0, //Reset CPLL
output TX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished.
output reg TXUSERRDY = 1'b0,
output RUN_PHALIGNMENT,
output reg RESET_PHALIGNMENT = 1'b0,
input wire PHALIGNMENT_DONE,
output [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of
// Retries it took to get the transceiver up and running
);
//Interdependencies:
// * Timing depends on the frequency of the stable clock. Hence counters-sizes
// are calculated at design-time based on the Generics
//
// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
// => signal which PLL has been reset
// *
localparam [2:0]
INIT = 3'b000,
ASSERT_ALL_RESETS = 3'b001,
RELEASE_PLL_RESET = 3'b010,
RELEASE_MMCM_RESET = 3'b011,
WAIT_RESET_DONE = 3'b100,
DO_PHASE_ALIGNMENT = 3'b101,
RESET_FSM_DONE = 3'b110;
reg [2:0] tx_state = INIT;
parameter MMCM_LOCK_CNT_MAX = 1024;
parameter STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration
parameter WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration
parameter WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin
parameter WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD;// 2 ms time-out
parameter WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD;//100 us time-out
parameter WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD;//100 us time-out
reg [7:0] init_wait_count = 0;
reg init_wait_done = 1'b0;
reg pll_reset_asserted = 1'b0;
reg tx_fsm_reset_done_int = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg tx_fsm_reset_done_int_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg tx_fsm_reset_done_int_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg tx_fsm_reset_done_int_s3 = 1'b0;
parameter MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1;
reg [7:0] retry_counter_int = 0;
reg [18:0] time_out_counter = 0;
reg reset_time_out = 1'b0;
reg time_out_2ms = 1'b0; //--\Flags that the various time-out points
reg time_tlock_max = 1'b0; //--|have been reached.
reg time_out_500us = 1'b0; //--/
reg [9:0] mmcm_lock_count = 0;
reg mmcm_lock_int = 1'b0;
reg [3:0] mmcm_lock_reclocked = 3'b0;
reg run_phase_alignment_int = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg run_phase_alignment_int_s3 = 1'b0;
parameter MAX_WAIT_BYPASS = 110000; //110000 TXUSRCLK cycles is the max time needed for Multilane designs
reg [16:0] wait_bypass_count = 0;
reg time_out_wait_bypass = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg time_out_wait_bypass_s3 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg txresetdone_s1 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg txresetdone_s2 = 1'b0;
(* ASYNC_REG = "TRUE" *)
reg txresetdone_s3 = 1'b0;
wire refclk_lost;
//Alias section, signals used within this module mapped to output ports:
assign RETRY_COUNTER = retry_counter_int;
assign RUN_PHALIGNMENT = run_phase_alignment_int;
assign TX_FSM_RESET_DONE = tx_fsm_reset_done_int;
always @(posedge STABLE_CLOCK)
begin
// The counter starts running when configuration has finished and
// the clock is stable. When its maximum count-value has been reached,
// the 500 ns from Answer Record 43482 have been passed.
if (init_wait_count == WAIT_MAX)
init_wait_done <= `DLY 1'b1;
else
init_wait_count <= `DLY init_wait_count + 1;
end
always @(posedge STABLE_CLOCK)
begin
// One common large counter for generating three time-out signals.
// Intermediate time-outs are derived from calculated values, based
// on the period of the provided clock.
if (reset_time_out == 1'b1)
begin
time_out_counter <= `DLY 0;
time_out_2ms <= `DLY 1'b0;
time_tlock_max <= `DLY 1'b0;
time_out_500us <= `DLY 1'b0;
end
else
begin
if (time_out_counter == WAIT_TIMEOUT_2ms)
time_out_2ms <= `DLY 1'b1;
else
time_out_counter <= `DLY time_out_counter + 1;
if (time_out_counter == WAIT_TLOCK_MAX)
time_tlock_max <= `DLY 1'b1;
if (time_out_counter == WAIT_TIMEOUT_500us)
time_out_500us <= `DLY 1'b1;
end
end
always @(posedge TXUSERCLK)
begin
if (MMCM_LOCK == 1'b0)
begin
mmcm_lock_count <= `DLY 0;
mmcm_lock_int <= `DLY 1'b0;
end
else
begin
if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1)
mmcm_lock_count <= `DLY mmcm_lock_count + 1;
else
mmcm_lock_int <= `DLY 1'b1;
end
end
always @(posedge STABLE_CLOCK)
//Reclocking onto the FSM-clock.
begin
if (MMCM_LOCK == 1'b0)
//The reset-signal is here on purpose. This avoids
//getting the shift-register targetted to an SRL.
//The reason for this is that an SRL will not help
//on the cross-clock domain but "real" Flip-flops will.
mmcm_lock_reclocked <= `DLY 4'b0000;
else
begin
mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int;
mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1];
end
end
//Clock Domain Crossing
always @(posedge TXUSERCLK)
begin
run_phase_alignment_int_s1 <= `DLY run_phase_alignment_int;
run_phase_alignment_int_s2 <= `DLY run_phase_alignment_int_s1;
run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2;
tx_fsm_reset_done_int_s1 <= `DLY tx_fsm_reset_done_int;
tx_fsm_reset_done_int_s2 <= `DLY tx_fsm_reset_done_int_s1;
tx_fsm_reset_done_int_s3 <= `DLY tx_fsm_reset_done_int_s2;
end
always @(posedge STABLE_CLOCK)
begin
time_out_wait_bypass_s1 <= `DLY time_out_wait_bypass;
time_out_wait_bypass_s2 <= `DLY time_out_wait_bypass_s1;
time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2;
txresetdone_s1 <= `DLY TXRESETDONE;
txresetdone_s2 <= `DLY txresetdone_s1;
txresetdone_s3 <= `DLY txresetdone_s2;
end
always @(posedge TXUSERCLK)
begin
if (run_phase_alignment_int_s3 == 1'b0)
begin
wait_bypass_count <= `DLY 0;
time_out_wait_bypass <= `DLY 1'b0;
end
else if (run_phase_alignment_int_s3 == 1'b1 && tx_fsm_reset_done_int_s3 == 1'b0)
begin
if (wait_bypass_count == MAX_WAIT_BYPASS - 1)
time_out_wait_bypass <= `DLY 1'b1;
else
wait_bypass_count <= `DLY wait_bypass_count + 1;
end
end
assign refclk_lost = ( TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 :
( TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0;
//FSM for resetting the GTX/GTH/GTP in the 7-series.
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
// Following steps are performed:
// 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
// answer-record 43482
// 2) Assert all resets on the GT and on an MMCM potentially connected.
// After that wait until a reference-clock has been detected.
// 3) Release the reset to the GT and wait until the GT-PLL has locked.
// 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
// Also signal to the RX-side which PLL has been reset.
// 5) Wait for the RESET_DONE-signal from the GTX.
// 6) Signal to start the phase-alignment procedure and wait for it to
// finish.
// 7) Reset-sequence has successfully run through. Signal this to the
// rest of the design by asserting TX_FSM_RESET_DONE.
always @(posedge STABLE_CLOCK)
begin
if (SOFT_RESET == 1'b1 || (tx_state != INIT && tx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1))
begin
tx_state <= `DLY INIT;
TXUSERRDY <= `DLY 1'b0;
GTTXRESET <= `DLY 1'b0;
MMCM_RESET <= `DLY 1'b1;
tx_fsm_reset_done_int <= `DLY 1'b0;
QPLL_RESET <= `DLY 1'b0;
CPLL_RESET <= `DLY 1'b0;
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
retry_counter_int <= `DLY 0;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
end
else
begin
case (tx_state)
INIT :
begin
//Initial state after configuration. This state will be left after
//approx. 500 ns and not be re-entered.
if (init_wait_done == 1'b1)
tx_state <= `DLY ASSERT_ALL_RESETS;
reset_time_out <= `DLY 1'b1;
end
ASSERT_ALL_RESETS :
begin
//This is the state into which the FSM will always jump back if any
//time-outs will occur.
//The number of retries is reported on the output RETRY_COUNTER. In
//case the transceiver never comes up for some reason, this machine
//will still continue its best and rerun until the FPGA is turned off
//or the transceivers come up correctly.
if (TX_QPLL_USED == "TRUE")
begin
if (pll_reset_asserted == 1'b0)
begin
QPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
QPLL_RESET <= `DLY 1'b0;
end
else
begin
if (pll_reset_asserted == 1'b0)
begin
CPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
CPLL_RESET <= `DLY 1'b0;
end
TXUSERRDY <= `DLY 1'b0;
GTTXRESET <= `DLY 1'b1;
MMCM_RESET <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
if ((TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) ||
(TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted))
tx_state <= `DLY RELEASE_PLL_RESET;
end
RELEASE_PLL_RESET :
begin
//PLL-Reset of the GTX gets released and the time-out counter
//starts running.
pll_reset_asserted <= `DLY 1'b1;
if ((TX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) ||
(TX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1))
begin
tx_state <= `DLY RELEASE_MMCM_RESET;
reset_time_out <= `DLY 1'b1;
end
if (time_out_2ms == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
RELEASE_MMCM_RESET :
begin
GTTXRESET <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
//Release of the MMCM-reset. Waiting for the MMCM to lock.
MMCM_RESET <= `DLY 1'b0;
if (mmcm_lock_reclocked[0] == 1'b1)
begin
tx_state <= `DLY WAIT_RESET_DONE;
reset_time_out <= `DLY 1'b1;
end
if (time_tlock_max == 1'b1 && mmcm_lock_reclocked[0] == 1'b0)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
WAIT_RESET_DONE :
begin
TXUSERRDY <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (txresetdone_s3 == 1'b1)
begin
tx_state <= `DLY DO_PHASE_ALIGNMENT;
reset_time_out <= `DLY 1'b1;
end
if (time_out_500us == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
DO_PHASE_ALIGNMENT :
begin
//The direct handling of the signals for the Phase Alignment is done outside
//this state-machine.
RESET_PHALIGNMENT <= `DLY 1'b0;
run_phase_alignment_int <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (PHALIGNMENT_DONE == 1'b1)
tx_state <= `DLY RESET_FSM_DONE;
if (time_out_wait_bypass_s3 == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
RESET_FSM_DONE :
begin
reset_time_out <= `DLY 1'b1;
tx_fsm_reset_done_int <= `DLY 1'b1;
end
endcase
end
end
endmodule
top/x300/coregen/gige_sfp_mdio/gig_eth_pcs_pma_readme.txt
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CHANGE LOG for Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v11.5
Release Date: December 18, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
This file contains the change log for all released versions of the Xilinx
LogiCORE IP core Ethernet 1000BASE-X PCS/PMA or SGMII.
For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm
For installation instructions for this release, please go to:
www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements, see:
www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
2. DEVICE SUPPORT
2.1. ISE
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
Virtex-6 devices
Virtex-6 CXT/LXT/SXT/HXT
Virtex-6 Lower Power (-1L) LXT/SXT
Defense Grade Virtex-6Q (XQ) LXT/SXT
Spartan-6 devices
Spartan-6 LX/LXT
Defense Grade Spartan-6Q LX/LXT
All Virtex-5 devices
Virtex-4 devices
Virtex-4 LX/SX/FX
Spartan-3 device families
Spartan-3
Spartan-3A and Spartan-3AN
Spartan-3A DSP
Spartan-3E
2.2. VIVADO
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
3. NEW FEATURE HISTORY
3.1 ISE
v11.5
- ISE 14.4 software support
- GT updates for Spartan-7,Series-7 and Virtex -6 Tranceivers.
v11.4
- ISE 14.2 software support
- Support for Zynq Devices
v11.3
- ISE 14.1 software support
- Support for Artix7 Devices
- Support for Virtex-7 HT Devices
v11.2
- ISE 13.4 software support
- Added programability through configuration vector
v11.1
- ISE 13.1 software support
- Updated status vector
- SGMII PHY mode
- Support for Kintex7 Devices
- Support for Virtex7 Devices
3.2 Vivado
v11.5
- Vivado 2012.4 software support
- GT updates for Series-7 transceivers.
v11.4
- Vivado 2012.2 software support
- Initial public release
- Block level user editable logic delivered as part of the core
4. RESOLVED ISSUES
4.1 ISE
The following issues are resolved in the indicated IP versions:
v11.5
- None
v11.4
- None
v11.3
- AR: 45676
- AR: 46123
v11.2
- AR: 42672
- AR: 36961
- AR: 42842
- AR: 43421
- AR: 43482
v11.1
- AR: 36957
- AR: 36961
- AR: 35681
4.2 Vivado
v11.5
- None
v11.4
- None
5. KNOWN ISSUES & LIMITATIONS
- For a comprehensive listing of Known Issues for this core, please see the IP
Release Notes Guide,
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Feedback on this IP core may also be submitted under the "Leave Feedback"
menu item in Vivado/PlanAhead.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/18/2012 Xilinx, Inc. 11.5 ISE 14.4 and Vivado 2012.4.
GT updates and CR closures.
07/25/2012 Xilinx, Inc. 11.4 ISE 14.2 and Vivado 2012.2.
Support for Zynq Devices. Sync LVDS Solution
04/24/2012 Xilinx, Inc. 11.3 ISE 14.1, Artix-7 and Vivado 2012.1 support
01/18/2012 Xilinx, Inc. 11.2 ISE 13.4 Support
09/06/2011 Xilinx, Inc. 11.1 Rev 1 Patch release for ISE 13.1
03/01/2011 Xilinx, Inc. 11.1 ISE 13.1 and Virtex-7 / Kintex-7 support
07/30/2010 Xilinx, Inc. 10.5 Rev 1 Patch release for ISE 12.2
07/23/2010 Xilinx, Inc. 10.5 ISE 12.2 support and Virtex-6 LVDS I/O
04/19/2010 Xilinx, Inc. 10.4 Release for ISE 12.1
03/09/2010 Xilinx, Inc. 10.3 Rev 1 Patch release for ISE 11.5
09/16/2009 Xilinx, Inc. 10.3 11.3, Virtex-6 HXT and Lower Power support
06/24/2009 Xilinx, Inc. 10.2 Release for ISE 11.2 and Spartan-6 support
04/27/2009 Xilinx, Inc. 10.1 Release for ISE 11.1
03/24/2008 Xilinx, Inc. 9.1 Release for ISE 10.1
08/15/2007 Xilinx, Inc. 9.0 Release for 9.2i
04/02/2007 Xilinx, Inc. 8.1 Rev 1 Spartan-3A DSP support
03/05/2007 Xilinx, Inc. 8.1 Release for ISE 9.1i
10/26/2006 Xilinx, Inc. 8.0 Release for Virtex-5 and Spartan-3A
07/19/2006 Xilinx, Inc. 7.1 Release for ISE 8.2i
05/22/2006 Xilinx, Inc. 7.0 Rev 1 Virtex-4 FX CES4 update
01/18/2006 Xilinx, Inc. 7.0 Release for ISE 8.1i
06/24/2005 Xilinx, Inc. 6.0 patch1 Patch release
05/12/2005 Xilinx, Inc. 6.0 Release for ISE 7.1i
09/30/2004 Xilinx, Inc. 5.0 Release for ISE 6.3i
================================================================================
8. LEGAL DISCLAIMER
(c) Copyright 2004 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
top/x300/coregen/gige_sfp_mdio/implement/example_design_xst.xcf
Executable
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# RLOCs for reset_sync / sync_block logic
#------------------------------------------------------
# To keep the FF pairs in the same slice to minimise routing delay between them
BEGIN MODEL sync_block
INST "data_sync" rloc = X0Y0;
INST "data_sync_reg" rloc = X0Y0;
END;
BEGIN MODEL reset_sync
INST "reset_sync1" rloc = X0Y0;
INST "reset_sync2" rloc = X0Y0;
END;
top/x300/coregen/gige_sfp_mdio/implement/implement.bat
Executable
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REM Clean up the results directory
rmdir /S /Q results
mkdir results
REM Synthesize the Example Design
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing the example design with XST';
xst -ifn xst.scr
copy gige_sfp_mdio_example_design.ngc .\results\
REM Copy the netlist generated by Coregen
echo 'Copy files from the netlist directory to the results directory'
copy ..\..\gige_sfp_mdio.ngc results
REM Copy the constraints files generated by Coregen
echo 'Copy files from constraints directory to results directory'
copy ..\example_design\gige_sfp_mdio_example_design.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild gige_sfp_mdio_example_design
echo 'Running map'
map -ol high -timing gige_sfp_mdio_example_design -o mapped.ncd
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_mdio_example_design -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/gige_sfp_mdio/implement/implement.sh
Executable
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#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
# Synthesize the Example Design
echo 'Synthesizing the example design with XST';
xst -ifn xst.scr
cp gige_sfp_mdio_example_design.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../gige_sfp_mdio.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/gige_sfp_mdio_example_design.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild gige_sfp_mdio_example_design
echo 'Running map'
map -ol high -timing gige_sfp_mdio_example_design -o mapped.ncd
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_mdio_example_design -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/gige_sfp_mdio/implement/xst.prj
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verilog work ../example_design/gige_sfp_mdio_sync_block.v
verilog work ../example_design/gige_sfp_mdio_reset_sync.v
verilog work ../example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v
verilog work ../example_design/transceiver/gige_sfp_mdio_gtwizard.v
verilog work ../example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v
verilog work ../example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v
verilog work ../example_design/transceiver/gige_sfp_mdio_recclk_monitor.v
verilog work ../example_design/transceiver/gige_sfp_mdio_gtwizard_init.v
verilog work ../example_design/transceiver/gige_sfp_mdio_transceiver.v
verilog work ../example_design/gige_sfp_mdio_tx_elastic_buffer.v
verilog work ../example_design/gige_sfp_mdio_mod.v
verilog work ../example_design/gige_sfp_mdio_block.v
verilog work ../example_design/gige_sfp_mdio_example_design.v
top/x300/coregen/gige_sfp_mdio/implement/xst.scr
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# XST synthesis script for GPCS_PMA core.
set -tmpdir .
set -xsthdpdir ./xst
run
-ifmt mixed
-top gige_sfp_mdio_example_design
-ofn gige_sfp_mdio_example_design
-p kintex7
-uc example_design_xst.xcf
-ifn xst.prj
-iobuf YES
top/x300/coregen/gige_sfp_mdio/simulation/demo_tb.v
Executable
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//------------------------------------------------------------------------------
// File : demo_tb.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Description: This testbench will exercise the ports of the Ethernet
// 1000BASE-X PCS/PMA core's example design to perform the following
// operations:
//
//----------------
// Configuration
//----------------
// The core will be reset, then Auto-Negotiation (if present) will
// be disabled and and the core will be taken out of the Isolate
// state.
//
//----------------
// Transmitter
//----------------
// Four frames are generated by the Tx Stimulus and pushed into the
// GMII transmitter.
//
// The PHY side transmitter interface data is captured, 8B10B decoded
// and the Tx Monitor checks that the captured data matches that
// injected.
//
//----------------
// Receiver
//----------------
// Four frames are generated by the Rx Stimulus, 8B10B encoded and
// pushed into the PHY side receiver interface.
//
// The GMII side receiver interface data is captured and the
// Rx Monitor checks that the captured data matches that injected.
//
//
//----------------------------------------------------------------------
// Demonstration Test Fixture |
// |
// |
// -------------------------- |
// | Example Design | |
// | (DUT) | |
// | | |
// | | |
// | | |
// Tx | | 8B10B decode, Tx |
// Generate -------> --------> Monitor |
// Frames | | Frames |
// |GMII PHY | |
// | I/F I/F | |
// | | |
// | | |
// | | |
// Rx | | 8B10B encode, Rx |
// Monitor <-------- <-------- Generate |
// Frames | | Frames |
// | | |
// ------------^------------- |
// | |
// | |
// Stimulate |
// MDIO I/F |
// (if present) |
// |
//----------------------------------------------------------------------
`timescale 1 ps/1 ps
// This module is the demonstration testbench
module demo_tb;
//----------------------------------------------------------------------------
// Stimulus - Management Frame data
//----------------------------------------------------------------------------
// Create management frame
reg [0:63] mdio_data;
initial
begin
mdio_data[0:31] = 32'hffffffff; // preamble field
mdio_data[32:33] = 2'h1; // start opcode
mdio_data[34:35] = 2'h1; // write opcode
mdio_data[36:40] = 5'h1; // phyad (write to this device)
mdio_data[41:45] = 5'h0; // regad (write to Configuration Register)
mdio_data[46:47] = 2'h2; // Turn-around cycles
// DATA FIELD
mdio_data[48] = 1'b0; // Do not assert Reset
mdio_data[49] = 1'b0; // No loopback
mdio_data[50] = 1'b0; // Speed selection
mdio_data[51] = 1'b0; // Disable Auto-Negotiation
mdio_data[52] = 1'b0; // Disable Power Down
mdio_data[53] = 1'b0; // Disable Isolate GMII
mdio_data[54] = 1'b0; // Disable Auto-Negotiation Restart
mdio_data[55] = 1'b1; // Full Duplex Mode
mdio_data[56] = 1'b0; // Disable Collision Test
mdio_data[57] = 1'b0; // Speed selection
mdio_data[58:63] = 6'h0; // Reserved
end
//----------------------------------------------------------------------------
// testbench signals
//----------------------------------------------------------------------------
// testbench control semaphores
reg configuration_finished;
wire tx_monitor_finished;
wire rx_monitor_finished;
wire simulation_finished;
//----------------------------------------------------------------------------
// DUT signals
//----------------------------------------------------------------------------
// An independent clock source used as the reference clock for an
// IDELAYCTRL (if present) and for the main GT transceiver reset logic.
// This example design assumes that this is of frequency 200MHz.
reg independent_clock;
// System Reset
reg reset;
// Transceiver Interface
//----------------------
reg gtrefclk_p;
reg gtrefclk_n;
wire txp;
wire txn;
wire rxp;
wire rxn;
// GMII Interface
//---------------
wire gmii_tx_clk;
wire gmii_rx_clk;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_rxd;
wire gmii_rx_dv;
wire gmii_rx_er;
// Management: MDIO Interface
//---------------------------
reg mdc;
reg mdio_i;
wire mdio_o;
wire mdio_t;
wire [4:0] phyad;
reg [4:0] configuration_vector;
reg configuration_valid;
wire signal_detect;
wire [15:0] status_vector;
wire [8:0] link_timer_value;
//----------------------------------------------------------------------------
// Create clock sources
//----------------------------------------------------------------------------
// An independent clock source used as the reference clock for an
// IDELAYCTRL (if present) and for the main GT transceiver reset logic.
// This testbench uses the frequency of 200MHz.
initial
begin
independent_clock <= 1'b0;
forever
begin
independent_clock <= 1'b0;
#2500;
independent_clock <= 1'b1;
#2500;
end
end
// Create the transceiver Reference clock (125 MHz)
initial
begin
gtrefclk_p <= 1'b0;
gtrefclk_n <= 1'b1;
forever
begin
gtrefclk_p <= 1'b0;
gtrefclk_n <= 1'b1;
#4000;
gtrefclk_p <= 1'b1;
gtrefclk_n <= 1'b0;
#4000;
end
end
//----------------------------------------------------------------------------
// Wire up Device Under Test
//----------------------------------------------------------------------------
gige_sfp_mdio_example_design dut
(
.independent_clock (independent_clock),
.gtrefclk_p (gtrefclk_p),
.gtrefclk_n (gtrefclk_n),
.txp (txp),
.txn (txn),
.rxp (rxp),
.rxn (rxn),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rx_clk (gmii_rx_clk),
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.mdc (mdc),
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
.phyad (phyad),
.configuration_vector (configuration_vector),
.configuration_valid (configuration_valid),
.status_vector (status_vector),
.reset (reset),
.signal_detect (signal_detect)
);
//----------------------------------------------------------------------------
// Instantiate a Stimulus module for the core
//----------------------------------------------------------------------------
stimulus_tb stimulus
(
.txp (txp),
.txn (txn),
.rxp (rxp),
.rxn (rxn),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rx_clk (gmii_rx_clk),
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.configuration_finished (configuration_finished),
.tx_monitor_finished (tx_monitor_finished),
.rx_monitor_finished (rx_monitor_finished)
);
//----------------------------------------------------------------------------
// Simulate that PMD sublayer has detected and optical input.
//----------------------------------------------------------------------------
assign signal_detect = 1'b1;
//----------------------------------------------------------------------------
// Set the PHYAD for the core
//----------------------------------------------------------------------------
assign phyad = 5'h1;
//----------------------------------------------------------------------------
// Configuration process. This process will reset the core, then write
// to configuration register 0 to turn off autonegotiation and take
// the core out of the isolate state.
//----------------------------------------------------------------------------
// drives MDC at 2.5 MHz
initial
begin
mdc <= 1'b0;
forever
begin
mdc <= 1'b0;
#200000;
mdc <= 1'b1;
#200000;
end
end
// Main configuration process
initial
begin : p_configuration
integer MDIO_BIT; // Bit counter within MDIO frame
$display("** Note: Timing checks are not valid");
configuration_finished <= 0;
configuration_vector <= 5'b00000;
configuration_valid <= 1'b0;
mdio_i <= 1'b1;
// reset the core
$display("Resetting core...");
reset <= 1'b1;
#1000000
@(posedge gtrefclk_p)
reset <= 1'b0;
// wait for core to obtain synchronisation
#50000000
// Write to PCS Management configuration register 0.
$display("Writing to Control Register in PCS sublayer....");
@(negedge mdc) // centre MDIO around MDC rising edge
MDIO_BIT = 0;
// transmit serial management frame
while(MDIO_BIT !== 64)
begin
@(negedge mdc);
mdio_i <= mdio_data[MDIO_BIT];
MDIO_BIT = MDIO_BIT + 1;
end
@(negedge mdc)
mdio_i <= 1'b1; // simulate tri-state with pullup
// wait for core to obtain synchronisation
wait (status_vector[1] == 1);
#20000000
configuration_finished <= 1;
end // p_configuration
//----------------------------------------------------------------------------
// End the simulation.
//----------------------------------------------------------------------------
assign simulation_finished = tx_monitor_finished & rx_monitor_finished;
initial
begin : p_end_simulation
fork: sim_in_progress
@(posedge simulation_finished) disable sim_in_progress;
#300000000 disable sim_in_progress;
join
if (simulation_finished) begin
#1000000
$display("Test completed successfully");
$display("Simulation Complete.");
end
else
$display("** Error: Testbench timed out");
$stop;
end // p_end_simulation
endmodule
top/x300/coregen/gige_sfp_mdio/simulation/functional/simulate_mti.do
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vlib work
vmap work work
echo "Compiling Core Simulation Models"
vlog -work work ../../../gige_sfp_mdio.v
echo "Compiling Example Design"
vlog -work work \
../../example_design/gige_sfp_mdio_sync_block.v \
../../example_design/gige_sfp_mdio_reset_sync.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard.v \
../../example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \
../../example_design/transceiver/gige_sfp_mdio_transceiver.v \
../../example_design/gige_sfp_mdio_tx_elastic_buffer.v \
../../example_design/gige_sfp_mdio_block.v \
../../example_design/gige_sfp_mdio_example_design.v
echo "Compiling Test Bench"
vlog -work work -novopt ../stimulus_tb.v ../demo_tb.v
echo "Starting simulation"
vsim -voptargs="+acc" -L unisims_ver -L secureip -t ps work.demo_tb work.glbl
do wave_mti.do
run -all
top/x300/coregen/gige_sfp_mdio/simulation/functional/simulate_ncsim.sh
Executable
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#!/bin/sh
mkdir work
echo "Compiling Core Simulation Models"
ncvlog -work work ../../../gige_sfp_mdio.v
echo "Compiling Example Design"
ncvlog -work work \
../../example_design/gige_sfp_mdio_sync_block.v \
../../example_design/gige_sfp_mdio_reset_sync.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard.v \
../../example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \
../../example_design/transceiver/gige_sfp_mdio_transceiver.v \
../../example_design/gige_sfp_mdio_tx_elastic_buffer.v \
../../example_design/gige_sfp_mdio_block.v \
../../example_design/gige_sfp_mdio_example_design.v
echo "Compiling Test Bench"
ncvlog -work work ../stimulus_tb.v ../demo_tb.v
echo "Elaborating design"
ncelab -access +rw work.demo_tb glbl
echo "Starting simulation"
ncsim -gui work.demo_tb -input @"simvision -input wave_ncsim.sv"
top/x300/coregen/gige_sfp_mdio/simulation/functional/simulate_vcs.sh
Executable
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#!/bin/sh
rm -rf simv* csrc DVEfiles AN.DB
echo "Compiling Core Simulation Models"
vlogan +v2k \
../../../gige_sfp_mdio.v \
../../example_design/gige_sfp_mdio_sync_block.v \
../../example_design/gige_sfp_mdio_reset_sync.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard.v \
../../example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
../../example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \
../../example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \
../../example_design/transceiver/gige_sfp_mdio_transceiver.v \
../../example_design/gige_sfp_mdio_tx_elastic_buffer.v \
../../example_design/gige_sfp_mdio_block.v \
../../example_design/gige_sfp_mdio_example_design.v \
../stimulus_tb.v \
../demo_tb.v
echo "Elaborating design"
vcs +vcs+lic+wait \
-debug \
demo_tb glbl
echo "Starting simulation"
./simv -ucli -i ucli_commands.key
dve -vpd vcdplus.vpd -session vcs_session.tcl
top/x300/coregen/gige_sfp_mdio/simulation/functional/ucli_commands.key
Executable
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call {$vcdpluson}
run
call {$vcdplusclose}
quit
top/x300/coregen/gige_sfp_mdio/simulation/functional/vcs_session.tcl
Executable
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gui_open_window Wave
gui_list_select -id Hier.1 { glbl demo_tb }
gui_sg_create PCS_PMA_group
gui_list_add_group -id Wave.1 {PCS_PMA_group}
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Test_semaphores }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Rx_Stimulus }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Tx_Monitor }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Transceiver_Rx_Signals }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Transceiver_Tx_Signals }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Rx_GMII_Signals }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Tx_GMII_Signals }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Management_Signals }
gui_list_add_divider -id Wave.1 -after PCS_PMA_group { System_Signals }
gui_list_add -id Wave.1 -after System_Signals {{demo_tb.gtrefclk_p} {demo_tb.gtrefclk_n}}
gui_list_add -id Wave.1 -after System_Signals {demo_tb.signal_detect}
gui_list_add -id Wave.1 -after Management_Signals {{demo_tb.status_vector}}
gui_list_add -id Wave.1 -after Management_Signals {{demo_tb.mdc} {demo_tb.mdio_i} {demo_tb.mdio_o} {demo_tb.mdio_t} {demo_tb.phyad}}
gui_list_add -id Wave.1 -after Tx_GMII_Signals {{demo_tb.gmii_txd} {demo_tb.gmii_tx_en} {demo_tb.gmii_tx_er}}
gui_list_add -id Wave.1 -after Rx_GMII_Signals {{demo_tb.gmii_rxd} {demo_tb.gmii_rx_dv} {demo_tb.gmii_rx_er}}
gui_list_add -id Wave.1 -after Transceiver_Tx_Signals {{demo_tb.txp} {demo_tb.txn}}
gui_list_add -id Wave.1 -after Transceiver_Rx_Signals {{demo_tb.rxp} {demo_tb.rxn}}
gui_list_add -id Wave.1 -after Tx_Monitor {{demo_tb.stimulus.mon_tx_clk} {demo_tb.stimulus.tx_pdata} {demo_tb.stimulus.tx_is_k}}
gui_list_add -id Wave.1 -after Tx_Monitor {{demo_tb.stimulus.bitclock}}
gui_list_add -id Wave.1 -after Rx_Stimulus {{demo_tb.stimulus.stim_rx_clk} {demo_tb.stimulus.rx_even} {demo_tb.stimulus.rx_pdata} {demo_tb.stimulus.rx_is_k} {demo_tb.stimulus.rx_rundisp_pos}}
gui_list_add -id Wave.1 -after Test_semaphores {{demo_tb.configuration_finished} {demo_tb.tx_monitor_finished} {demo_tb.rx_monitor_finished} {demo_tb.simulation_finished}}
gui_zoom -window Wave.1 -full
top/x300/coregen/gige_sfp_mdio/simulation/functional/wave_mti.do
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view structure
view signals
view wave
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {System Signals}
add wave -noupdate -format logic /demo_tb/reset
add wave -noupdate -format logic /demo_tb/gtrefclk_p
add wave -noupdate -format logic /demo_tb/gtrefclk_n
add wave -noupdate -format logic /demo_tb/signal_detect
add wave -noupdate -divider {Management I/F}
add wave -noupdate -format logic /demo_tb/mdc
add wave -noupdate -format logic /demo_tb/mdio_i
add wave -noupdate -format logic /demo_tb/mdio_o
add wave -noupdate -format logic /demo_tb/mdio_t
add wave -noupdate -format logic -binary /demo_tb/phyad
add wave -noupdate -format logic -binary /demo_tb/status_vector
add wave -noupdate -divider {Tx GMII}
add wave -noupdate -format logic -hex /demo_tb/gmii_txd
add wave -noupdate -format logic /demo_tb/gmii_tx_en
add wave -noupdate -format logic /demo_tb/gmii_tx_er
add wave -noupdate -divider {Rx GMII}
add wave -noupdate -format logic -hex /demo_tb/gmii_rxd
add wave -noupdate -format logic /demo_tb/gmii_rx_dv
add wave -noupdate -format logic /demo_tb/gmii_rx_er
add wave -noupdate -divider {Transceiver Tx}
add wave -noupdate -format logic /demo_tb/txp
add wave -noupdate -format logic /demo_tb/txn
add wave -noupdate -divider {Transceiver Rx}
add wave -noupdate -format logic /demo_tb/rxp
add wave -noupdate -format logic /demo_tb/rxn
add wave -noupdate -divider {Tx Monitor}
add wave -noupdate -format logic /demo_tb/stimulus/mon_tx_clk
add wave -noupdate -format logic -hex /demo_tb/stimulus/tx_pdata
add wave -noupdate -format logic /demo_tb/stimulus/tx_is_k
add wave -noupdate -format logic /demo_tb/stimulus/bitclock
add wave -noupdate -divider {Rx Stimulus}
add wave -noupdate -format logic /demo_tb/stimulus/stim_rx_clk
add wave -noupdate -format logic /demo_tb/stimulus/rx_even
add wave -noupdate -format logic -hex /demo_tb/stimulus/rx_pdata
add wave -noupdate -format logic /demo_tb/stimulus/rx_is_k
add wave -noupdate -format logic /demo_tb/stimulus/rx_rundisp_pos
add wave -noupdate -divider {Test semaphores}
add wave -noupdate -format logic /demo_tb/configuration_finished
add wave -noupdate -format logic /demo_tb/tx_monitor_finished
add wave -noupdate -format logic /demo_tb/rx_monitor_finished
add wave -noupdate -format logic /demo_tb/simulation_finished
TreeUpdate [SetDefaultTree]
top/x300/coregen/gige_sfp_mdio/simulation/functional/wave_ncsim.sv
Executable
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# SimVision Command Script
#
# groups
#
if {[catch {group new -name {System Signals} -overlay 0}] != ""} {
group using {System Signals}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.reset \
demo_tb.gtrefclk_p \
demo_tb.gtrefclk_n
demo_tb.signal_detect \
if {[catch {group new -name {Management I/F} -overlay 0}] != ""} {
group using {Management I/F}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.mdc \
demo_tb.mdio_i \
demo_tb.mdio_o \
demo_tb.mdio_t \
{demo_tb.phyad[4:0]} \
demo_tb.status_vector
if {[catch {group new -name {Tx GMII} -overlay 0}] != ""} {
group using {Tx GMII}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
{demo_tb.gmii_txd[7:0]} \
demo_tb.gmii_tx_en \
demo_tb.gmii_tx_er
if {[catch {group new -name {Rx GMII} -overlay 0}] != ""} {
group using {Rx GMII}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
{demo_tb.gmii_rxd[7:0]} \
demo_tb.gmii_rx_dv \
demo_tb.gmii_rx_er
if {[catch {group new -name {Transceiver Tx} -overlay 0}] != ""} {
group using {Transceiver Tx}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.txp \
demo_tb.txn
if {[catch {group new -name {Transceiver Rx} -overlay 0}] != ""} {
group using {Transceiver Rx}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.rxp \
demo_tb.rxn
if {[catch {group new -name {Tx Monitor} -overlay 0}] != ""} {
group using {Tx Monitor}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.stimulus.mon_tx_clk \
{demo_tb.stimulus.tx_pdata[7:0]} \
demo_tb.stimulus.tx_is_k \
demo_tb.stimulus.bitclock
if {[catch {group new -name {Rx Stimulus} -overlay 0}] != ""} {
group using {Rx Stimulus}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.stimulus.stim_rx_clk \
demo_tb.stimulus.rx_even \
{demo_tb.stimulus.rx_pdata[7:0]} \
demo_tb.stimulus.rx_is_k \
demo_tb.stimulus.rx_rundisp_pos
if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} {
group using {Test semaphores}
group set -overlay 0
group set -comment {}
group clear 0 end
}
group insert \
demo_tb.configuration_finished \
demo_tb.tx_monitor_finished \
demo_tb.rx_monitor_finished \
demo_tb.simulation_finished
#
# Waveform windows
#
if {[window find -match exact -name "Waveform 1"] == {}} {
window new WaveWindow -name "Waveform 1" -geometry 906x585+25+55
} else {
window geometry "Waveform 1" 906x585+25+55
}
window target "Waveform 1" on
waveform using {Waveform 1}
waveform sidebar visibility partial
waveform set \
-primarycursor TimeA \
-signalnames name \
-signalwidth 175 \
-units fs \
-valuewidth 75
cursor set -using TimeA -time 50,000,000,000fs
cursor set -using TimeA -marching 1
waveform baseline set -time 0
set groupId [waveform add -groups {{System Signals}}]
set groupId [waveform add -groups {{Management I/F}}]
set groupId [waveform add -groups {{Tx GMII}}]
set groupId [waveform add -groups {{Rx GMII}}]
set groupId [waveform add -groups {{Transceiver Tx}}]
set groupId [waveform add -groups {{Transceiver Rx}}]
set groupId [waveform add -groups {{Tx Monitor}}]
set groupId [waveform add -groups {{Rx Stimulus}}]
set groupId [waveform add -groups {{Test semaphores}}]
waveform xview limits 0fs 10us
simcontrol run -time 200us
top/x300/coregen/gige_sfp_mdio/simulation/stimulus_tb.v
Executable
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