Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
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/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2012 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: *
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* xilinx.com:ip:gig_eth_pcs_pma:11.4 *
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* *
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* The Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE(TM) provides the *
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* functionality to implement one of two different specifications: *
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* firstly the IEEE 802.3 1000BASE-X specification; secondly the *
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* Serial-GMII (SGMII) specification which is closely based on *
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* 1000BASE-X. The core provides a choice of physical interface *
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* options: a Ten-Bit-Interface (TBI) for connection to an external *
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* SERDES; high speed serial functionality using the device specific *
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* transceivers in Virtex-7, Kintex-7, Artix-7, Virtex-4, Virtex-5, *
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* Virtex-6 and Spartan-6; SGMII standard only - LVDS using SelectIO in *
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* Virtex-6 devices -2 speed grade and faster. All options provide up *
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* to 1 gigabit per second total bandwidth. When perfoming the SGMII *
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* standard, the core can carry Ethernet traffic up to 1 gigabit per *
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* second total bandwidth; this is inclusive of 10Mbps, 100Mbps and *
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* 1Gbps Ethernet speeds. The core is designed to interface to the *
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* LogiCORE Tri-Mode Ethernet MAC from Xilinx to provide a complete *
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* solution. *
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*******************************************************************************/
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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gige_sfp your_instance_name (
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.reset(reset), // input reset
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.signal_detect(signal_detect), // input signal_detect
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.mgt_rx_reset(mgt_rx_reset), // output mgt_rx_reset
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.mgt_tx_reset(mgt_tx_reset), // output mgt_tx_reset
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.userclk(userclk), // input userclk
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.userclk2(userclk2), // input userclk2
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.dcm_locked(dcm_locked), // input dcm_locked
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.rxbufstatus(rxbufstatus), // input [1 : 0] rxbufstatus
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.rxchariscomma(rxchariscomma), // input rxchariscomma
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.rxcharisk(rxcharisk), // input rxcharisk
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.rxclkcorcnt(rxclkcorcnt), // input [2 : 0] rxclkcorcnt
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.rxdata(rxdata), // input [7 : 0] rxdata
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.rxdisperr(rxdisperr), // input rxdisperr
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.rxnotintable(rxnotintable), // input rxnotintable
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.rxrundisp(rxrundisp), // input rxrundisp
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.txbuferr(txbuferr), // input txbuferr
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.powerdown(powerdown), // output powerdown
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.txchardispmode(txchardispmode), // output txchardispmode
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.txchardispval(txchardispval), // output txchardispval
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.txcharisk(txcharisk), // output txcharisk
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.txdata(txdata), // output [7 : 0] txdata
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.enablealign(enablealign), // output enablealign
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.gmii_txd(gmii_txd), // input [7 : 0] gmii_txd
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.gmii_tx_en(gmii_tx_en), // input gmii_tx_en
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.gmii_tx_er(gmii_tx_er), // input gmii_tx_er
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.gmii_rxd(gmii_rxd), // output [7 : 0] gmii_rxd
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.gmii_rx_dv(gmii_rx_dv), // output gmii_rx_dv
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.gmii_rx_er(gmii_rx_er), // output gmii_rx_er
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.gmii_isolate(gmii_isolate), // output gmii_isolate
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.configuration_vector(configuration_vector), // input [4 : 0] configuration_vector
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.status_vector(status_vector) // output [15 : 0] status_vector
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file gige_sfp.v when simulating
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// the core, gige_sfp. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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