Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,14 @@
+# RLOCs for reset_sync / sync_block logic
+#------------------------------------------------------
+# To keep the FF pairs in the same slice to minimise routing delay between them
+
+BEGIN MODEL sync_block
+  INST "data_sync" rloc = X0Y0;
+  INST "data_sync_reg"  rloc = X0Y0;
+END;
+
+BEGIN MODEL reset_sync
+  INST "reset_sync1"  rloc = X0Y0;
+  INST "reset_sync2"  rloc = X0Y0;
+END;
+
@@ -0,0 +1,37 @@
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Synthesize the Example Design
+rem Synthesize the VHDL Wrapper Files
+echo 'Synthesizing the example design with XST';
+xst -ifn xst.scr
+copy gige_sfp_example_design.ngc .\results\
+
+REM Copy the netlist generated by Coregen
+echo 'Copy files from the netlist directory to the results directory'
+copy ..\..\gige_sfp.ngc results
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copy files from constraints directory to results directory'
+copy ..\example_design\gige_sfp_example_design.ucf results\
+
+cd results
+echo 'Running ngdbuild'
+ngdbuild gige_sfp_example_design
+
+echo 'Running map'
+map -ol high -timing gige_sfp_example_design -o mapped.ncd
+
+echo 'Running par'
+par -ol high -w mapped.ncd routed.ncd mapped.pcf
+
+echo 'Running trce'
+trce -u -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed.ncd routed mapped.pcf  -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_example_design -w -sdf_anno false routed.ncd routed.v
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Synthesize the Example Design
+echo 'Synthesizing the example design with XST';
+xst -ifn xst.scr
+cp gige_sfp_example_design.ngc ./results/
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../gige_sfp.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/gige_sfp_example_design.ucf results/
+
+cd results
+echo 'Running ngdbuild'
+ngdbuild gige_sfp_example_design
+
+echo 'Running map'
+map -ol high -timing gige_sfp_example_design -o mapped.ncd
+
+echo 'Running par'
+par -ol high -w mapped.ncd routed.ncd mapped.pcf
+
+echo 'Running trce'
+trce -u -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed.ncd routed mapped.pcf -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_example_design -w -sdf_anno false routed.ncd routed.v
+
@@ -0,0 +1,13 @@
+verilog work ../example_design/gige_sfp_sync_block.v
+verilog work ../example_design/gige_sfp_reset_sync.v
+verilog work ../example_design/transceiver/gige_sfp_gtwizard_gt.v
+verilog work ../example_design/transceiver/gige_sfp_gtwizard.v
+verilog work ../example_design/transceiver/gige_sfp_tx_startup_fsm.v
+verilog work ../example_design/transceiver/gige_sfp_rx_startup_fsm.v
+verilog work ../example_design/transceiver/gige_sfp_gtwizard_init.v
+verilog work ../example_design/transceiver/gige_sfp_transceiver.v
+verilog work ../example_design/gige_sfp_tx_elastic_buffer.v
+verilog work ../example_design/gige_sfp_mod.v
+verilog work ../example_design/gige_sfp_block.v
+verilog work ../example_design/gige_sfp_example_design.v
+
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+# XST synthesis script for GPCS_PMA core.
+set -tmpdir .
+set -xsthdpdir ./xst
+run
+-ifmt mixed
+-top gige_sfp_example_design
+-ofn gige_sfp_example_design
+-p kintex7
+-uc example_design_xst.xcf
+-ifn xst.prj
+-iobuf YES
+