Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,49 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Tue Jan 15 20:47:01 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:mig_7series:1.8
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc7k410t
+SET devicefamily = kintex7
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ffg900
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT MIG_7_Series family Xilinx,_Inc. 1.8
+# END Select
+# BEGIN Parameters
+CSET component_name=ddr3_interface
+CSET xml_input_file=./ddr3_interface/mig.prj
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T05:23:34Z
+# END Extra information
+GENERATE
+# CRC: e97936bd