miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Pushing the bulk of UHD-3.7.0 code.

Browse Source 
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x300/coregen/ddr3_32bit/datasheet.txt
+79
View File
@@ -0,0 +1,79 @@
CORE Generator Options:
Target Device : xc7k410t-ffg900
Speed Grade : -2
HDL : verilog
Synthesis Tool : Foundation_ISE
MIG Output Options:
Module Name : ddr3_32bit
No of Controllers : 1
Selected Compatible Device(s) : xc7k325t-ffg900
FPGA Options:
System Clock Type : Single-Ended
Reference Clock Type : No Buffer
Debug Port : OFF
Internal Vref : disabled
IO Power Reduction : ON
XADC instantiation in MIG : Enabled
Extended FPGA Options:
DCI for DQ,DQS/DQS#,DM : enabled
Internal Termination (HR Banks) : 50 Ohms
/*******************************************************/
/* Controller 0 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Interface : AXI
Design Clock Frequency : 2000 ps (500.00 MHz)
Phy to Controller Clock Ratio : 2:1
Input Clock Period : 10000 ps
CLKFBOUT_MULT (PLL) : 10
DIVCLK_DIVIDE (PLL) : 1
VCC_AUX IO : 1.8V
Memory Type : Components
Memory Part : MT41J256m16XX-125
Equivalent Part(s) : MT41J256M16HA-125
Data Width : 32
ECC : Disabled
Data Mask : enabled
ORDERING : Normal
AXI Parameters :
Data Width : 128
Arbitration Scheme : ROUND_ROBIN
Narrow Burst Support : 1
ID Width : 4
Memory Options:
Burst Length (MR0[1:0]) : 8 - Fixed
Read Burst Type (MR0[3]) : Sequential
CAS Latency (MR0[6:4]) : 7
Output Drive Strength (MR1[5,1]) : RZQ/7
Controller CS option : Enable
Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/4
Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
Memory Address Mapping : BANK_ROW_COLUMN
Bank Selections:
System_Clock:
SignalName: sys_clk_i
PadLocation: AD17(SRCC_P) Bank: 32
System_Control:
SignalName: sys_rst
PadLocation: No connect Bank: Select Bank
SignalName: init_calib_complete
PadLocation: No connect Bank: Select Bank
SignalName: tg_compare_error
PadLocation: No connect Bank: Select Bank
top/x300/coregen/ddr3_32bit/ddr3_32bit.csv
+150
View File
@@ -0,0 +1,150 @@
#Generated by MIG Version 1.8
#Coregen 14.4 - Build Number P.49d on Thu Jan 24 15:58:25 2013
#FPGA Part xc7k410t-ffg900-2
IO Bank,Pin Number,Signal Name,IO Standard,Direction,Slew Rate,DiffPair Type,DiffPair Signal
34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
32,AD17,sys_clk_i,LVCMOS18,IN,,,
34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
32,AD17,sys_clk_i,LVCMOS18,IN,,,
34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
1 #Generated by MIG Version 1.8
2 #Coregen 14.4 - Build Number P.49d on Thu Jan 24 15:58:25 2013
3 #FPGA Part xc7k410t-ffg900-2
4 IO Bank,Pin Number,Signal Name,IO Standard,Direction,Slew Rate,DiffPair Type,DiffPair Signal
5 34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
6 34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
7 34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
8 34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
9 34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
10 34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
11 34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
12 34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
13 34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
14 34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
15 34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
16 34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
17 34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
18 34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
19 34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
20 34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
21 34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
22 34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
23 34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
24 34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
25 34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
26 34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
27 34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
28 34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
29 34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
30 34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
31 34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
32 34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
33 34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34 34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
35 34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
36 34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
37 33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
38 33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
39 33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
40 33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
41 33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
42 33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
43 33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
44 33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
45 33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
46 33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
47 33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
48 33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
49 33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
50 33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
51 33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
52 33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
53 33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
54 33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
55 33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
56 33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
57 33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
58 34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
59 33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
60 33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
61 33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
62 34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
63 34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
64 34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
65 34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
66 32,AD17,sys_clk_i,LVCMOS18,IN,,,
67 34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
68 34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
69 34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
70 34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
71 34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
72 34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
73 34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
74 34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
75 33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
76 33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
77 34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
78 34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
79 34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
80 34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
81 34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
82 34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
83 34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
84 34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
85 34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
86 34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
87 34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
88 34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
89 34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
90 34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
91 34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
92 34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
93 34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
94 34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
95 34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
96 34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
97 34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
98 34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
99 34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
100 34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
101 34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
102 34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
103 34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
104 34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
105 34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
106 34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
107 34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
108 34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
109 33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
110 33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
111 33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
112 33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
113 33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
114 33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
115 33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
116 33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
117 33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
118 33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
119 33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
120 33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
121 33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
122 33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
123 33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
124 33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
125 33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
126 33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
127 33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
128 33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
129 33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
130 34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
131 33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
132 33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
133 33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
134 34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
135 34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
136 34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
137 34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
138 32,AD17,sys_clk_i,LVCMOS18,IN,,,
139 34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
140 34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
141 34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
142 34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
143 34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
144 34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
145 34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
146 34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
147 33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
148 33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
top/x300/coregen/ddr3_32bit/docs/phy_only_support_readme.txt
+11
View File
@@ -0,0 +1,11 @@
This file includes the information about the PHY layer support:
- Folder "<component name>/user_design/rtl/phy" includes the PHY layer
RTL modules.
- The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v)
- PHY modules can be used in any environment by taking the RTL modules
listed in "phy" folder and PHY layer needs to be connected to
the memory controller.
- Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory
Controller Design)" for more details on PHY interface signaling,
parameter(s) and timing information.
top/x300/coregen/ddr3_32bit/docs/ug586_7Series_MIS.pdf
Executable
BIN
View File
Binary file not shown.
top/x300/coregen/ddr3_32bit/example_design/log.txt
+80
View File
@@ -0,0 +1,80 @@
Log file
Generated by MIG MIG Version 1.8
Coregen 14.4 - Build Number P.49d on Thu Jan 24 15:58:26 2013
Creating the directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design
Created the UCF file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/example_top.ucf Successfully
Created the SDC file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/example_top.xdc Successfully
Copied the Traffic Gen Files Successfully
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/../docs/phy_only_support_readme.txt Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/create_ise.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/makeproj.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/rem_files.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ise_flow.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/vivado.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/vivado_gui.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/rem_files.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/set_ise_prop.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/readme.txt Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/xst_options.txt Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_icon_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_ila_basic_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_ila_wrpath_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_ila_rdpath_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_vio_sync_async_out72_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/ddr_vio_async_in_sync_out_cg.xco Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/example_top.cdc Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/par/example_top.cpj Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/ddr3_model.v Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/ddr3_model_parameters.vh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/isim_files.prj Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/isim_options.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/isim_run.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/xsim_files.prj Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/xsim_options.tcl Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/xsim_run.sh Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/readme.txt Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/sim.do Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/sim_tb_top.v Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/wiredly.v Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/synth/example_top.lso Successfully
..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/synth/example_top.prj Successfully
..Successful
Created the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/rtl/example_top.v
Created the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/sim/sim_tb_top.v
The design output files are located in /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_32bit/example_design/rtl and ..example_design/par for rtl & ucf files respectively.
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.asy
+9
View File
@@ -0,0 +1,9 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 chipscope_icon
RECTANGLE Normal 32 32 544 864
LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.constraints/chipscope_icon.ucf
+9
View File
@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.constraints/chipscope_icon.xdc
+7
View File
@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.gise
+31
View File
@@ -0,0 +1,31 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_icon.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_icon.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_icon.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.ncf
+9
View File
@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.ngc
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.ucf
+9
View File
@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.v
+27
View File
@@ -0,0 +1,27 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Tue Jan 22 18:22:30 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
endmodule
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.veo
+28
View File
@@ -0,0 +1,28 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Tue Jan 22 18:22:30 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.xco
+56
View File
@@ -0,0 +1,56 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Jan 23 02:22:01 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 9e07fae8
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.xdc
+7
View File
@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon.xise
+361
View File
@@ -0,0 +1,361 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="chipscope_icon.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="chipscope_icon" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="chipscope_icon_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="chipscope_icon_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="chipscope_icon_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="chipscope_icon_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-22T18:22:32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FA49FD295DEF021862E9C20CE0FF44BA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon_flist.txt
+15
View File
@@ -0,0 +1,15 @@
# Output products list for <chipscope_icon>
chipscope_icon.asy
chipscope_icon.constraints/chipscope_icon.ucf
chipscope_icon.constraints/chipscope_icon.xdc
chipscope_icon.gise
chipscope_icon.ngc
chipscope_icon.ucf
chipscope_icon.v
chipscope_icon.veo
chipscope_icon.xco
chipscope_icon.xdc
chipscope_icon.xise
chipscope_icon_flist.txt
chipscope_icon_readme.txt
chipscope_icon_xmdf.tcl
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon_readme.txt
+45
View File
@@ -0,0 +1,45 @@
The following files were generated for 'chipscope_icon' in directory
/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/example_design/par/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_icon.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_icon.constraints/chipscope_icon.ucf
* chipscope_icon.constraints/chipscope_icon.xdc
* chipscope_icon.ngc
* chipscope_icon.ucf
* chipscope_icon.v
* chipscope_icon.veo
* chipscope_icon.xdc
* chipscope_icon_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_icon.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* chipscope_icon.gise
* chipscope_icon.xise
Deliver Readme:
Readme file for the IP.
* chipscope_icon_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_icon_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_icon_xmdf.tcl
Executable
+88
View File
@@ -0,0 +1,88 @@
# The package naming convention is <core_name>_xmdf
package provide chipscope_icon_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::chipscope_icon_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::chipscope_icon_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon
}
# ::chipscope_icon_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.asy
+17
View File
@@ -0,0 +1,17 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 chipscope_ila
RECTANGLE Normal 32 32 288 704
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName control[35:0]
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Wide 0 176 32 176
PIN 0 176 LEFT 36
PINATTR PinName trig0[191:0]
PINATTR Polarity IN
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.cdc
+208
View File
@@ -0,0 +1,208 @@
#ChipScope Core Generator Project File Version 3.0
#Tue Jan 22 18:24:11 PST 2013
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
SignalExport.bus<0000>.precision=0
SignalExport.bus<0000>.radix=Bin
SignalExport.bus<0000>.scaleFactor=1.0
SignalExport.clockChannel=CLK
SignalExport.dataEqualsTrigger=true
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerChannel<0000><0008>=TRIG0[8]
SignalExport.triggerChannel<0000><0009>=TRIG0[9]
SignalExport.triggerChannel<0000><0010>=TRIG0[10]
SignalExport.triggerChannel<0000><0011>=TRIG0[11]
SignalExport.triggerChannel<0000><0012>=TRIG0[12]
SignalExport.triggerChannel<0000><0013>=TRIG0[13]
SignalExport.triggerChannel<0000><0014>=TRIG0[14]
SignalExport.triggerChannel<0000><0015>=TRIG0[15]
SignalExport.triggerChannel<0000><0016>=TRIG0[16]
SignalExport.triggerChannel<0000><0017>=TRIG0[17]
SignalExport.triggerChannel<0000><0018>=TRIG0[18]
SignalExport.triggerChannel<0000><0019>=TRIG0[19]
SignalExport.triggerChannel<0000><0020>=TRIG0[20]
SignalExport.triggerChannel<0000><0021>=TRIG0[21]
SignalExport.triggerChannel<0000><0022>=TRIG0[22]
SignalExport.triggerChannel<0000><0023>=TRIG0[23]
SignalExport.triggerChannel<0000><0024>=TRIG0[24]
SignalExport.triggerChannel<0000><0025>=TRIG0[25]
SignalExport.triggerChannel<0000><0026>=TRIG0[26]
SignalExport.triggerChannel<0000><0027>=TRIG0[27]
SignalExport.triggerChannel<0000><0028>=TRIG0[28]
SignalExport.triggerChannel<0000><0029>=TRIG0[29]
SignalExport.triggerChannel<0000><0030>=TRIG0[30]
SignalExport.triggerChannel<0000><0031>=TRIG0[31]
SignalExport.triggerChannel<0000><0032>=TRIG0[32]
SignalExport.triggerChannel<0000><0033>=TRIG0[33]
SignalExport.triggerChannel<0000><0034>=TRIG0[34]
SignalExport.triggerChannel<0000><0035>=TRIG0[35]
SignalExport.triggerChannel<0000><0036>=TRIG0[36]
SignalExport.triggerChannel<0000><0037>=TRIG0[37]
SignalExport.triggerChannel<0000><0038>=TRIG0[38]
SignalExport.triggerChannel<0000><0039>=TRIG0[39]
SignalExport.triggerChannel<0000><0040>=TRIG0[40]
SignalExport.triggerChannel<0000><0041>=TRIG0[41]
SignalExport.triggerChannel<0000><0042>=TRIG0[42]
SignalExport.triggerChannel<0000><0043>=TRIG0[43]
SignalExport.triggerChannel<0000><0044>=TRIG0[44]
SignalExport.triggerChannel<0000><0045>=TRIG0[45]
SignalExport.triggerChannel<0000><0046>=TRIG0[46]
SignalExport.triggerChannel<0000><0047>=TRIG0[47]
SignalExport.triggerChannel<0000><0048>=TRIG0[48]
SignalExport.triggerChannel<0000><0049>=TRIG0[49]
SignalExport.triggerChannel<0000><0050>=TRIG0[50]
SignalExport.triggerChannel<0000><0051>=TRIG0[51]
SignalExport.triggerChannel<0000><0052>=TRIG0[52]
SignalExport.triggerChannel<0000><0053>=TRIG0[53]
SignalExport.triggerChannel<0000><0054>=TRIG0[54]
SignalExport.triggerChannel<0000><0055>=TRIG0[55]
SignalExport.triggerChannel<0000><0056>=TRIG0[56]
SignalExport.triggerChannel<0000><0057>=TRIG0[57]
SignalExport.triggerChannel<0000><0058>=TRIG0[58]
SignalExport.triggerChannel<0000><0059>=TRIG0[59]
SignalExport.triggerChannel<0000><0060>=TRIG0[60]
SignalExport.triggerChannel<0000><0061>=TRIG0[61]
SignalExport.triggerChannel<0000><0062>=TRIG0[62]
SignalExport.triggerChannel<0000><0063>=TRIG0[63]
SignalExport.triggerChannel<0000><0064>=TRIG0[64]
SignalExport.triggerChannel<0000><0065>=TRIG0[65]
SignalExport.triggerChannel<0000><0066>=TRIG0[66]
SignalExport.triggerChannel<0000><0067>=TRIG0[67]
SignalExport.triggerChannel<0000><0068>=TRIG0[68]
SignalExport.triggerChannel<0000><0069>=TRIG0[69]
SignalExport.triggerChannel<0000><0070>=TRIG0[70]
SignalExport.triggerChannel<0000><0071>=TRIG0[71]
SignalExport.triggerChannel<0000><0072>=TRIG0[72]
SignalExport.triggerChannel<0000><0073>=TRIG0[73]
SignalExport.triggerChannel<0000><0074>=TRIG0[74]
SignalExport.triggerChannel<0000><0075>=TRIG0[75]
SignalExport.triggerChannel<0000><0076>=TRIG0[76]
SignalExport.triggerChannel<0000><0077>=TRIG0[77]
SignalExport.triggerChannel<0000><0078>=TRIG0[78]
SignalExport.triggerChannel<0000><0079>=TRIG0[79]
SignalExport.triggerChannel<0000><0080>=TRIG0[80]
SignalExport.triggerChannel<0000><0081>=TRIG0[81]
SignalExport.triggerChannel<0000><0082>=TRIG0[82]
SignalExport.triggerChannel<0000><0083>=TRIG0[83]
SignalExport.triggerChannel<0000><0084>=TRIG0[84]
SignalExport.triggerChannel<0000><0085>=TRIG0[85]
SignalExport.triggerChannel<0000><0086>=TRIG0[86]
SignalExport.triggerChannel<0000><0087>=TRIG0[87]
SignalExport.triggerChannel<0000><0088>=TRIG0[88]
SignalExport.triggerChannel<0000><0089>=TRIG0[89]
SignalExport.triggerChannel<0000><0090>=TRIG0[90]
SignalExport.triggerChannel<0000><0091>=TRIG0[91]
SignalExport.triggerChannel<0000><0092>=TRIG0[92]
SignalExport.triggerChannel<0000><0093>=TRIG0[93]
SignalExport.triggerChannel<0000><0094>=TRIG0[94]
SignalExport.triggerChannel<0000><0095>=TRIG0[95]
SignalExport.triggerChannel<0000><0096>=TRIG0[96]
SignalExport.triggerChannel<0000><0097>=TRIG0[97]
SignalExport.triggerChannel<0000><0098>=TRIG0[98]
SignalExport.triggerChannel<0000><0099>=TRIG0[99]
SignalExport.triggerChannel<0000><0100>=TRIG0[100]
SignalExport.triggerChannel<0000><0101>=TRIG0[101]
SignalExport.triggerChannel<0000><0102>=TRIG0[102]
SignalExport.triggerChannel<0000><0103>=TRIG0[103]
SignalExport.triggerChannel<0000><0104>=TRIG0[104]
SignalExport.triggerChannel<0000><0105>=TRIG0[105]
SignalExport.triggerChannel<0000><0106>=TRIG0[106]
SignalExport.triggerChannel<0000><0107>=TRIG0[107]
SignalExport.triggerChannel<0000><0108>=TRIG0[108]
SignalExport.triggerChannel<0000><0109>=TRIG0[109]
SignalExport.triggerChannel<0000><0110>=TRIG0[110]
SignalExport.triggerChannel<0000><0111>=TRIG0[111]
SignalExport.triggerChannel<0000><0112>=TRIG0[112]
SignalExport.triggerChannel<0000><0113>=TRIG0[113]
SignalExport.triggerChannel<0000><0114>=TRIG0[114]
SignalExport.triggerChannel<0000><0115>=TRIG0[115]
SignalExport.triggerChannel<0000><0116>=TRIG0[116]
SignalExport.triggerChannel<0000><0117>=TRIG0[117]
SignalExport.triggerChannel<0000><0118>=TRIG0[118]
SignalExport.triggerChannel<0000><0119>=TRIG0[119]
SignalExport.triggerChannel<0000><0120>=TRIG0[120]
SignalExport.triggerChannel<0000><0121>=TRIG0[121]
SignalExport.triggerChannel<0000><0122>=TRIG0[122]
SignalExport.triggerChannel<0000><0123>=TRIG0[123]
SignalExport.triggerChannel<0000><0124>=TRIG0[124]
SignalExport.triggerChannel<0000><0125>=TRIG0[125]
SignalExport.triggerChannel<0000><0126>=TRIG0[126]
SignalExport.triggerChannel<0000><0127>=TRIG0[127]
SignalExport.triggerChannel<0000><0128>=TRIG0[128]
SignalExport.triggerChannel<0000><0129>=TRIG0[129]
SignalExport.triggerChannel<0000><0130>=TRIG0[130]
SignalExport.triggerChannel<0000><0131>=TRIG0[131]
SignalExport.triggerChannel<0000><0132>=TRIG0[132]
SignalExport.triggerChannel<0000><0133>=TRIG0[133]
SignalExport.triggerChannel<0000><0134>=TRIG0[134]
SignalExport.triggerChannel<0000><0135>=TRIG0[135]
SignalExport.triggerChannel<0000><0136>=TRIG0[136]
SignalExport.triggerChannel<0000><0137>=TRIG0[137]
SignalExport.triggerChannel<0000><0138>=TRIG0[138]
SignalExport.triggerChannel<0000><0139>=TRIG0[139]
SignalExport.triggerChannel<0000><0140>=TRIG0[140]
SignalExport.triggerChannel<0000><0141>=TRIG0[141]
SignalExport.triggerChannel<0000><0142>=TRIG0[142]
SignalExport.triggerChannel<0000><0143>=TRIG0[143]
SignalExport.triggerChannel<0000><0144>=TRIG0[144]
SignalExport.triggerChannel<0000><0145>=TRIG0[145]
SignalExport.triggerChannel<0000><0146>=TRIG0[146]
SignalExport.triggerChannel<0000><0147>=TRIG0[147]
SignalExport.triggerChannel<0000><0148>=TRIG0[148]
SignalExport.triggerChannel<0000><0149>=TRIG0[149]
SignalExport.triggerChannel<0000><0150>=TRIG0[150]
SignalExport.triggerChannel<0000><0151>=TRIG0[151]
SignalExport.triggerChannel<0000><0152>=TRIG0[152]
SignalExport.triggerChannel<0000><0153>=TRIG0[153]
SignalExport.triggerChannel<0000><0154>=TRIG0[154]
SignalExport.triggerChannel<0000><0155>=TRIG0[155]
SignalExport.triggerChannel<0000><0156>=TRIG0[156]
SignalExport.triggerChannel<0000><0157>=TRIG0[157]
SignalExport.triggerChannel<0000><0158>=TRIG0[158]
SignalExport.triggerChannel<0000><0159>=TRIG0[159]
SignalExport.triggerChannel<0000><0160>=TRIG0[160]
SignalExport.triggerChannel<0000><0161>=TRIG0[161]
SignalExport.triggerChannel<0000><0162>=TRIG0[162]
SignalExport.triggerChannel<0000><0163>=TRIG0[163]
SignalExport.triggerChannel<0000><0164>=TRIG0[164]
SignalExport.triggerChannel<0000><0165>=TRIG0[165]
SignalExport.triggerChannel<0000><0166>=TRIG0[166]
SignalExport.triggerChannel<0000><0167>=TRIG0[167]
SignalExport.triggerChannel<0000><0168>=TRIG0[168]
SignalExport.triggerChannel<0000><0169>=TRIG0[169]
SignalExport.triggerChannel<0000><0170>=TRIG0[170]
SignalExport.triggerChannel<0000><0171>=TRIG0[171]
SignalExport.triggerChannel<0000><0172>=TRIG0[172]
SignalExport.triggerChannel<0000><0173>=TRIG0[173]
SignalExport.triggerChannel<0000><0174>=TRIG0[174]
SignalExport.triggerChannel<0000><0175>=TRIG0[175]
SignalExport.triggerChannel<0000><0176>=TRIG0[176]
SignalExport.triggerChannel<0000><0177>=TRIG0[177]
SignalExport.triggerChannel<0000><0178>=TRIG0[178]
SignalExport.triggerChannel<0000><0179>=TRIG0[179]
SignalExport.triggerChannel<0000><0180>=TRIG0[180]
SignalExport.triggerChannel<0000><0181>=TRIG0[181]
SignalExport.triggerChannel<0000><0182>=TRIG0[182]
SignalExport.triggerChannel<0000><0183>=TRIG0[183]
SignalExport.triggerChannel<0000><0184>=TRIG0[184]
SignalExport.triggerChannel<0000><0185>=TRIG0[185]
SignalExport.triggerChannel<0000><0186>=TRIG0[186]
SignalExport.triggerChannel<0000><0187>=TRIG0[187]
SignalExport.triggerChannel<0000><0188>=TRIG0[188]
SignalExport.triggerChannel<0000><0189>=TRIG0[189]
SignalExport.triggerChannel<0000><0190>=TRIG0[190]
SignalExport.triggerChannel<0000><0191>=TRIG0[191]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPortCount=1
SignalExport.triggerPortIsData<0000>=true
SignalExport.triggerPortWidth<0000>=192
SignalExport.type=ila
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.constraints/chipscope_ila.ucf
+15
View File
@@ -0,0 +1,15 @@
#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.constraints/chipscope_ila.xdc
+6
View File
@@ -0,0 +1,6 @@
#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.gise
+31
View File
@@ -0,0 +1,31 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.ncf
+15
View File
@@ -0,0 +1,15 @@
#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.ngc
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.ucf
+15
View File
@@ -0,0 +1,15 @@
#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.v
+31
View File
@@ -0,0 +1,31 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila.v
// /___/ /\ Timestamp : Tue Jan 22 18:24:11 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_ila(
CONTROL,
CLK,
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL;
input CLK;
input [191 : 0] TRIG0;
endmodule
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.veo
+30
View File
@@ -0,0 +1,30 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila.veo
// /___/ /\ Timestamp : Tue Jan 22 18:24:11 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_ila YourInstanceName (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK), // IN
.TRIG0(TRIG0) // IN BUS [191:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.xco
+141
View File
@@ -0,0 +1,141 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Jan 23 02:22:35 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=chipscope_ila
CSET constraint_type=external
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=0
CSET data_same_as_trigger=true
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET example_design=false
CSET exclude_from_data_storage_1=false
CSET exclude_from_data_storage_10=false
CSET exclude_from_data_storage_11=false
CSET exclude_from_data_storage_12=false
CSET exclude_from_data_storage_13=false
CSET exclude_from_data_storage_14=false
CSET exclude_from_data_storage_15=false
CSET exclude_from_data_storage_16=false
CSET exclude_from_data_storage_2=false
CSET exclude_from_data_storage_3=false
CSET exclude_from_data_storage_4=false
CSET exclude_from_data_storage_5=false
CSET exclude_from_data_storage_6=false
CSET exclude_from_data_storage_7=false
CSET exclude_from_data_storage_8=false
CSET exclude_from_data_storage_9=false
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=192
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 7c772861
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.xdc
+6
View File
@@ -0,0 +1,6 @@
#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila.xise
+361
View File
@@ -0,0 +1,361 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="chipscope_ila.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="chipscope_ila" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="chipscope_ila_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="chipscope_ila_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="chipscope_ila_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="chipscope_ila_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-22T18:24:13" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3F44703BFD18C778089B3E7E34E627A9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila_flist.txt
+17
View File
@@ -0,0 +1,17 @@
# Output products list for <chipscope_ila>
chipscope_ila.asy
chipscope_ila.cdc
chipscope_ila.constraints/chipscope_ila.ucf
chipscope_ila.constraints/chipscope_ila.xdc
chipscope_ila.gise
chipscope_ila.ncf
chipscope_ila.ngc
chipscope_ila.ucf
chipscope_ila.v
chipscope_ila.veo
chipscope_ila.xco
chipscope_ila.xdc
chipscope_ila.xise
chipscope_ila_flist.txt
chipscope_ila_readme.txt
chipscope_ila_xmdf.tcl
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila_readme.txt
+47
View File
@@ -0,0 +1,47 @@
The following files were generated for 'chipscope_ila' in directory
/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/example_design/par/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_ila.cdc
* chipscope_ila.constraints/chipscope_ila.ucf
* chipscope_ila.constraints/chipscope_ila.xdc
* chipscope_ila.ncf
* chipscope_ila.ngc
* chipscope_ila.ucf
* chipscope_ila.v
* chipscope_ila.veo
* chipscope_ila.xdc
* chipscope_ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_ila.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* chipscope_ila.gise
* chipscope_ila.xise
Deliver Readme:
Readme file for the IP.
* chipscope_ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen/ddr3_32bit/example_design/par/chipscope_ila_xmdf.tcl
Executable
+87
View File
@@ -0,0 +1,87 @@
# The package naming convention is <core_name>_xmdf
package provide chipscope_ila_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::chipscope_ila_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::chipscope_ila_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila
}
# ::chipscope_ila_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen/ddr3_32bit/example_design/par/compatible_ucf/xc7k325tffg900_pkg.ucf
+175
View File
@@ -0,0 +1,175 @@
##################################################################################################
##
## Xilinx, Inc. 2010 www.xilinx.com
## Thu Jan 24 15:58:25 2013
## Generated by MIG Version 1.8
##
##################################################################################################
## File name : example_top.ucf
## Details : Constraints file
## FPGA Family: KINTEX7
## FPGA Part: XC7K325TFFG900_PKG
## Speedgrade: -2
## Design Entry: VERILOG
## Frequency: 500 MHz
## Time Period: 2000 ps
##################################################################################################
##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-125
## Data Width: 32
## Time Period: 2000
## Data Mask: 1
##################################################################################################
NET "sys_clk_i" TNM_NET = TNM_sys_clk;
TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 10 ns;
#NET "clk_ref_i" TNM_NET = TNM_clk_ref;
#TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;
# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
# to the following:
# WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
# placed at an optimal clock IOB / PLL site pair.
# This warning can be ignored. See the Users Guide for more information.
NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
PIN "*/u_ddr3_infrastructure/plle2_i.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;
############## NET - IOSTANDARD ##################
NET "ddr3_dq[0]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_34
NET "ddr3_dq[1]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_34
NET "ddr3_dq[2]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_34
NET "ddr3_dq[3]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_34
NET "ddr3_dq[4]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_34
NET "ddr3_dq[5]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_34
NET "ddr3_dq[6]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_34
NET "ddr3_dq[7]" LOC = "AC7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_34
NET "ddr3_dq[8]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_34
NET "ddr3_dq[9]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_34
NET "ddr3_dq[10]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_34
NET "ddr3_dq[11]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_34
NET "ddr3_dq[12]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_34
NET "ddr3_dq[13]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_34
NET "ddr3_dq[14]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_34
NET "ddr3_dq[15]" LOC = "AF6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_34
NET "ddr3_dq[16]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34
NET "ddr3_dq[17]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34
NET "ddr3_dq[18]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34
NET "ddr3_dq[19]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_34
NET "ddr3_dq[20]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_34
NET "ddr3_dq[21]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17P_T2_34
NET "ddr3_dq[22]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17N_T2_34
NET "ddr3_dq[23]" LOC = "AJ3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_34
NET "ddr3_dq[24]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_34
NET "ddr3_dq[25]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_34
NET "ddr3_dq[26]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_34
NET "ddr3_dq[27]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_34
NET "ddr3_dq[28]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_34
NET "ddr3_dq[29]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_34
NET "ddr3_dq[30]" LOC = "AK5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_34
NET "ddr3_dq[31]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_34
NET "ddr3_addr[14]" LOC = "AA12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_33
NET "ddr3_addr[13]" LOC = "AB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_33
NET "ddr3_addr[12]" LOC = "AA8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_33
NET "ddr3_addr[11]" LOC = "AB8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_33
NET "ddr3_addr[10]" LOC = "Y11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_33
NET "ddr3_addr[9]" LOC = "Y10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_33
NET "ddr3_addr[8]" LOC = "AA11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_33
NET "ddr3_addr[7]" LOC = "AA10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_33
NET "ddr3_addr[6]" LOC = "AA13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_33
NET "ddr3_addr[5]" LOC = "AB13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6N_T0_VREF_33
NET "ddr3_addr[4]" LOC = "AB10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_33
NET "ddr3_addr[3]" LOC = "AC10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_33
NET "ddr3_addr[2]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_33
NET "ddr3_addr[1]" LOC = "AE8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_33
NET "ddr3_addr[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_33
NET "ddr3_ba[2]" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_33
NET "ddr3_ba[1]" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_33
NET "ddr3_ba[0]" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_33
NET "ddr3_ras_n" LOC = "AE11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_33
NET "ddr3_cas_n" LOC = "AF11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_33
NET "ddr3_we_n" LOC = "AD12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_33
NET "ddr3_reset_n" LOC = "AG5" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_34
NET "ddr3_cke[0]" LOC = "AJ9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_33
NET "ddr3_odt[0]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_33
NET "ddr3_cs_n[0]" LOC = "AD11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_33
NET "ddr3_dm[0]" LOC = "AD4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_34
NET "ddr3_dm[1]" LOC = "AF3" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_34
NET "ddr3_dm[2]" LOC = "AH4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34
NET "ddr3_dm[3]" LOC = "AF8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_34
NET "sys_clk_i" LOC = "AD17" | IOSTANDARD = LVCMOS18 | VCCAUX_IO = DONTCARE ; # Pad function: IO_L14P_T2_SRCC_32
NET "ddr3_dqs_p[0]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34
NET "ddr3_dqs_n[0]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34
NET "ddr3_dqs_p[1]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_34
NET "ddr3_dqs_n[1]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_34
NET "ddr3_dqs_p[2]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34
NET "ddr3_dqs_n[2]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34
NET "ddr3_dqs_p[3]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_34
NET "ddr3_dqs_n[3]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_34
NET "ddr3_ck_p[0]" LOC = "AB9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_33
NET "ddr3_ck_n[0]" LOC = "AC9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_33
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107;
INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y1;
NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2000 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;
INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;
top/x300/coregen/ddr3_32bit/example_design/par/compatible_ucf/xc7k325tffg900_pkg.xdc
+547
View File
@@ -0,0 +1,547 @@
##################################################################################################
##
## Xilinx, Inc. 2010 www.xilinx.com
## Thu Jan 24 15:58:25 2013
## Generated by MIG Version 1.8
##
##################################################################################################
## File name : example_top.sdc
## Details : Constraints file
## FPGA Family: KINTEX7
## FPGA Part: XC7K325TFFG900_PKG
## Speedgrade: -2
## Design Entry: VERILOG
## Frequency: 500 MHz
## Time Period: 2000 ps
##################################################################################################
##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-125
## Data Width: 32
## Time Period: 2000
## Data Mask: 1
##################################################################################################
create_clock -name sys_clk_i -period 10 [get_ports sys_clk_i]
#set_propagated_clock sys_clk_i
#create_clock -name clk_ref_i -period 5 [get_ports clk_ref_i]
#set_propagated_clock clk_ref_i
# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
# to the following:
# WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
# placed at an optimal clock IOB / PLL site pair.
# This warning can be ignored. See the Users Guide for more information.
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_i]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
############## NET - IOSTANDARD ##################
# PadFunction: IO_L1N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]
set_property LOC AD3 [get_ports {ddr3_dq[0]}]
# PadFunction: IO_L2P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]
set_property LOC AC2 [get_ports {ddr3_dq[1]}]
# PadFunction: IO_L2N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]
set_property LOC AC1 [get_ports {ddr3_dq[2]}]
# PadFunction: IO_L4P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]
set_property LOC AC5 [get_ports {ddr3_dq[3]}]
# PadFunction: IO_L4N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]
set_property LOC AC4 [get_ports {ddr3_dq[4]}]
# PadFunction: IO_L5P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]
set_property LOC AD6 [get_ports {ddr3_dq[5]}]
# PadFunction: IO_L5N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]
set_property LOC AE6 [get_ports {ddr3_dq[6]}]
# PadFunction: IO_L6P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]
set_property LOC AC7 [get_ports {ddr3_dq[7]}]
# PadFunction: IO_L7N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]
set_property LOC AF2 [get_ports {ddr3_dq[8]}]
# PadFunction: IO_L8P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]
set_property LOC AE1 [get_ports {ddr3_dq[9]}]
# PadFunction: IO_L8N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]
set_property LOC AF1 [get_ports {ddr3_dq[10]}]
# PadFunction: IO_L10P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]
set_property LOC AE4 [get_ports {ddr3_dq[11]}]
# PadFunction: IO_L10N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]
set_property LOC AE3 [get_ports {ddr3_dq[12]}]
# PadFunction: IO_L11P_T1_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]
set_property LOC AE5 [get_ports {ddr3_dq[13]}]
# PadFunction: IO_L11N_T1_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]
set_property LOC AF5 [get_ports {ddr3_dq[14]}]
# PadFunction: IO_L12P_T1_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]
set_property LOC AF6 [get_ports {ddr3_dq[15]}]
# PadFunction: IO_L13N_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]
set_property LOC AJ4 [get_ports {ddr3_dq[16]}]
# PadFunction: IO_L14P_T2_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]
set_property LOC AH6 [get_ports {ddr3_dq[17]}]
# PadFunction: IO_L14N_T2_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]
set_property LOC AH5 [get_ports {ddr3_dq[18]}]
# PadFunction: IO_L16P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]
set_property LOC AH2 [get_ports {ddr3_dq[19]}]
# PadFunction: IO_L16N_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]
set_property LOC AJ2 [get_ports {ddr3_dq[20]}]
# PadFunction: IO_L17P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]
set_property LOC AJ1 [get_ports {ddr3_dq[21]}]
# PadFunction: IO_L17N_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]
set_property LOC AK1 [get_ports {ddr3_dq[22]}]
# PadFunction: IO_L18P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]
set_property LOC AJ3 [get_ports {ddr3_dq[23]}]
# PadFunction: IO_L20P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]
set_property LOC AF7 [get_ports {ddr3_dq[24]}]
# PadFunction: IO_L20N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]
set_property LOC AG7 [get_ports {ddr3_dq[25]}]
# PadFunction: IO_L22P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]
set_property LOC AJ6 [get_ports {ddr3_dq[26]}]
# PadFunction: IO_L22N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]
set_property LOC AK6 [get_ports {ddr3_dq[27]}]
# PadFunction: IO_L23P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]
set_property LOC AJ8 [get_ports {ddr3_dq[28]}]
# PadFunction: IO_L23N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]
set_property LOC AK8 [get_ports {ddr3_dq[29]}]
# PadFunction: IO_L24P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]
set_property LOC AK5 [get_ports {ddr3_dq[30]}]
# PadFunction: IO_L24N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]
set_property LOC AK4 [get_ports {ddr3_dq[31]}]
# PadFunction: IO_L1P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
set_property LOC AA12 [get_ports {ddr3_addr[14]}]
# PadFunction: IO_L1N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
set_property LOC AB12 [get_ports {ddr3_addr[13]}]
# PadFunction: IO_L2P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
set_property LOC AA8 [get_ports {ddr3_addr[12]}]
# PadFunction: IO_L2N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
set_property LOC AB8 [get_ports {ddr3_addr[11]}]
# PadFunction: IO_L4P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
set_property LOC Y11 [get_ports {ddr3_addr[10]}]
# PadFunction: IO_L4N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
set_property LOC Y10 [get_ports {ddr3_addr[9]}]
# PadFunction: IO_L5P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
set_property LOC AA11 [get_ports {ddr3_addr[8]}]
# PadFunction: IO_L5N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
set_property LOC AA10 [get_ports {ddr3_addr[7]}]
# PadFunction: IO_L6P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
set_property LOC AA13 [get_ports {ddr3_addr[6]}]
# PadFunction: IO_L6N_T0_VREF_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
set_property LOC AB13 [get_ports {ddr3_addr[5]}]
# PadFunction: IO_L7P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
set_property LOC AB10 [get_ports {ddr3_addr[4]}]
# PadFunction: IO_L7N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
set_property LOC AC10 [get_ports {ddr3_addr[3]}]
# PadFunction: IO_L8P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
set_property LOC AD8 [get_ports {ddr3_addr[2]}]
# PadFunction: IO_L8N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
set_property LOC AE8 [get_ports {ddr3_addr[1]}]
# PadFunction: IO_L9P_T1_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property LOC AC12 [get_ports {ddr3_addr[0]}]
# PadFunction: IO_L9N_T1_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
set_property LOC AC11 [get_ports {ddr3_ba[2]}]
# PadFunction: IO_L10P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
set_property LOC AD9 [get_ports {ddr3_ba[1]}]
# PadFunction: IO_L10N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
set_property LOC AE9 [get_ports {ddr3_ba[0]}]
# PadFunction: IO_L11P_T1_SRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ras_n}]
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property LOC AE11 [get_ports {ddr3_ras_n}]
# PadFunction: IO_L11N_T1_SRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cas_n}]
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property LOC AF11 [get_ports {ddr3_cas_n}]
# PadFunction: IO_L12P_T1_MRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_we_n}]
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property LOC AD12 [get_ports {ddr3_we_n}]
# PadFunction: IO_L12N_T1_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_reset_n}]
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
set_property LOC AG5 [get_ports {ddr3_reset_n}]
# PadFunction: IO_L15P_T2_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cke[0]}]
set_property SLEW FAST [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
set_property LOC AJ9 [get_ports {ddr3_cke[0]}]
# PadFunction: IO_L15N_T2_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_odt[0]}]
set_property SLEW FAST [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
set_property LOC AK9 [get_ports {ddr3_odt[0]}]
# PadFunction: IO_L12N_T1_MRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
set_property LOC AD11 [get_ports {ddr3_cs_n[0]}]
# PadFunction: IO_L1P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[0]}]
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
set_property LOC AD4 [get_ports {ddr3_dm[0]}]
# PadFunction: IO_L7P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[1]}]
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
set_property LOC AF3 [get_ports {ddr3_dm[1]}]
# PadFunction: IO_L13P_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[2]}]
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
set_property LOC AH4 [get_ports {ddr3_dm[2]}]
# PadFunction: IO_L19P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[3]}]
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
set_property LOC AF8 [get_ports {ddr3_dm[3]}]
# PadFunction: IO_L14P_T2_SRCC_32
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_i}]
set_property IOSTANDARD LVCMOS18 [get_ports {sys_clk_i}]
set_property LOC AD17 [get_ports {sys_clk_i}]
# PadFunction: IO_L3P_T0_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]
set_property LOC AD2 [get_ports {ddr3_dqs_p[0]}]
# PadFunction: IO_L3N_T0_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]
set_property LOC AD1 [get_ports {ddr3_dqs_n[0]}]
# PadFunction: IO_L9P_T1_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]
set_property LOC AG4 [get_ports {ddr3_dqs_p[1]}]
# PadFunction: IO_L9N_T1_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]
set_property LOC AG3 [get_ports {ddr3_dqs_n[1]}]
# PadFunction: IO_L15P_T2_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]
set_property LOC AG2 [get_ports {ddr3_dqs_p[2]}]
# PadFunction: IO_L15N_T2_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]
set_property LOC AH1 [get_ports {ddr3_dqs_n[2]}]
# PadFunction: IO_L21P_T3_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]
set_property LOC AH7 [get_ports {ddr3_dqs_p[3]}]
# PadFunction: IO_L21N_T3_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]
set_property LOC AJ7 [get_ports {ddr3_dqs_n[3]}]
# PadFunction: IO_L3P_T0_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ck_p[0]}]
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
set_property LOC AB9 [get_ports {ddr3_ck_p[0]}]
# PadFunction: IO_L3N_T0_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ck_n[0]}]
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
set_property LOC AC9 [get_ports {ddr3_ck_n[0]}]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out]
## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in]
## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in]
## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in]
set_property LOC OUT_FIFO_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo]
set_property LOC OUT_FIFO_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo]
set_property LOC OUT_FIFO_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo]
set_property LOC OUT_FIFO_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo]
set_property LOC OUT_FIFO_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo]
set_property LOC OUT_FIFO_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo]
set_property LOC OUT_FIFO_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo]
set_property LOC IN_FIFO_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo]
set_property LOC PHY_CONTROL_X1Y1 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i]
set_property LOC PHY_CONTROL_X1Y2 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i]
set_property LOC PHASER_REF_X1Y1 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i]
set_property LOC PHASER_REF_X1Y2 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i]
set_property LOC OLOGIC_X1Y143 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y131 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y119 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y107 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts]
set_property LOC PLLE2_ADV_X1Y1 [get_cells u_ddr3_32bit/u_ddr3_infrastructure/plle2_i]
set_property LOC MMCME2_ADV_X1Y1 [get_cells u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i]
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-setup 6
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-hold 5
set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/device_temp_sync_r1*}] \
-setup 12 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/device_temp_sync_r1*}] \
-hold 11 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/xadc_supplied_temperature.rst_r1*}] \
-setup 2 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/xadc_supplied_temperature.rst_r1*}] \
-hold 1 -end
top/x300/coregen/ddr3_32bit/example_design/par/coregen.cgc
+668
View File
@@ -0,0 +1,668 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>CoreGen</spirit:library>
<spirit:name>coregen</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>chipscope_icon</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="chipscope_icon" spirit:version="1.06.a" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">chipscope_icon</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_SCAN_CHAIN">USER1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXAMPLE_DESIGN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SOFTBSCAN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXT_BSCAN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUMBER_CONTROL_PORTS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONSTRAINT_TYPE">external</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_UNUSED_BSCAN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_JTAG_BUFG">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_SCAN_CHAIN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL0">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL4">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL5">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL6">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL7">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL8">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CONTROL_PORTS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_JTAG_BUFG">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_UNUSED_BSCAN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONSTRAINT_TYPE">external</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXAMPLE_DESIGN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTBSCAN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EXT_BSCAN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL10">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL11">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL12">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CONTROL14">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_NEW_PARSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPONENT_NAME">chipscope_icon</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XCO_LIST">Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:instanceProperties xmlns:xilinx="http://www.xilinx.com">
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc7k410t</xilinx:device>
<xilinx:deviceFamily>kintex7</xilinx:deviceFamily>
<xilinx:package>ffg900</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Structural</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2012-12-18+02:47</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
<xilinx:generationHistory>
<xilinx:fileSet>
<xilinx:name>model_parameter_resolution_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ip_xco_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon.xco</xilinx:name>
<xilinx:userFileType>xco</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:01 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x9FBB1DDF</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ngc_netlist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon.constraints/chipscope_icon.ucf</xilinx:name>
<xilinx:userFileType>ucf</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x4E907B10</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.constraints/chipscope_icon.xdc</xilinx:name>
<xilinx:userFileType>xdc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x23B3A75F</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.ngc</xilinx:name>
<xilinx:userFileType>ngc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:26 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x7C73C7C2</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.ucf</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>ucf</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x4E907B10</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.v</xilinx:name>
<xilinx:userFileType>verilog</xilinx:userFileType>
<xilinx:userFileType>verilogSynthesis</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x0981F7E0</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.veo</xilinx:name>
<xilinx:userFileType>veo</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xCAC27C17</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.xdc</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xdc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x23B3A75F</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon_xmdf.tcl</xilinx:name>
<xilinx:userFileType>tcl</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:01 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xA9BCAE1B</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>instantiation_template_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>asy_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon.asy</xilinx:name>
<xilinx:userFileType>asy</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:30 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xEE64DF2A</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>xmdf_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ise_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon.gise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>gise</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:32 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x2CE4C054</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_icon.xise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xise</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:32 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xA94D5E36</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>deliver_readme_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon_readme.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtReadme</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:32 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x0B792C54</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>flist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_icon_flist.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtFlist</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:32 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xC5079496</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
</xilinx:generationHistory>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>chipscope_ila</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="chipscope_ila" spirit:version="1.05.a" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">chipscope_ila</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_6">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_7">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_8">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_9">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_10">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_11">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_12">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXAMPLE_DESIGN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_10">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_13">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_14">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_11">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_15">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_12">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_SAME_AS_TRIGGER">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_13">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_16">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_14">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_15">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_16">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_1">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_2">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_3">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_4">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_10">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_5">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_11">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_6">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_12">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_7">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_13">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_8">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_14">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_TYPE_9">basic_with_edges</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_15">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_16">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONSTRAINT_TYPE">external</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUMBER_OF_TRIGGER_PORTS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHECK_BRAMCOUNT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_SAVE_KEEP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SAMPLE_ON">Rising</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_10">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_11">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_12">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_STORAGE_QUALIFICATION">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_13">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_14">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_15">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_16">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_PORT_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRIGGER_OUTPUT_PORT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RPMS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_1">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_2">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_3">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_4">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_5">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_6">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAX_SEQUENCE_LEVELS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_7">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SAMPLE_DATA_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_8">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MATCH_UNITS_9">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_1">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_2">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_3">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_4">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_5">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_6">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_10">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_7">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_11">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_8">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_12">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COUNTER_WIDTH_9">Disabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_5">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_13">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_14">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_15">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_16">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_8">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXCLUDE_FROM_DATA_STORAGE_9">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_1">192</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_2">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_3">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_4">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRIGGER_PORT_WIDTH_5">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M9_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG5_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M15_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TSEQ_STATES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT9_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M4_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG4_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG10">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT10">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG11">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT11">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG12">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M10_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT12">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG14">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT8_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG15">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT14">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M6_TPID">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT15">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M12_TPID">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG3_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STORAGE_QUAL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT7_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M1_TPID">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG2_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT6_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG1_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT5_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG0_WIDTH">192</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT4_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M5_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M11_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONSTRAINT_TYPE">external</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M7_TPID">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M13_TPID">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M0_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT3_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT15_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M2_TPID">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TSEQ_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXAMPLE_DESIGN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT2_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT14_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG15_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT1_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT13_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG14_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MATCH_UNITS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT0_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INV_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT12_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG13_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M6_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M12_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT11_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG12_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M8_TPID">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M14_TPID">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M1_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MCNT10_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG11_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M3_TPID">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG10_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT4">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA10">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT5">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA11">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT6">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA12">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT7">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT8">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA14">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MCNT9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA15">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M7_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG_OUT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M13_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M9_TPID">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPONENT_NAME">chipscope_ila</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M15_TPID">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M2_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XCO_LIST">Component_Name=chipscope_ila;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=false;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=1024;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=192;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M4_TPID">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M10_TPID">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RAM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M8_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M14_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG9_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SRL16_TYPE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M3_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA0">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG8_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M5_TPID">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA4">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA5">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M11_TPID">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA6">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA7">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA8">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIGDATA9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG7_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M0_TPID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG0">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIG6_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG4">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG5">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG6">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG7">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRIG8">0</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc7k410t</xilinx:device>
<xilinx:deviceFamily>kintex7</xilinx:deviceFamily>
<xilinx:package>ffg900</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Structural</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2012-12-18+02:47</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
<xilinx:generationHistory>
<xilinx:fileSet>
<xilinx:name>model_parameter_resolution_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ip_xco_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila.xco</xilinx:name>
<xilinx:userFileType>xco</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:35 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x0DEC4796</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ngc_netlist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila.cdc</xilinx:name>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x4E16DB8C</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.constraints/chipscope_ila.ucf</xilinx:name>
<xilinx:userFileType>ucf</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x519492F6</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.constraints/chipscope_ila.xdc</xilinx:name>
<xilinx:userFileType>xdc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x5F4D4543</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.ncf</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x241A9D00</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.ngc</xilinx:name>
<xilinx:userFileType>ngc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:03 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xF9AB1130</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.ucf</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>ucf</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x519492F6</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.v</xilinx:name>
<xilinx:userFileType>verilog</xilinx:userFileType>
<xilinx:userFileType>verilogSynthesis</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xA04810C9</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.veo</xilinx:name>
<xilinx:userFileType>veo</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x7A023B26</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.xdc</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xdc</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x5F4D4543</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila_xmdf.tcl</xilinx:name>
<xilinx:userFileType>tcl</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:22:35 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xC99E4D94</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>instantiation_template_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>asy_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila.asy</xilinx:name>
<xilinx:userFileType>asy</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:11 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x06B9D438</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>xmdf_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ise_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila.gise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>gise</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:14 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xBAD08DEE</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./chipscope_ila.xise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xise</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:14 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xA4EBD9EE</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>deliver_readme_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila_readme.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtReadme</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:14 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0xBB082617</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>flist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./chipscope_ila_flist.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtFlist</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Wed Jan 23 02:24:14 GMT 2013</xilinx:timeStamp>
<xilinx:checkSum>0x7BFAD8E1</xilinx:checkSum>
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
</xilinx:generationHistory>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc7vx330t</xilinx:device>
<xilinx:deviceFamily>virtex7</xilinx:deviceFamily>
<xilinx:package>ffg1157</xilinx:package>
<xilinx:speedGrade>-3</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>
top/x300/coregen/ddr3_32bit/example_design/par/coregen.cgp
+22
View File
@@ -0,0 +1,22 @@
# Date: Wed Jan 23 02:21:59 2013
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx330t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1157
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: f72a7428
top/x300/coregen/ddr3_32bit/example_design/par/create_ise.sh
Executable
+71
View File
@@ -0,0 +1,71 @@
#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 1.8
# \ \ Application : MIG
# / / Filename : creat_ise.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:12 $
# \ \ / \ Date Created : Tue Sept 21 2010
# \___\/\___\
#
# Device : 7 Series
# Design Name : DDR3 SDRAM
# Purpose : Batch file to run PAR through ISE
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
xtclsh set_ise_prop.tcl
top/x300/coregen/ddr3_32bit/example_design/par/ddr_icon_cg.xco
+48
View File
@@ -0,0 +1,48 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:08:44 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET component_name=ddr_icon
CSET enable_jtag_bufg=true
CSET number_control_ports=5
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: e242b23d
top/x300/coregen/ddr3_32bit/example_design/par/ddr_ila_basic_cg.xco
+131
View File
@@ -0,0 +1,131 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:08:08 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET component_name=ddr_ila_basic
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=32
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
GENERATE
# CRC: 81425beb
top/x300/coregen/ddr3_32bit/example_design/par/ddr_ila_rdpath_cg.xco
+131
View File
@@ -0,0 +1,131 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:08:08 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET component_name=ddr_ila_rdpath
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=1024
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=64
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
GENERATE
# CRC: 81425beb
top/x300/coregen/ddr3_32bit/example_design/par/ddr_ila_wrpath_cg.xco
+131
View File
@@ -0,0 +1,131 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:08:08 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET component_name=ddr_ila_wrpath
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=32
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
GENERATE
# CRC: 81425beb
top/x300/coregen/ddr3_32bit/example_design/par/ddr_vio_async_in_sync_out_cg.xco
+51
View File
@@ -0,0 +1,51 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:09:15 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET asynchronous_input_port_width=128
CSET asynchronous_output_port_width=8
CSET component_name=ddr_vio_async_in_sync_out
CSET enable_asynchronous_input_port=true
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=true
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=128
# END Parameters
GENERATE
# CRC: 59654a2d
top/x300/coregen/ddr3_32bit/example_design/par/ddr_vio_sync_async_out72_cg.xco
+51
View File
@@ -0,0 +1,51 @@
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Tue Aug 11 01:09:15 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
# CSET constraint_type=ucf
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=72
CSET component_name=ddr_vio_sync_async_out72
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=true
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=72
# END Parameters
GENERATE
# CRC: 59654a2d
top/x300/coregen/ddr3_32bit/example_design/par/example_top.bgn
+938
View File
@@ -0,0 +1,938 @@
Release 14.4 - Bitgen P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '7k410t.nph' in environment
/opt/Xilinx/14.4/ISE_DS/ISE/.
"example_top" is an NCD, version 3.2, device xc7k410t, package ffg900, speed
-2
Opened constraints file example_top.pcf.
Tue Jan 22 18:33:42 2013
/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise example_top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 3* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| CclkPin | Pullup* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup* |
+----------------------+----------------------+
| M1Pin | Pullup* |
+----------------------+----------------------+
| M2Pin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| InitPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| OverTempPowerDown | Disable* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| Match_cycle | 2 |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DonePipe | Yes* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| EncryptKeySelect | bbram* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| HKey | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| DCIUpdateMode | AsRequired* |
+----------------------+----------------------+
| ICAP_Select | Auto* |
+----------------------+----------------------+
| ConfigFallback | Disable* |
+----------------------+----------------------+
| SelectMAPAbort | Enable* |
+----------------------+----------------------+
| BPI_page_size | 1* |
+----------------------+----------------------+
| BPI_1st_read_cycle | 1* |
+----------------------+----------------------+
| next_config_addr | None* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| InitSignalsError | Enable* |
+----------------------+----------------------+
| XADCPartialReconfig | Disable* |
+----------------------+----------------------+
| XADCEnhancedLinearity | Off* |
+----------------------+----------------------+
| JTAG_XADC | Enable* |
+----------------------+----------------------+
| Disable_JTAG | No* |
+----------------------+----------------------+
| XADCPowerDown | Disable* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| ExtMasterCclk_en | Disable* |
+----------------------+----------------------+
| BPI_sync_mode | Disable* |
+----------------------+----------------------+
| SPI_32bit_addr | No* |
+----------------------+----------------------+
| SPI_buswidth | 1* |
+----------------------+----------------------+
| SPI_Fall_Edge | No* |
+----------------------+----------------------+
| RevisionSelect | 00* |
+----------------------+----------------------+
| RevisionSelect_tristate | Disable* |
+----------------------+----------------------+
| TIMER_CFG | None* |
+----------------------+----------------------+
| TIMER_USR | None* |
+----------------------+----------------------+
| USR_ACCESS | None* |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from example_top.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_ca
rry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_
carry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_23_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_21_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_25_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_19_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMC_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_ddr3_infrastructure/rst_phaser_ref_sync_r<0>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/rd_data_r<65>> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:2487 - For MMCM_ADV block
u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i, the CLKOUT0_DIVIDE_F programming
of <6.4> is not supported. CLKOUT0_DIVIDE_F will be adjusted to the hardware
granularity of a multiple of 0.125.
WARNING:PhysDesignRules:2245 - The PLLE2_ADV block
<u_ddr3_32bit/u_ddr3_infrastructure/plle2_i> has CLKOUT pins that do not
drive the same kind of BUFFER load. Routing from the different buffer types
will not be phase aligned.
DRC detected 0 errors and 172 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "example_top.bit".
Bitstream generation is complete.
top/x300/coregen/ddr3_32bit/example_design/par/example_top.bit
BIN
View File
Binary file not shown.
top/x300/coregen/ddr3_32bit/example_design/par/example_top.bld
+406
View File
@@ -0,0 +1,406 @@
Release 14.4 ngdbuild P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd ../synth/_ngo -nt timestamp -uc example_top.ucf -p xc7k410t-ffg900-2
example_top.ngc example_top.ngd
Reading NGO file
"/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/exa
mple_design/par/example_top.ngc" ...
Loading design module
"/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/exa
mple_design/par/chipscope_ila.ngc"...
Loading design module
"/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/exa
mple_design/par/chipscope_icon.ngc"...
Applying constraints in
"/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/exa
mple_design/par/chipscope_ila.ncf" to module "chipscope_ila_i0"...
Checking Constraint Associations...
Applying constraints in
"/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/exa
mple_design/par/chipscope_icon.ncf" to module "chipscope_icon_i0"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "example_top.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - TNM : D_CLK was distributed to a DCM but new TNM
constraints were not derived. This TNM is used in the following user groups
or specifications:
<TIMESPEC TS_J_TO_D = FROM "J_CLK" TO "D_CLK" TIG;>
<TIMESPEC TS_D_TO_J = FROM "D_CLK" TO "J_CLK" TIG;>
INFO:ConstraintSystem:178 - TNM 'TNM_sys_clk', used in period specification
'TS_sys_clk', was traced into PLLE2_ADV instance
u_ddr3_32bit/u_ddr3_infrastructure/plle2_i. The following new TNM groups and
period specifications were generated at the PLLE2_ADV output(s):
CLKOUT3: <TIMESPEC TS_u_ddr3_32bit_u_ddr3_infrastructure_pll_clk3 = PERIOD
"u_ddr3_32bit_u_ddr3_infrastructure_pll_clk3" TS_sys_clk / 1.25 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'TNM_sys_clk', used in period specification
'TS_sys_clk', was traced into PLLE2_ADV instance
u_ddr3_32bit/u_ddr3_infrastructure/plle2_i. The following new TNM groups and
period specifications were generated at the PLLE2_ADV output(s):
CLKOUT0: <TIMESPEC TS_u_ddr3_32bit_freq_refclk = PERIOD
"u_ddr3_32bit_freq_refclk" TS_sys_clk / 5 PHASE 1.875 ns HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'TNM_sys_clk', used in period specification
'TS_sys_clk', was traced into PLLE2_ADV instance
u_ddr3_32bit/u_ddr3_infrastructure/plle2_i. The following new TNM groups and
period specifications were generated at the PLLE2_ADV output(s):
CLKOUT1: <TIMESPEC TS_u_ddr3_32bit_mem_refclk = PERIOD
"u_ddr3_32bit_mem_refclk" TS_sys_clk / 5 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'TNM_sys_clk', used in period specification
'TS_sys_clk', was traced into PLLE2_ADV instance
u_ddr3_32bit/u_ddr3_infrastructure/plle2_i. The following new TNM groups and
period specifications were generated at the PLLE2_ADV output(s):
CLKOUT5: <TIMESPEC TS_u_ddr3_32bit_clk_ref_i = PERIOD
"u_ddr3_32bit_clk_ref_i" TS_sys_clk / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'TNM_sys_clk', used in period specification
'TS_sys_clk', was traced into PLLE2_ADV instance
u_ddr3_32bit/u_ddr3_infrastructure/plle2_i. The following new TNM groups and
period specifications were generated at the PLLE2_ADV output(s):
CLKOUT2: <TIMESPEC TS_u_ddr3_32bit_sync_pulse = PERIOD
"u_ddr3_32bit_sync_pulse" TS_sys_clk / 0.3125 PHASE 0.875 ns HIGH 6.25%>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_u_ddr3_infrastructure_pll_clk3',
used in period specification
'TS_u_ddr3_32bit_u_ddr3_infrastructure_pll_clk3', was traced into MMCME2_ADV
instance u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i. The following new TNM
groups and period specifications were generated at the MMCME2_ADV output(s):
CLKFBOUT: <TIMESPEC TS_u_ddr3_32bit_u_ddr3_infrastructure_clk_pll_i = PERIOD
"u_ddr3_32bit_u_ddr3_infrastructure_clk_pll_i"
TS_u_ddr3_32bit_u_ddr3_infrastructure_pll_clk3 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
A.ddr_byte_lane_A/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_A_ddr_byte_lane_A_iserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
A.ddr_byte_lane_A/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_A_ddr_byte_lane_A_iserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_iserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_iserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_iserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_iserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_iserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_freq_refclk', used in period
specification 'TS_u_ddr3_32bit_freq_refclk', was traced into PHASER_IN_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_in_gen.phaser_in. The following new TNM groups and
period specifications were generated at the PHASER_IN_PHY output(s):
ICLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_iserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
A.ddr_byte_lane_A/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_A_ddr_byte_lane_A_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
A.ddr_byte_lane_A/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_A_ddr_byte_lane_A_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
D.ddr_byte_lane_D/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_D_ddr_byte_lane_D_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
C.ddr_byte_lane_C/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_C_ddr_byte_lane_C_oserdes_clkdi...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLK: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_oserdes_clk =...>
INFO:ConstraintSystem:178 - TNM 'u_ddr3_32bit_mem_refclk', used in period
specification 'TS_u_ddr3_32bit_mem_refclk', was traced into PHASER_OUT_PHY
instance
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr
_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_
B.ddr_byte_lane_B/phaser_out. The following new TNM groups and period
specifications were generated at the PHASER_OUT_PHY output(s):
OCLKDIV: <TIMESPEC
TS_u_ddr3_32bit_u_mig_7series_v1_8_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_
ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_la
ne_B_ddr_byte_lane_B_oserdes_clkdi...>
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N1266' has no driver
WARNING:NgdBuild:452 - logical net 'N1267' has no driver
WARNING:NgdBuild:452 - logical net 'N1268' has no driver
WARNING:NgdBuild:452 - logical net 'N1269' has no driver
WARNING:NgdBuild:452 - logical net 'N1270' has no driver
WARNING:NgdBuild:452 - logical net 'N1271' has no driver
WARNING:NgdBuild:452 - logical net 'N1272' has no driver
WARNING:NgdBuild:452 - logical net 'N1273' has no driver
WARNING:NgdBuild:452 - logical net 'N1274' has no driver
WARNING:NgdBuild:452 - logical net 'N1275' has no driver
WARNING:NgdBuild:452 - logical net 'N1276' has no driver
WARNING:NgdBuild:452 - logical net 'N1277' has no driver
WARNING:NgdBuild:452 - logical net 'N1278' has no driver
WARNING:NgdBuild:452 - logical net 'N1279' has no driver
WARNING:NgdBuild:452 - logical net 'N1280' has no driver
WARNING:NgdBuild:452 - logical net 'N1281' has no driver
WARNING:NgdBuild:452 - logical net 'N1282' has no driver
WARNING:NgdBuild:452 - logical net 'N1283' has no driver
WARNING:NgdBuild:452 - logical net 'N1284' has no driver
WARNING:NgdBuild:452 - logical net 'N1285' has no driver
WARNING:NgdBuild:452 - logical net 'N1286' has no driver
WARNING:NgdBuild:452 - logical net 'N1287' has no driver
WARNING:NgdBuild:452 - logical net 'N1288' has no driver
WARNING:NgdBuild:452 - logical net 'N1289' has no driver
WARNING:NgdBuild:452 - logical net 'N1290' has no driver
WARNING:NgdBuild:452 - logical net 'N1291' has no driver
WARNING:NgdBuild:452 - logical net 'N1292' has no driver
WARNING:NgdBuild:452 - logical net 'N1293' has no driver
WARNING:NgdBuild:452 - logical net 'N1294' has no driver
WARNING:NgdBuild:452 - logical net 'N1295' has no driver
WARNING:NgdBuild:452 - logical net 'N1296' has no driver
WARNING:NgdBuild:452 - logical net 'N1297' has no driver
WARNING:NgdBuild:452 - logical net 'N1298' has no driver
WARNING:NgdBuild:452 - logical net 'N1299' has no driver
WARNING:NgdBuild:452 - logical net 'N1300' has no driver
WARNING:NgdBuild:452 - logical net 'N1301' has no driver
WARNING:NgdBuild:452 - logical net 'N1302' has no driver
WARNING:NgdBuild:452 - logical net 'N1303' has no driver
WARNING:NgdBuild:452 - logical net 'N1304' has no driver
WARNING:NgdBuild:452 - logical net 'N1305' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 41
Total memory usage is 597360 kilobytes
Writing NGD file "example_top.ngd" ...
Total REAL time to NGDBUILD completion: 43 sec
Total CPU time to NGDBUILD completion: 42 sec
Writing NGDBUILD log file "example_top.bld"...
top/x300/coregen/ddr3_32bit/example_design/par/example_top.cdc
+1805
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.cpj
+18859
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.drc
+793
View File
@@ -0,0 +1,793 @@
Release 14.4 Drc P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Tue Jan 22 18:33:42 2013
drc -z example_top.ncd example_top.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_ca
rry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_
carry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_23_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_21_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_25_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_19_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMC_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_ddr3_infrastructure/rst_phaser_ref_sync_r<0>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/rd_data_r<65>> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:2487 - For MMCM_ADV block
u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i, the CLKOUT0_DIVIDE_F programming
of <6.4> is not supported. CLKOUT0_DIVIDE_F will be adjusted to the hardware
granularity of a multiple of 0.125.
WARNING:PhysDesignRules:2245 - The PLLE2_ADV block
<u_ddr3_32bit/u_ddr3_infrastructure/plle2_i> has CLKOUT pins that do not
drive the same kind of BUFFER load. Routing from the different buffer types
will not be phase aligned.
DRC detected 0 errors and 172 warnings. Please see the previously displayed
individual error or warning messages for more details.
top/x300/coregen/ddr3_32bit/example_design/par/example_top.ncd
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top.ngc
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top.ngd
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top.pad
+931
View File
@@ -0,0 +1,931 @@
Release 14.4 - par P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Tue Jan 22 18:32:42 2013
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: example_top_map.ncd
OUTPUT FILE: example_top.pad
PART TYPE: xc7k410t
SPEED GRADE: -2
PACKAGE: ffg900
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
A1|||GND||||||||||||
A2|||GND||||||||||||
A3||OPAD|MGTXTXN3_118|UNUSED|||||||||||
A4||OPAD|MGTXTXP3_118|UNUSED|||||||||||
A5|||GND||||||||||||
A6|||GND||||||||||||
A7||IPAD|MGTXRXN3_118|UNUSED|||||||||||
A8||IPAD|MGTXRXP3_118|UNUSED|||||||||||
A9|||GND||||||||||||
A10|||INIT_B_0||||||||||||
A11||IOB33M|IO_L17P_T2_18|UNUSED||18|||||||||
A12||IOB33S|IO_L17N_T2_18|UNUSED||18|||||||||
A13||IOB33S|IO_L22N_T3_18|UNUSED||18|||||||||
A14|||GND||||||||||||
A15||IOB33S|IO_L24N_T3_18|UNUSED||18|||||||||
A16||IOB33M|IO_L20P_T3_17|UNUSED||17|||||||||
A17||IOB33S|IO_L20N_T3_17|UNUSED||17|||||||||
A18||IOB33S|IO_L22N_T3_17|UNUSED||17|||||||||
A19|||VCCO_17|||17|||||any******||||
A20||IOB33M|IO_L21P_T3_DQS_17|UNUSED||17|||||||||
A21||IOB33S|IO_L21N_T3_DQS_17|UNUSED||17|||||||||
A22||IOB33S|IO_L23N_T3_17|UNUSED||17|||||||||
A23||IOB33S|IO_L1N_T0_16|UNUSED||16|||||||||
A24|||GND||||||||||||
A25||IOB33M|IO_L10P_T1_16|UNUSED||16|||||||||
A26||IOB33S|IO_L10N_T1_16|UNUSED||16|||||||||
A27||IOB33S|IO_L7N_T1_16|UNUSED||16|||||||||
A28||IOB33S|IO_L9N_T1_DQS_16|UNUSED||16|||||||||
A29|||VCCO_16|||16|||||any******||||
A30||IOB33S|IO_L17N_T2_16|UNUSED||16|||||||||
AA1|||GND||||||||||||
AA2|||GND||||||||||||
AA3||IPAD|MGTXRXN0_115|UNUSED|||||||||||
AA4||IPAD|MGTXRXP0_115|UNUSED|||||||||||
AA5|||GND||||||||||||
AA6|||GND||||||||||||
AA7|||GND||||||||||||
AA8|ddr3_addr<12>|IOB18|IO_L2P_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AA9|||VCCO_33|||33|||||1.50||||
AA10|ddr3_addr<7>|IOB18|IO_L5N_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AA11|ddr3_addr<8>|IOB18|IO_L5P_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AA12|ddr3_addr<14>|IOB18|IO_L1P_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AA13|ddr3_addr<6>|IOB18|IO_L6P_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AA14|||GND||||||||||||
AA15||IOB18M|IO_L20P_T3_32|UNUSED||32|||||||||
AA16||IOB18S|IO_L23N_T3_32|UNUSED||32|||||||||
AA17||IOB18M|IO_L23P_T3_32|UNUSED||32|||||||||
AA18||IOB18M|IO_L16P_T2_32|UNUSED||32|||||||||
AA19|||VCCO_32|||32|||||any******||||
AA20||IOB33M|IO_L6P_T0_12|UNUSED||12|||||||||
AA21||IOB33S|IO_L2N_T0_12|UNUSED||12|||||||||
AA22||IOB33M|IO_L4P_T0_12|UNUSED||12|||||||||
AA23||IOB33S|IO_L4N_T0_12|UNUSED||12|||||||||
AA24|||GND||||||||||||
AA25||IOB33M|IO_L6P_T0_13|UNUSED||13|||||||||
AA26||IOB33S|IO_L1N_T0_13|UNUSED||13|||||||||
AA27||IOB33M|IO_L5P_T0_13|UNUSED||13|||||||||
AA28||IOB33S|IO_L3N_T0_DQS_13|UNUSED||13|||||||||
AA29|||VCCO_13|||13|||||3.30||||
AA30|init_calib_complete|IOB33|IO_L8N_T1_13|OUTPUT|LVCMOS33|13|12|SLOW||||LOCATED|NO|NONE|
AB1|||M2_0||||||||||||
AB2|||M1_0||||||||||||
AB3|||GND||||||||||||
AB4|||GND||||||||||||
AB5|||M0_0||||||||||||
AB6|||VCCO_0|||0|||||any******||||
AB7||IOB18|IO_25_VRP_34|Termination Required||34|||TERMINATION||||||
AB8|ddr3_addr<11>|IOB18|IO_L2N_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AB9|ddr3_ck_p<0>|IOB18M|IO_L3P_T0_DQS_33|OUTPUT|DIFF_SSTL15|33||FAST||||LOCATED|YES|NONE|
AB10|ddr3_addr<4>|IOB18|IO_L7P_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AB11|||GND||||||||||||
AB12|ddr3_addr<13>|IOB18|IO_L1N_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AB13|ddr3_addr<5>|IOB18|IO_L6N_T0_VREF_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AB14||IOB18|IO_25_VRP_32|UNUSED||32|||||||||
AB15||IOB18S|IO_L20N_T3_32|UNUSED||32|||||||||
AB16|||VCCO_32|||32|||||any******||||
AB17||IOB18M|IO_L18P_T2_32|UNUSED||32|||||||||
AB18||IOB18S|IO_L16N_T2_32|UNUSED||32|||||||||
AB19||IOB18M|IO_L17P_T2_32|UNUSED||32|||||||||
AB20||IOB33S|IO_L6N_T0_VREF_12|UNUSED||12|||||||||
AB21|||GND||||||||||||
AB22||IOB33M|IO_L3P_T0_DQS_12|UNUSED||12|||||||||
AB23||IOB33S|IO_L3N_T0_DQS_12|UNUSED||12|||||||||
AB24||IOB33M|IO_L7P_T1_12|UNUSED||12|||||||||
AB25||IOB33S|IO_L6N_T0_VREF_13|UNUSED||13|||||||||
AB26|||VCCO_13|||13|||||3.30||||
AB27||IOB33M|IO_L12P_T1_MRCC_13|UNUSED||13|||||||||
AB28||IOB33S|IO_L5N_T0_13|UNUSED||13|||||||||
AB29||IOB33M|IO_L10P_T1_13|UNUSED||13|||||||||
AB30||IOB33S|IO_L10N_T1_13|UNUSED||13|||||||||
AC1|ddr3_dq<2>|IOB18|IO_L2N_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AC2|ddr3_dq<1>|IOB18|IO_L2P_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AC3|||VCCO_34|||34|||||1.50||||
AC4|ddr3_dq<4>|IOB18|IO_L4N_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AC5|ddr3_dq<3>|IOB18|IO_L4P_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AC6||IOB18|IO_0_VRN_34|Termination Required||34|||TERMINATION||||||
AC7|ddr3_dq<7>|IOB18|IO_L6P_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AC8|||GND||||||||||||
AC9|ddr3_ck_n<0>|IOB18S|IO_L3N_T0_DQS_33|OUTPUT|DIFF_SSTL15|33||FAST||||LOCATED|YES|NONE|
AC10|ddr3_addr<3>|IOB18|IO_L7N_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AC11|ddr3_ba<2>|IOB18|IO_L9N_T1_DQS_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AC12|ddr3_addr<0>|IOB18|IO_L9P_T1_DQS_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AC13|||VCCO_33|||33|||||1.50||||
AC14||IOB18M|IO_L22P_T3_32|UNUSED||32|||||||||
AC15||IOB18S|IO_L21N_T3_DQS_32|UNUSED||32|||||||||
AC16||IOB18M|IO_L21P_T3_DQS_32|UNUSED||32|||||||||
AC17||IOB18S|IO_L18N_T2_32|UNUSED||32|||||||||
AC18|||GND||||||||||||
AC19||IOB18S|IO_L17N_T2_32|UNUSED||32|||||||||
AC20||IOB33M|IO_L5P_T0_12|UNUSED||12|||||||||
AC21||IOB33S|IO_L5N_T0_12|UNUSED||12|||||||||
AC22||IOB33M|IO_L8P_T1_12|UNUSED||12|||||||||
AC23|||VCCO_12|||12|||||any******||||
AC24||IOB33M|IO_L9P_T1_DQS_12|UNUSED||12|||||||||
AC25||IOB33S|IO_L7N_T1_12|UNUSED||12|||||||||
AC26||IOB33M|IO_L19P_T3_13|UNUSED||13|||||||||
AC27||IOB33S|IO_L12N_T1_MRCC_13|UNUSED||13|||||||||
AC28|||GND||||||||||||
AC29|sys_rst|IOB33|IO_L7P_T1_13|INPUT|LVCMOS33|13|||PULLUP|NONE||LOCATED|NO|NONE|
AC30||IOB33S|IO_L7N_T1_13|UNUSED||13|||||||||
AD1|ddr3_dqs_n<0>|IOB18S|IO_L3N_T0_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AD2|ddr3_dqs_p<0>|IOB18M|IO_L3P_T0_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AD3|ddr3_dq<0>|IOB18|IO_L1N_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AD4|ddr3_dm<0>|IOB18|IO_L1P_T0_34|TRISTATE|SSTL15|34||FAST||||LOCATED|NO|NONE|
AD5|||GND||||||||||||
AD6|ddr3_dq<5>|IOB18|IO_L5P_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AD7||IOB18S|IO_L6N_T0_VREF_34|VREF Required||34|||||0.75||||
AD8|ddr3_addr<2>|IOB18|IO_L8P_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AD9|ddr3_ba<1>|IOB18|IO_L10P_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AD10|||VCCO_33|||33|||||1.50||||
AD11|ddr3_cs_n<0>|IOB18|IO_L12N_T1_MRCC_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AD12|ddr3_we_n|IOB18|IO_L12P_T1_MRCC_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AD13||IOB18|IO_25_VRP_33|UNUSED||33|||||||||
AD14||IOB18S|IO_L22N_T3_32|UNUSED||32|||||||||
AD15|||GND||||||||||||
AD16||IOB18S|IO_L14N_T2_SRCC_32|UNUSED||32|||||||||
AD17||IOB18M|IO_L14P_T2_SRCC_32|UNUSED||32|||||||||
AD18||IOB18M|IO_L13P_T2_MRCC_32|UNUSED||32|||||||||
AD19||IOB18M|IO_L10P_T1_32|UNUSED||32|||||||||
AD20|||VCCO_12|||12|||||any******||||
AD21||IOB33M|IO_L10P_T1_12|UNUSED||12|||||||||
AD22||IOB33S|IO_L8N_T1_12|UNUSED||12|||||||||
AD23||IOB33M|IO_L12P_T1_MRCC_12|UNUSED||12|||||||||
AD24||IOB33S|IO_L9N_T1_DQS_12|UNUSED||12|||||||||
AD25|||GND||||||||||||
AD26||IOB33S|IO_L19N_T3_VREF_13|UNUSED||13|||||||||
AD27||IOB33M|IO_L11P_T1_SRCC_13|UNUSED||13|||||||||
AD28||IOB33S|IO_L11N_T1_SRCC_13|UNUSED||13|||||||||
AD29||IOB33M|IO_L9P_T1_DQS_13|UNUSED||13|||||||||
AD30|||VCCO_13|||13|||||3.30||||
AE1|ddr3_dq<9>|IOB18|IO_L8P_T1_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AE2|||GND||||||||||||
AE3|ddr3_dq<12>|IOB18|IO_L10N_T1_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AE4|ddr3_dq<11>|IOB18|IO_L10P_T1_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AE5|ddr3_dq<13>|IOB18|IO_L11P_T1_SRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AE6|ddr3_dq<6>|IOB18|IO_L5N_T0_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AE7|||VCCO_34|||34|||||1.50||||
AE8|ddr3_addr<1>|IOB18|IO_L8N_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AE9|ddr3_ba<0>|IOB18|IO_L10N_T1_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AE10|sys_clk_i|IOB18|IO_L14P_T2_SRCC_33|INPUT|LVCMOS15|33||||NONE||LOCATED|NO|NONE|
AE11|ddr3_ras_n|IOB18|IO_L11P_T1_SRCC_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AE12|||GND||||||||||||
AE13||IOB18M|IO_L19P_T3_33|UNUSED||33|||||||||
AE14||IOB18S|IO_L19N_T3_VREF_32|UNUSED||32|||||||||
AE15||IOB18M|IO_L19P_T3_32|UNUSED||32|||||||||
AE16||IOB18M|IO_L6P_T0_32|UNUSED||32|||||||||
AE17|||VCCO_32|||32|||||any******||||
AE18||IOB18S|IO_L13N_T2_MRCC_32|UNUSED||32|||||||||
AE19||IOB18S|IO_L10N_T1_32|UNUSED||32|||||||||
AE20||IOB33|IO_25_12|UNUSED||12|||||||||
AE21||IOB33S|IO_L10N_T1_12|UNUSED||12|||||||||
AE22|||GND||||||||||||
AE23||IOB33M|IO_L11P_T1_SRCC_12|UNUSED||12|||||||||
AE24||IOB33S|IO_L12N_T1_MRCC_12|UNUSED||12|||||||||
AE25||IOB33M|IO_L16P_T2_12|UNUSED||12|||||||||
AE26||IOB33|IO_25_13|UNUSED||13|||||||||
AE27|||VCCO_13|||13|||||3.30||||
AE28||IOB33M|IO_L14P_T2_SRCC_13|UNUSED||13|||||||||
AE29||IOB33S|IO_L9N_T1_DQS_13|UNUSED||13|||||||||
AE30||IOB33M|IO_L16P_T2_13|UNUSED||13|||||||||
AF1|ddr3_dq<10>|IOB18|IO_L8N_T1_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AF2|ddr3_dq<8>|IOB18|IO_L7N_T1_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AF3|ddr3_dm<1>|IOB18|IO_L7P_T1_34|TRISTATE|SSTL15|34||FAST||||LOCATED|NO|NONE|
AF4|||VCCO_34|||34|||||1.50||||
AF5|ddr3_dq<14>|IOB18|IO_L11N_T1_SRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AF6|ddr3_dq<15>|IOB18|IO_L12P_T1_MRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AF7|ddr3_dq<24>|IOB18|IO_L20P_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AF8|ddr3_dm<3>|IOB18|IO_L19P_T3_34|TRISTATE|SSTL15|34||FAST||||LOCATED|NO|NONE|
AF9|||GND||||||||||||
AF10||IOB18S|IO_L14N_T2_SRCC_33|UNUSED||33|||||||||
AF11|ddr3_cas_n|IOB18|IO_L11N_T1_SRCC_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AF12||IOB18M|IO_L23P_T3_33|UNUSED||33|||||||||
AF13||IOB18S|IO_L19N_T3_VREF_33|UNUSED||33|||||||||
AF14|||VCCO_32|||32|||||any******||||
AF15||IOB18M|IO_L4P_T0_32|UNUSED||32|||||||||
AF16||IOB18S|IO_L6N_T0_VREF_32|UNUSED||32|||||||||
AF17||IOB18M|IO_L12P_T1_MRCC_32|UNUSED||32|||||||||
AF18||IOB18M|IO_L11P_T1_SRCC_32|UNUSED||32|||||||||
AF19|||GND||||||||||||
AF20||IOB33M|IO_L19P_T3_12|UNUSED||12|||||||||
AF21||IOB33S|IO_L19N_T3_VREF_12|UNUSED||12|||||||||
AF22||IOB33M|IO_L13P_T2_MRCC_12|UNUSED||12|||||||||
AF23||IOB33S|IO_L11N_T1_SRCC_12|UNUSED||12|||||||||
AF24|||VCCO_12|||12|||||any******||||
AF25||IOB33S|IO_L16N_T2_12|UNUSED||12|||||||||
AF26||IOB33M|IO_L23P_T3_13|UNUSED||13|||||||||
AF27||IOB33S|IO_L23N_T3_13|UNUSED||13|||||||||
AF28||IOB33S|IO_L14N_T2_SRCC_13|UNUSED||13|||||||||
AF29|||GND||||||||||||
AF30||IOB33S|IO_L16N_T2_13|UNUSED||13|||||||||
AG1|||VCCO_34|||34|||||1.50||||
AG2|ddr3_dqs_p<2>|IOB18M|IO_L15P_T2_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AG3|ddr3_dqs_n<1>|IOB18S|IO_L9N_T1_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AG4|ddr3_dqs_p<1>|IOB18M|IO_L9P_T1_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AG5|ddr3_reset_n|IOB18|IO_L12N_T1_MRCC_34|OUTPUT|LVCMOS15|34|12|FAST||||LOCATED|NO|NONE|
AG6|||GND||||||||||||
AG7|ddr3_dq<25>|IOB18|IO_L20N_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AG8||IOB18S|IO_L19N_T3_VREF_34|VREF Required||34|||||0.75||||
AG9||IOB18M|IO_L16P_T2_33|UNUSED||33|||||||||
AG10||IOB18M|IO_L13P_T2_MRCC_33|UNUSED||33|||||||||
AG11|||VCCO_33|||33|||||1.50||||
AG12||IOB18S|IO_L23N_T3_33|UNUSED||33|||||||||
AG13||IOB18M|IO_L24P_T3_33|UNUSED||33|||||||||
AG14||IOB18S|IO_L4N_T0_32|UNUSED||32|||||||||
AG15||IOB18M|IO_L2P_T0_32|UNUSED||32|||||||||
AG16|||GND||||||||||||
AG17||IOB18S|IO_L12N_T1_MRCC_32|UNUSED||32|||||||||
AG18||IOB18S|IO_L11N_T1_SRCC_32|UNUSED||32|||||||||
AG19||IOB18M|IO_L8P_T1_32|UNUSED||32|||||||||
AG20||IOB33M|IO_L22P_T3_12|UNUSED||12|||||||||
AG21|||VCCO_12|||12|||||any******||||
AG22||IOB33M|IO_L20P_T3_12|UNUSED||12|||||||||
AG23||IOB33S|IO_L13N_T2_MRCC_12|UNUSED||12|||||||||
AG24||IOB33M|IO_L14P_T2_SRCC_12|UNUSED||12|||||||||
AG25||IOB33M|IO_L18P_T2_12|UNUSED||12|||||||||
AG26|||GND||||||||||||
AG27||IOB33M|IO_L21P_T3_DQS_13|UNUSED||13|||||||||
AG28||IOB33S|IO_L21N_T3_DQS_13|UNUSED||13|||||||||
AG29||IOB33M|IO_L13P_T2_MRCC_13|UNUSED||13|||||||||
AG30||IOB33M|IO_L18P_T2_13|UNUSED||13|||||||||
AH1|ddr3_dqs_n<2>|IOB18S|IO_L15N_T2_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AH2|ddr3_dq<19>|IOB18|IO_L16P_T2_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AH3|||GND||||||||||||
AH4|ddr3_dm<2>|IOB18|IO_L13P_T2_MRCC_34|TRISTATE|SSTL15|34||FAST||||LOCATED|NO|NONE|
AH5|ddr3_dq<18>|IOB18|IO_L14N_T2_SRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AH6|ddr3_dq<17>|IOB18|IO_L14P_T2_SRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AH7|ddr3_dqs_p<3>|IOB18M|IO_L21P_T3_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AH8|||VCCO_34|||34|||||1.50||||
AH9||IOB18S|IO_L16N_T2_33|UNUSED||33|||||||||
AH10||IOB18S|IO_L13N_T2_MRCC_33|UNUSED||33|||||||||
AH11||IOB18M|IO_L18P_T2_33|UNUSED||33|||||||||
AH12||IOB18S|IO_L24N_T3_33|UNUSED||33|||||||||
AH13|||GND||||||||||||
AH14||IOB18M|IO_L21P_T3_DQS_33|UNUSED||33|||||||||
AH15||IOB18S|IO_L2N_T0_32|UNUSED||32|||||||||
AH16||IOB18M|IO_L3P_T0_DQS_32|UNUSED||32|||||||||
AH17||IOB18M|IO_L5P_T0_32|UNUSED||32|||||||||
AH18|||VCCO_32|||32|||||any******||||
AH19||IOB18S|IO_L8N_T1_32|UNUSED||32|||||||||
AH20||IOB33S|IO_L22N_T3_12|UNUSED||12|||||||||
AH21||IOB33M|IO_L23P_T3_12|UNUSED||12|||||||||
AH22||IOB33S|IO_L20N_T3_12|UNUSED||12|||||||||
AH23|||GND||||||||||||
AH24||IOB33S|IO_L14N_T2_SRCC_12|UNUSED||12|||||||||
AH25||IOB33S|IO_L18N_T2_12|UNUSED||12|||||||||
AH26||IOB33M|IO_L22P_T3_13|UNUSED||13|||||||||
AH27||IOB33S|IO_L22N_T3_13|UNUSED||13|||||||||
AH28|||VCCO_13|||13|||||3.30||||
AH29||IOB33S|IO_L13N_T2_MRCC_13|UNUSED||13|||||||||
AH30||IOB33S|IO_L18N_T2_13|UNUSED||13|||||||||
AJ1|ddr3_dq<21>|IOB18|IO_L17P_T2_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ2|ddr3_dq<20>|IOB18|IO_L16N_T2_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ3|ddr3_dq<23>|IOB18|IO_L18P_T2_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ4|ddr3_dq<16>|IOB18|IO_L13N_T2_MRCC_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ5|||VCCO_34|||34|||||1.50||||
AJ6|ddr3_dq<26>|IOB18|IO_L22P_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ7|ddr3_dqs_n<3>|IOB18S|IO_L21N_T3_DQS_34|BIDIR|DIFF_SSTL15_T_DCI|34||FAST||NONE||LOCATED|YES|SPLIT|
AJ8|ddr3_dq<28>|IOB18|IO_L23P_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AJ9|ddr3_cke<0>|IOB18|IO_L15P_T2_DQS_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AJ10|||GND||||||||||||
AJ11||IOB18S|IO_L18N_T2_33|UNUSED||33|||||||||
AJ12||IOB18S|IO_L22N_T3_33|UNUSED||33|||||||||
AJ13||IOB18M|IO_L22P_T3_33|UNUSED||33|||||||||
AJ14||IOB18S|IO_L21N_T3_DQS_33|UNUSED||33|||||||||
AJ15|||VCCO_32|||32|||||any******||||
AJ16||IOB18S|IO_L3N_T0_DQS_32|UNUSED||32|||||||||
AJ17||IOB18S|IO_L5N_T0_32|UNUSED||32|||||||||
AJ18||IOB18M|IO_L9P_T1_DQS_32|UNUSED||32|||||||||
AJ19||IOB18M|IO_L7P_T1_32|UNUSED||32|||||||||
AJ20|||GND||||||||||||
AJ21||IOB33S|IO_L23N_T3_12|UNUSED||12|||||||||
AJ22||IOB33M|IO_L21P_T3_DQS_12|UNUSED||12|||||||||
AJ23||IOB33S|IO_L21N_T3_DQS_12|UNUSED||12|||||||||
AJ24||IOB33M|IO_L15P_T2_DQS_12|UNUSED||12|||||||||
AJ25|||VCCO_13|||13|||||3.30||||
AJ26||IOB33M|IO_L24P_T3_13|UNUSED||13|||||||||
AJ27||IOB33M|IO_L20P_T3_13|UNUSED||13|||||||||
AJ28||IOB33M|IO_L17P_T2_13|UNUSED||13|||||||||
AJ29||IOB33S|IO_L17N_T2_13|UNUSED||13|||||||||
AJ30|||GND||||||||||||
AK1|ddr3_dq<22>|IOB18|IO_L17N_T2_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AK2|||VCCO_34|||34|||||1.50||||
AK3||IOB18S|IO_L18N_T2_34|UNUSED||34|||||||||
AK4|ddr3_dq<31>|IOB18|IO_L24N_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AK5|ddr3_dq<30>|IOB18|IO_L24P_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AK6|ddr3_dq<27>|IOB18|IO_L22N_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AK7|||GND||||||||||||
AK8|ddr3_dq<29>|IOB18|IO_L23N_T3_34|BIDIR|SSTL15_T_DCI|34||FAST||NONE||LOCATED|NO|SPLIT|
AK9|ddr3_odt<0>|IOB18|IO_L15N_T2_DQS_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
AK10||IOB18S|IO_L17N_T2_33|UNUSED||33|||||||||
AK11||IOB18M|IO_L17P_T2_33|UNUSED||33|||||||||
AK12|||VCCO_33|||33|||||1.50||||
AK13||IOB18S|IO_L20N_T3_33|UNUSED||33|||||||||
AK14||IOB18M|IO_L20P_T3_33|UNUSED||33|||||||||
AK15||IOB18S|IO_L1N_T0_32|UNUSED||32|||||||||
AK16||IOB18M|IO_L1P_T0_32|UNUSED||32|||||||||
AK17|||GND||||||||||||
AK18||IOB18S|IO_L9N_T1_DQS_32|UNUSED||32|||||||||
AK19||IOB18S|IO_L7N_T1_32|UNUSED||32|||||||||
AK20||IOB33M|IO_L24P_T3_12|UNUSED||12|||||||||
AK21||IOB33S|IO_L24N_T3_12|UNUSED||12|||||||||
AK22|||VCCO_12|||12|||||any******||||
AK23||IOB33M|IO_L17P_T2_12|UNUSED||12|||||||||
AK24||IOB33S|IO_L17N_T2_12|UNUSED||12|||||||||
AK25||IOB33S|IO_L15N_T2_DQS_12|UNUSED||12|||||||||
AK26||IOB33S|IO_L24N_T3_13|UNUSED||13|||||||||
AK27|||GND||||||||||||
AK28||IOB33S|IO_L20N_T3_13|UNUSED||13|||||||||
AK29||IOB33M|IO_L15P_T2_DQS_13|UNUSED||13|||||||||
AK30||IOB33S|IO_L15N_T2_DQS_13|UNUSED||13|||||||||
B1||OPAD|MGTXTXN2_118|UNUSED|||||||||||
B2||OPAD|MGTXTXP2_118|UNUSED|||||||||||
B3|||MGTAVTT||||||||||||
B4|||GND||||||||||||
B5||IPAD|MGTXRXN2_118|UNUSED|||||||||||
B6||IPAD|MGTXRXP2_118|UNUSED|||||||||||
B7|||MGTAVCC||||||||||||
B8|||GND||||||||||||
B9|||GND||||||||||||
B10|||CCLK_0||||||||||||
B11|||GND||||||||||||
B12||IOB33S|IO_L15N_T2_DQS_18|UNUSED||18|||||||||
B13||IOB33M|IO_L22P_T3_18|UNUSED||18|||||||||
B14||IOB33M|IO_L24P_T3_18|UNUSED||18|||||||||
B15||IOB33S|IO_L23N_T3_18|UNUSED||18|||||||||
B16|||VCCO_17|||17|||||any******||||
B17||IOB33S|IO_L17N_T2_17|UNUSED||17|||||||||
B18||IOB33M|IO_L22P_T3_17|UNUSED||17|||||||||
B19||IOB33S|IO_L24N_T3_17|UNUSED||17|||||||||
B20||IOB33S|IO_L19N_T3_VREF_17|UNUSED||17|||||||||
B21|||GND||||||||||||
B22||IOB33M|IO_L23P_T3_17|UNUSED||17|||||||||
B23||IOB33M|IO_L1P_T0_16|UNUSED||16|||||||||
B24||IOB33S|IO_L8N_T1_16|UNUSED||16|||||||||
B25||IOB33S|IO_L12N_T1_MRCC_16|UNUSED||16|||||||||
B26|||VCCO_16|||16|||||any******||||
B27||IOB33M|IO_L7P_T1_16|UNUSED||16|||||||||
B28||IOB33M|IO_L9P_T1_DQS_16|UNUSED||16|||||||||
B29||IOB33S|IO_L15N_T2_DQS_16|UNUSED||16|||||||||
B30||IOB33M|IO_L17P_T2_16|UNUSED||16|||||||||
C1|||GND||||||||||||
C2|||GND||||||||||||
C3||OPAD|MGTXTXN1_118|UNUSED|||||||||||
C4||OPAD|MGTXTXP1_118|UNUSED|||||||||||
C5|||MGTAVTT||||||||||||
C6|||GND||||||||||||
C7||IPAD|MGTREFCLK0N_118|UNUSED|||||||||||
C8||IPAD|MGTREFCLK0P_118|UNUSED|||||||||||
C9|||GND||||||||||||
C10|||VCCBATT_0||||||||||||
C11||IOB33S|IO_L18N_T2_18|UNUSED||18|||||||||
C12||IOB33M|IO_L15P_T2_DQS_18|UNUSED||18|||||||||
C13|||VCCO_18|||18|||||any******||||
C14||IOB33S|IO_L21N_T3_DQS_18|UNUSED||18|||||||||
C15||IOB33M|IO_L23P_T3_18|UNUSED||18|||||||||
C16||IOB33S|IO_L15N_T2_DQS_17|UNUSED||17|||||||||
C17||IOB33M|IO_L17P_T2_17|UNUSED||17|||||||||
C18|||GND||||||||||||
C19||IOB33M|IO_L24P_T3_17|UNUSED||17|||||||||
C20||IOB33M|IO_L19P_T3_17|UNUSED||17|||||||||
C21||IOB33S|IO_L8N_T1_17|UNUSED||17|||||||||
C22||IOB33S|IO_L10N_T1_17|UNUSED||17|||||||||
C23|||VCCO_16|||16|||||any******||||
C24||IOB33M|IO_L8P_T1_16|UNUSED||16|||||||||
C25||IOB33M|IO_L12P_T1_MRCC_16|UNUSED||16|||||||||
C26||IOB33S|IO_L11N_T1_SRCC_16|UNUSED||16|||||||||
C27||IOB33S|IO_L13N_T2_MRCC_16|UNUSED||16|||||||||
C28|||GND||||||||||||
C29||IOB33M|IO_L15P_T2_DQS_16|UNUSED||16|||||||||
C30||IOB33S|IO_L16N_T2_16|UNUSED||16|||||||||
D1||OPAD|MGTXTXN0_118|UNUSED|||||||||||
D2||OPAD|MGTXTXP0_118|UNUSED|||||||||||
D3|||MGTAVTT||||||||||||
D4|||GND||||||||||||
D5||IPAD|MGTXRXN1_118|UNUSED|||||||||||
D6||IPAD|MGTXRXP1_118|UNUSED|||||||||||
D7|||MGTAVCC||||||||||||
D8|||GND||||||||||||
D9|||GND||||||||||||
D10|||VCCO_18|||18|||||any******||||
D11||IOB33M|IO_L18P_T2_18|UNUSED||18|||||||||
D12||IOB33M|IO_L13P_T2_MRCC_18|UNUSED||18|||||||||
D13||IOB33S|IO_L13N_T2_MRCC_18|UNUSED||18|||||||||
D14||IOB33M|IO_L21P_T3_DQS_18|UNUSED||18|||||||||
D15|||GND||||||||||||
D16||IOB33M|IO_L15P_T2_DQS_17|UNUSED||17|||||||||
D17||IOB33M|IO_L13P_T2_MRCC_17|UNUSED||17|||||||||
D18||IOB33S|IO_L13N_T2_MRCC_17|UNUSED||17|||||||||
D19||IOB33S|IO_L14N_T2_SRCC_17|UNUSED||17|||||||||
D20|||VCCO_17|||17|||||any******||||
D21||IOB33M|IO_L8P_T1_17|UNUSED||17|||||||||
D22||IOB33M|IO_L10P_T1_17|UNUSED||17|||||||||
D23||IOB33S|IO_L2N_T0_16|UNUSED||16|||||||||
D24||IOB33S|IO_L4N_T0_16|UNUSED||16|||||||||
D25|||GND||||||||||||
D26||IOB33M|IO_L11P_T1_SRCC_16|UNUSED||16|||||||||
D27||IOB33M|IO_L13P_T2_MRCC_16|UNUSED||16|||||||||
D28||IOB33S|IO_L14N_T2_SRCC_16|UNUSED||16|||||||||
D29||IOB33M|IO_L16P_T2_16|UNUSED||16|||||||||
D30|||VCCO_16|||16|||||any******||||
E1|||GND||||||||||||
E2|||GND||||||||||||
E3||IPAD|MGTXRXN0_118|UNUSED|||||||||||
E4||IPAD|MGTXRXP0_118|UNUSED|||||||||||
E5|||MGTAVTT||||||||||||
E6|||GND||||||||||||
E7||IPAD|MGTREFCLK1N_118|UNUSED|||||||||||
E8||IPAD|MGTREFCLK1P_118|UNUSED|||||||||||
E9|||GND||||||||||||
E10|||TCK_0||||||||||||
E11||IOB33S|IO_L16N_T2_18|UNUSED||18|||||||||
E12|||GND||||||||||||
E13||IOB33S|IO_L14N_T2_SRCC_18|UNUSED||18|||||||||
E14||IOB33M|IO_L20P_T3_18|UNUSED||18|||||||||
E15||IOB33S|IO_L20N_T3_18|UNUSED||18|||||||||
E16||IOB33S|IO_L19N_T3_VREF_18|UNUSED||18|||||||||
E17|||VCCO_17|||17|||||any******||||
E18||IOB33|IO_25_17|UNUSED||17|||||||||
E19||IOB33M|IO_L14P_T2_SRCC_17|UNUSED||17|||||||||
E20||IOB33S|IO_L12N_T1_MRCC_17|UNUSED||17|||||||||
E21||IOB33S|IO_L11N_T1_SRCC_17|UNUSED||17|||||||||
E22|||GND||||||||||||
E23||IOB33M|IO_L2P_T0_16|UNUSED||16|||||||||
E24||IOB33M|IO_L4P_T0_16|UNUSED||16|||||||||
E25||IOB33S|IO_L3N_T0_DQS_16|UNUSED||16|||||||||
E26||IOB33S|IO_L5N_T0_16|UNUSED||16|||||||||
E27|||VCCO_16|||16|||||any******||||
E28||IOB33M|IO_L14P_T2_SRCC_16|UNUSED||16|||||||||
E29||IOB33M|IO_L18P_T2_16|UNUSED||16|||||||||
E30||IOB33S|IO_L18N_T2_16|UNUSED||16|||||||||
F1||OPAD|MGTXTXN3_117|UNUSED|||||||||||
F2||OPAD|MGTXTXP3_117|UNUSED|||||||||||
F3|||MGTAVTT||||||||||||
F4|||GND||||||||||||
F5||IPAD|MGTXRXN3_117|UNUSED|||||||||||
F6||IPAD|MGTXRXP3_117|UNUSED|||||||||||
F7|||MGTAVCC||||||||||||
F8|||GND||||||||||||
F9|||GND||||||||||||
F10|||TMS_0||||||||||||
F11||IOB33M|IO_L16P_T2_18|UNUSED||18|||||||||
F12||IOB33M|IO_L14P_T2_SRCC_18|UNUSED||18|||||||||
F13||IOB33S|IO_L12N_T1_MRCC_18|UNUSED||18|||||||||
F14|||VCCO_18|||18|||||any******||||
F15||IOB33M|IO_L19P_T3_18|UNUSED||18|||||||||
F16||IOB33|IO_25_18|UNUSED||18|||||||||
F17||IOB33S|IO_L18N_T2_17|UNUSED||17|||||||||
F18||IOB33S|IO_L16N_T2_17|UNUSED||17|||||||||
F19|||GND||||||||||||
F20||IOB33M|IO_L12P_T1_MRCC_17|UNUSED||17|||||||||
F21||IOB33M|IO_L11P_T1_SRCC_17|UNUSED||17|||||||||
F22||IOB33S|IO_L9N_T1_DQS_17|UNUSED||17|||||||||
F23||IOB33|IO_0_16|UNUSED||16|||||||||
F24|||VCCO_16|||16|||||any******||||
F25||IOB33M|IO_L3P_T0_DQS_16|UNUSED||16|||||||||
F26||IOB33M|IO_L5P_T0_16|UNUSED||16|||||||||
F27||IOB33S|IO_L21N_T3_DQS_16|UNUSED||16|||||||||
F28||IOB33S|IO_L20N_T3_16|UNUSED||16|||||||||
F29|||GND||||||||||||
F30||IOB33S|IO_L22N_T3_16|UNUSED||16|||||||||
G1|||GND||||||||||||
G2|||GND||||||||||||
G3||IPAD|MGTXRXN2_117|UNUSED|||||||||||
G4||IPAD|MGTXRXP2_117|UNUSED|||||||||||
G5|||MGTAVTT||||||||||||
G6|||GND||||||||||||
G7||IPAD|MGTREFCLK0N_117|UNUSED|||||||||||
G8||IPAD|MGTREFCLK0P_117|UNUSED|||||||||||
G9|||GND||||||||||||
G10|||TDO_0||||||||||||
G11|||VCCO_18|||18|||||any******||||
G12||IOB33|IO_0_18|UNUSED||18|||||||||
G13||IOB33M|IO_L12P_T1_MRCC_18|UNUSED||18|||||||||
G14||IOB33S|IO_L11N_T1_SRCC_18|UNUSED||18|||||||||
G15||IOB33S|IO_L7N_T1_18|UNUSED||18|||||||||
G16|||GND||||||||||||
G17||IOB33M|IO_L18P_T2_17|UNUSED||17|||||||||
G18||IOB33M|IO_L16P_T2_17|UNUSED||17|||||||||
G19||IOB33|IO_0_17|UNUSED||17|||||||||
G20||IOB33S|IO_L2N_T0_17|UNUSED||17|||||||||
G21|||VCCO_17|||17|||||any******||||
G22||IOB33M|IO_L9P_T1_DQS_17|UNUSED||17|||||||||
G23||IOB33M|IO_L6P_T0_16|UNUSED||16|||||||||
G24||IOB33S|IO_L6N_T0_VREF_16|UNUSED||16|||||||||
G25||IOB33|IO_25_16|UNUSED||16|||||||||
G26|||GND||||||||||||
G27||IOB33M|IO_L21P_T3_DQS_16|UNUSED||16|||||||||
G28||IOB33M|IO_L20P_T3_16|UNUSED||16|||||||||
G29||IOB33M|IO_L22P_T3_16|UNUSED||16|||||||||
G30||IOB33S|IO_L24N_T3_16|UNUSED||16|||||||||
H1||OPAD|MGTXTXN2_117|UNUSED|||||||||||
H2||OPAD|MGTXTXP2_117|UNUSED|||||||||||
H3|||MGTAVTT||||||||||||
H4|||GND||||||||||||
H5||IPAD|MGTXRXN1_117|UNUSED|||||||||||
H6||IPAD|MGTXRXP1_117|UNUSED|||||||||||
H7|||MGTAVCC||||||||||||
H8|||GND||||||||||||
H9|||GND||||||||||||
H10|||TDI_0||||||||||||
H11||IOB33M|IO_L10P_T1_18|UNUSED||18|||||||||
H12||IOB33S|IO_L10N_T1_18|UNUSED||18|||||||||
H13|||GND||||||||||||
H14||IOB33M|IO_L11P_T1_SRCC_18|UNUSED||18|||||||||
H15||IOB33M|IO_L7P_T1_18|UNUSED||18|||||||||
H16||IOB33S|IO_L9N_T1_DQS_18|UNUSED||18|||||||||
H17||IOB33S|IO_L3N_T0_DQS_17|UNUSED||17|||||||||
H18|||VCCO_17|||17|||||any******||||
H19||IOB33S|IO_L4N_T0_17|UNUSED||17|||||||||
H20||IOB33M|IO_L2P_T0_17|UNUSED||17|||||||||
H21||IOB33M|IO_L7P_T1_17|UNUSED||17|||||||||
H22||IOB33S|IO_L7N_T1_17|UNUSED||17|||||||||
H23|||GND||||||||||||
H24||IOB33M|IO_L19P_T3_16|UNUSED||16|||||||||
H25||IOB33S|IO_L19N_T3_VREF_16|UNUSED||16|||||||||
H26||IOB33M|IO_L23P_T3_16|UNUSED||16|||||||||
H27||IOB33S|IO_L23N_T3_16|UNUSED||16|||||||||
H28|||VCCO_16|||16|||||any******||||
H29||IOB33S|IO_L7N_T1_AD10N_15|UNUSED||15|||||||||
H30||IOB33M|IO_L24P_T3_16|UNUSED||16|||||||||
J1|||GND||||||||||||
J2|||GND||||||||||||
J3||OPAD|MGTXTXN1_117|UNUSED|||||||||||
J4||OPAD|MGTXTXP1_117|UNUSED|||||||||||
J5|||MGTAVTT||||||||||||
J6|||GND||||||||||||
J7||IPAD|MGTREFCLK1N_117|UNUSED|||||||||||
J8||IPAD|MGTREFCLK1P_117|UNUSED|||||||||||
J9|||GND||||||||||||
J10|||GND||||||||||||
J11||IOB33M|IO_L8P_T1_18|UNUSED||18|||||||||
J12||IOB33S|IO_L8N_T1_18|UNUSED||18|||||||||
J13||IOB33S|IO_L4N_T0_18|UNUSED||18|||||||||
J14||IOB33S|IO_L5N_T0_18|UNUSED||18|||||||||
J15|||VCCO_18|||18|||||any******||||
J16||IOB33M|IO_L9P_T1_DQS_18|UNUSED||18|||||||||
J17||IOB33M|IO_L3P_T0_DQS_17|UNUSED||17|||||||||
J18||IOB33S|IO_L1N_T0_17|UNUSED||17|||||||||
J19||IOB33M|IO_L4P_T0_17|UNUSED||17|||||||||
J20|||GND||||||||||||
J21||IOB33M|IO_L5P_T0_AD2P_15|UNUSED||15|||||||||
J22||IOB33S|IO_L5N_T0_AD2N_15|UNUSED||15|||||||||
J23||IOB33M|IO_L1P_T0_AD0P_15|UNUSED||15|||||||||
J24||IOB33S|IO_L1N_T0_AD0N_15|UNUSED||15|||||||||
J25|||VCCO_15|||15|||||any******||||
J26||IOB33S|IO_L10N_T1_AD4N_15|UNUSED||15|||||||||
J27||IOB33M|IO_L8P_T1_AD3P_15|UNUSED||15|||||||||
J28||IOB33S|IO_L8N_T1_AD3N_15|UNUSED||15|||||||||
J29||IOB33M|IO_L7P_T1_AD10P_15|UNUSED||15|||||||||
J30|||GND||||||||||||
K1||OPAD|MGTXTXN0_117|UNUSED|||||||||||
K2||OPAD|MGTXTXP0_117|UNUSED|||||||||||
K3|||MGTAVTT||||||||||||
K4|||GND||||||||||||
K5||IPAD|MGTXRXN0_117|UNUSED|||||||||||
K6||IPAD|MGTXRXP0_117|UNUSED|||||||||||
K7|||MGTAVCC||||||||||||
K8|||GND||||||||||||
K9|||GND||||||||||||
K10|||PROGRAM_B_0||||||||||||
K11||IOB33S|IO_L6N_T0_VREF_18|UNUSED||18|||||||||
K12|||VCCO_18|||18|||||any******||||
K13||IOB33M|IO_L4P_T0_18|UNUSED||18|||||||||
K14||IOB33M|IO_L5P_T0_18|UNUSED||18|||||||||
K15||IOB33S|IO_L2N_T0_18|UNUSED||18|||||||||
K16||IOB33S|IO_L1N_T0_18|UNUSED||18|||||||||
K17|||GND||||||||||||
K18||IOB33M|IO_L1P_T0_17|UNUSED||17|||||||||
K19||IOB33M|IO_L6P_T0_17|UNUSED||17|||||||||
K20||IOB33S|IO_L6N_T0_VREF_17|UNUSED||17|||||||||
K21||IOB33S|IO_L4N_T0_AD9N_15|UNUSED||15|||||||||
K22|||VCCO_15|||15|||||any******||||
K23||IOB33M|IO_L3P_T0_DQS_AD1P_15|UNUSED||15|||||||||
K24||IOB33S|IO_L3N_T0_DQS_AD1N_15|UNUSED||15|||||||||
K25||IOB33S|IO_L12N_T1_MRCC_AD5N_15|UNUSED||15|||||||||
K26||IOB33M|IO_L10P_T1_AD4P_15|UNUSED||15|||||||||
K27|||GND||||||||||||
K28||IOB33M|IO_L13P_T2_MRCC_15|UNUSED||15|||||||||
K29||IOB33S|IO_L13N_T2_MRCC_15|UNUSED||15|||||||||
K30||IOB33S|IO_L9N_T1_DQS_AD11N_15|UNUSED||15|||||||||
L1|||GND||||||||||||
L2|||GND||||||||||||
L3||OPAD|MGTXTXN3_116|UNUSED|||||||||||
L4||OPAD|MGTXTXP3_116|UNUSED|||||||||||
L5|||MGTAVTT||||||||||||
L6|||GND||||||||||||
L7||IPAD|MGTREFCLK0N_116|UNUSED|||||||||||
L8||IPAD|MGTREFCLK0P_116|UNUSED|||||||||||
L9|||GND||||||||||||
L10|||CFGBVS_0||||||||||||
L11||IOB33M|IO_L6P_T0_18|UNUSED||18|||||||||
L12||IOB33M|IO_L3P_T0_DQS_18|UNUSED||18|||||||||
L13||IOB33S|IO_L3N_T0_DQS_18|UNUSED||18|||||||||
L14|||GND||||||||||||
L15||IOB33M|IO_L2P_T0_18|UNUSED||18|||||||||
L16||IOB33M|IO_L1P_T0_18|UNUSED||18|||||||||
L17||IOB33M|IO_L5P_T0_17|UNUSED||17|||||||||
L18||IOB33S|IO_L5N_T0_17|UNUSED||17|||||||||
L19|||VCCO_17|||17|||||any******||||
L20||IOB33S|IO_L6N_T0_VREF_15|UNUSED||15|||||||||
L21||IOB33M|IO_L4P_T0_AD9P_15|UNUSED||15|||||||||
L22||IOB33M|IO_L2P_T0_AD8P_15|UNUSED||15|||||||||
L23||IOB33S|IO_L2N_T0_AD8N_15|UNUSED||15|||||||||
L24|||GND||||||||||||
L25||IOB33M|IO_L12P_T1_MRCC_AD5P_15|UNUSED||15|||||||||
L26||IOB33M|IO_L11P_T1_SRCC_AD12P_15|UNUSED||15|||||||||
L27||IOB33S|IO_L11N_T1_SRCC_AD12N_15|UNUSED||15|||||||||
L28||IOB33S|IO_L14N_T2_SRCC_15|UNUSED||15|||||||||
L29|||VCCO_15|||15|||||any******||||
L30||IOB33M|IO_L9P_T1_DQS_AD11P_15|UNUSED||15|||||||||
M1||OPAD|MGTXTXN2_116|UNUSED|||||||||||
M2||OPAD|MGTXTXP2_116|UNUSED|||||||||||
M3|||MGTAVTT||||||||||||
M4|||GND||||||||||||
M5||IPAD|MGTXRXN3_116|UNUSED|||||||||||
M6||IPAD|MGTXRXP3_116|UNUSED|||||||||||
M7|||MGTAVCC||||||||||||
M8|||GND||||||||||||
M9|||GND||||||||||||
M10|||DONE_0||||||||||||
M11|||VCCINT||||||||1.0||||
M12|||GND||||||||||||
M13|||VCCINT||||||||1.0||||
M14|||GND||||||||||||
M15|||VCCINT||||||||1.0||||
M16|||GND||||||||||||
M17|||VCCINT||||||||1.0||||
M18|||GND||||||||||||
M19||IOB33|IO_0_15|UNUSED||15|||||||||
M20||IOB33M|IO_L6P_T0_15|UNUSED||15|||||||||
M21|||GND||||||||||||
M22||IOB33M|IO_L24P_T3_RS1_15|UNUSED||15|||||||||
M23||IOB33S|IO_L24N_T3_RS0_15|UNUSED||15|||||||||
M24||IOB33M|IO_L23P_T3_FOE_B_15|UNUSED||15|||||||||
M25||IOB33S|IO_L23N_T3_FWE_B_15|UNUSED||15|||||||||
M26|||VCCO_15|||15|||||any******||||
M27||IOB33S|IO_L16N_T2_A27_15|UNUSED||15|||||||||
M28||IOB33M|IO_L14P_T2_SRCC_15|UNUSED||15|||||||||
M29||IOB33M|IO_L15P_T2_DQS_15|UNUSED||15|||||||||
M30||IOB33S|IO_L15N_T2_DQS_ADV_B_15|UNUSED||15|||||||||
N1|||GND||||||||||||
N2|||GND||||||||||||
N3||OPAD|MGTXTXN1_116|UNUSED|||||||||||
N4||OPAD|MGTXTXP1_116|UNUSED|||||||||||
N5|||MGTAVTT||||||||||||
N6|||GND||||||||||||
N7||IPAD|MGTREFCLK1N_116|UNUSED|||||||||||
N8||IPAD|MGTREFCLK1P_116|UNUSED|||||||||||
N9|||GND||||||||||||
N10|||VCCINT||||||||1.0||||
N11|||GND||||||||||||
N12|||VCCINT||||||||1.0||||
N13|||GND||||||||||||
N14|||VCCINT||||||||1.0||||
N15|||GND||||||||||||
N16|||VCCBRAM||||||||||||
N17|||GND||||||||||||
N18|||VCCINT||||||||1.0||||
N19||IOB33M|IO_L19P_T3_A22_15|UNUSED||15|||||||||
N20||IOB33S|IO_L19N_T3_A21_VREF_15|UNUSED||15|||||||||
N21||IOB33M|IO_L20P_T3_A20_15|UNUSED||15|||||||||
N22||IOB33S|IO_L20N_T3_A19_15|UNUSED||15|||||||||
N23|||VCCO_15|||15|||||any******||||
N24||IOB33S|IO_L21N_T3_DQS_A18_15|UNUSED||15|||||||||
N25||IOB33M|IO_L18P_T2_A24_15|UNUSED||15|||||||||
N26||IOB33S|IO_L18N_T2_A23_15|UNUSED||15|||||||||
N27||IOB33M|IO_L16P_T2_A28_15|UNUSED||15|||||||||
N28|||GND||||||||||||
N29||IOB33M|IO_L17P_T2_A26_15|UNUSED||15|||||||||
N30||IOB33S|IO_L17N_T2_A25_15|UNUSED||15|||||||||
P1||OPAD|MGTXTXN0_116|UNUSED|||||||||||
P2||OPAD|MGTXTXP0_116|UNUSED|||||||||||
P3|||MGTAVTT||||||||||||
P4|||GND||||||||||||
P5||IPAD|MGTXRXN2_116|UNUSED|||||||||||
P6||IPAD|MGTXRXP2_116|UNUSED|||||||||||
P7|||MGTAVCC||||||||||||
P8|||GND||||||||||||
P9|||GND||||||||||||
P10|||GND||||||||||||
P11|||VCCINT||||||||1.0||||
P12|||GND||||||||||||
P13|||VCCAUX||||||||1.8||||
P14|||GNDADC_0||||||||||||
P15|||VCCADC_0||||||||||||
P16|||GND||||||||||||
P17|||VCCINT||||||||1.0||||
P18|||GND||||||||||||
P19||IOB33|IO_25_15|UNUSED||15|||||||||
P20|||VCCO_15|||15|||||any******||||
P21||IOB33M|IO_L22P_T3_A17_15|UNUSED||15|||||||||
P22||IOB33S|IO_L22N_T3_A16_15|UNUSED||15|||||||||
P23||IOB33M|IO_L21P_T3_DQS_15|UNUSED||15|||||||||
P24||IOB33M|IO_L1P_T0_D00_MOSI_14|UNUSED||14|||||||||
P25|||GND||||||||||||
P26||IOB33M|IO_L10P_T1_D14_14|UNUSED||14|||||||||
P27||IOB33M|IO_L8P_T1_D11_14|UNUSED||14|||||||||
P28||IOB33S|IO_L8N_T1_D12_14|UNUSED||14|||||||||
P29||IOB33M|IO_L7P_T1_D09_14|UNUSED||14|||||||||
P30|||VCCO_14|||14|||||any******||||
R1|||GND||||||||||||
R2|||GND||||||||||||
R3||IPAD|MGTXRXN1_116|UNUSED|||||||||||
R4||IPAD|MGTXRXP1_116|UNUSED|||||||||||
R5|||MGTAVTT||||||||||||
R6|||GND||||||||||||
R7||IPAD|MGTREFCLK0N_115|UNUSED|||||||||||
R8||IPAD|MGTREFCLK0P_115|UNUSED|||||||||||
R9|||GND||||||||||||
R10|||VCCINT||||||||1.0||||
R11|||GND||||||||||||
R12|||VCCINT||||||||1.0||||
R13|||GND||||||||||||
R14|||VREFN_0||||||||||||
R15||IPAD|VP_0|UNUSED||0|||||||||
R16|||VCCBRAM||||||||||||
R17|||GND||||||||||||
R18|||VCCINT||||||||1.0||||
R19||IOB33|IO_0_14|UNUSED||14|||||||||
R20||IOB33M|IO_L2P_T0_D02_14|UNUSED||14|||||||||
R21||IOB33S|IO_L2N_T0_D03_14|UNUSED||14|||||||||
R22|||GND||||||||||||
R23||IOB33M|IO_L3P_T0_DQS_PUDC_B_14|UNUSED||14|||||||||
R24||IOB33S|IO_L3N_T0_DQS_EMCCLK_14|UNUSED||14|||||||||
R25||IOB33S|IO_L1N_T0_D01_DIN_14|UNUSED||14|||||||||
R26||IOB33S|IO_L10N_T1_D15_14|UNUSED||14|||||||||
R27|||VCCO_14|||14|||||any******||||
R28||IOB33M|IO_L11P_T1_SRCC_14|UNUSED||14|||||||||
R29||IOB33S|IO_L7N_T1_D10_14|UNUSED||14|||||||||
R30||IOB33M|IO_L9P_T1_DQS_14|UNUSED||14|||||||||
T1||OPAD|MGTXTXN3_115|UNUSED|||||||||||
T2||OPAD|MGTXTXP3_115|UNUSED|||||||||||
T3|||MGTAVTT||||||||||||
T4|||GND||||||||||||
T5||IPAD|MGTXRXN0_116|UNUSED|||||||||||
T6||IPAD|MGTXRXP0_116|UNUSED|||||||||||
T7|||MGTVCCAUX||||||||||||
T8|||GND||||||||||||
T9|||VCCO_0|||0|||||any******||||
T10|||GND||||||||||||
T11|||VCCINT||||||||1.0||||
T12|||GND||||||||||||
T13|||VCCAUX||||||||1.8||||
T14||IPAD|VN_0|UNUSED||0|||||||||
T15|||VREFP_0||||||||||||
T16|||GND||||||||||||
T17|||VCCINT||||||||1.0||||
T18|||GND||||||||||||
T19|||GND||||||||||||
T20||IOB33M|IO_L4P_T0_D04_14|UNUSED||14|||||||||
T21||IOB33S|IO_L4N_T0_D05_14|UNUSED||14|||||||||
T22||IOB33M|IO_L5P_T0_D06_14|UNUSED||14|||||||||
T23||IOB33S|IO_L5N_T0_D07_14|UNUSED||14|||||||||
T24|||VCCO_14|||14|||||any******||||
T25||IOB33M|IO_L14P_T2_SRCC_14|UNUSED||14|||||||||
T26||IOB33M|IO_L12P_T1_MRCC_14|UNUSED||14|||||||||
T27||IOB33S|IO_L12N_T1_MRCC_14|UNUSED||14|||||||||
T28||IOB33S|IO_L11N_T1_SRCC_14|UNUSED||14|||||||||
T29|||GND||||||||||||
T30||IOB33S|IO_L9N_T1_DQS_D13_14|UNUSED||14|||||||||
U1|||GND||||||||||||
U2|||GND||||||||||||
U3||OPAD|MGTXTXN2_115|UNUSED|||||||||||
U4||OPAD|MGTXTXP2_115|UNUSED|||||||||||
U5|||MGTAVTT||||||||||||
U6|||GND||||||||||||
U7||IPAD|MGTREFCLK1N_115|UNUSED|||||||||||
U8||IPAD|MGTREFCLK1P_115|UNUSED|||||||||||
U9|||GND||||||||||||
U10|||VCCINT||||||||1.0||||
U11|||GND||||||||||||
U12|||VCCINT||||||||1.0||||
U13|||GND||||||||||||
U14|||DXN_0||||||||||||
U15|||DXP_0||||||||||||
U16|||VCCBRAM||||||||||||
U17|||GND||||||||||||
U18|||VCCINT||||||||1.0||||
U19||IOB33M|IO_L6P_T0_FCS_B_14|UNUSED||14|||||||||
U20||IOB33S|IO_L6N_T0_D08_VREF_14|UNUSED||14|||||||||
U21|||VCCO_14|||14|||||any******||||
U22||IOB33M|IO_L21P_T3_DQS_14|UNUSED||14|||||||||
U23||IOB33S|IO_L21N_T3_DQS_A06_D22_14|UNUSED||14|||||||||
U24||IOB33M|IO_L23P_T3_A03_D19_14|UNUSED||14|||||||||
U25||IOB33S|IO_L14N_T2_SRCC_14|UNUSED||14|||||||||
U26|||GND||||||||||||
U27||IOB33M|IO_L13P_T2_MRCC_14|UNUSED||14|||||||||
U28||IOB33S|IO_L13N_T2_MRCC_14|UNUSED||14|||||||||
U29||IOB33M|IO_L15P_T2_DQS_RDWR_B_14|UNUSED||14|||||||||
U30||IOB33S|IO_L15N_T2_DQS_DOUT_CSO_B_14|UNUSED||14|||||||||
V1||OPAD|MGTXTXN1_115|UNUSED|||||||||||
V2||OPAD|MGTXTXP1_115|UNUSED|||||||||||
V3|||MGTAVTT||||||||||||
V4|||GND||||||||||||
V5||IPAD|MGTXRXN3_115|UNUSED|||||||||||
V6||IPAD|MGTXRXP3_115|UNUSED|||||||||||
V7|||MGTVCCAUX||||||||||||
V8|||GND||||||||||||
V9|||GND||||||||||||
V10|||GND||||||||||||
V11|||VCCAUX_IO_G0||||||||1.8||||
V12|||GND||||||||||||
V13|||VCCAUX||||||||1.8||||
V14|||GND||||||||||||
V15|||VCCAUX||||||||1.8||||
V16|||GND||||||||||||
V17|||VCCINT||||||||1.0||||
V18|||GND||||||||||||
V19||IOB33M|IO_L19P_T3_A10_D26_14|UNUSED||14|||||||||
V20||IOB33S|IO_L19N_T3_A09_D25_VREF_14|UNUSED||14|||||||||
V21||IOB33M|IO_L22P_T3_A05_D21_14|UNUSED||14|||||||||
V22||IOB33S|IO_L22N_T3_A04_D20_14|UNUSED||14|||||||||
V23|||GND||||||||||||
V24||IOB33S|IO_L23N_T3_A02_D18_14|UNUSED||14|||||||||
V25||IOB33M|IO_L18P_T2_A12_D28_14|UNUSED||14|||||||||
V26||IOB33M|IO_L16P_T2_CSI_B_14|UNUSED||14|||||||||
V27||IOB33S|IO_L16N_T2_A15_D31_14|UNUSED||14|||||||||
V28|||VCCO_14|||14|||||any******||||
V29||IOB33M|IO_L17P_T2_A14_D30_14|UNUSED||14|||||||||
V30||IOB33S|IO_L17N_T2_A13_D29_14|UNUSED||14|||||||||
W1|||GND||||||||||||
W2|||GND||||||||||||
W3||IPAD|MGTXRXN2_115|UNUSED|||||||||||
W4||IPAD|MGTXRXP2_115|UNUSED|||||||||||
W5|||MGTAVTT||||||||||||
W6|||GND||||||||||||
W7|||MGTAVTTRCAL_115||||||||||||
W8|||MGTRREF_115||||||||||||
W9|||GND||||||||||||
W10|||VCCAUX_IO_G0||||||||1.8||||
W11|||GND||||||||||||
W12|||VCCAUX_IO_G0||||||||1.8||||
W13|||GND||||||||||||
W14|||VCCAUX||||||||1.8||||
W15|||GND||||||||||||
W16|||VCCBRAM||||||||||||
W17|||GND||||||||||||
W18|||VCCINT||||||||1.0||||
W19||IOB33|IO_25_14|UNUSED||14|||||||||
W20|||GND||||||||||||
W21||IOB33M|IO_L24P_T3_A01_D17_14|UNUSED||14|||||||||
W22||IOB33S|IO_L24N_T3_A00_D16_14|UNUSED||14|||||||||
W23||IOB33M|IO_L20P_T3_A08_D24_14|UNUSED||14|||||||||
W24||IOB33S|IO_L20N_T3_A07_D23_14|UNUSED||14|||||||||
W25|||VCCO_14|||14|||||any******||||
W26||IOB33S|IO_L18N_T2_A11_D27_14|UNUSED||14|||||||||
W27||IOB33M|IO_L2P_T0_13|UNUSED||13|||||||||
W28||IOB33S|IO_L2N_T0_13|UNUSED||13|||||||||
W29||IOB33M|IO_L4P_T0_13|UNUSED||13|||||||||
W30|||GND||||||||||||
Y1||OPAD|MGTXTXN0_115|UNUSED|||||||||||
Y2||OPAD|MGTXTXP0_115|UNUSED|||||||||||
Y3|||GND||||||||||||
Y4|||GND||||||||||||
Y5||IPAD|MGTXRXN1_115|UNUSED|||||||||||
Y6||IPAD|MGTXRXP1_115|UNUSED|||||||||||
Y7|||GND||||||||||||
Y8|||GND||||||||||||
Y9|||GND||||||||||||
Y10|ddr3_addr<9>|IOB18|IO_L4N_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
Y11|ddr3_addr<10>|IOB18|IO_L4P_T0_33|OUTPUT|SSTL15|33||FAST||||LOCATED|NO|NONE|
Y12|||VCCO_33|||33|||||1.50||||
Y13||IOB18|IO_0_VRN_33|UNUSED||33|||||||||
Y14||IOB18|IO_0_VRN_32|UNUSED||32|||||||||
Y15||IOB18S|IO_L24N_T3_32|UNUSED||32|||||||||
Y16||IOB18M|IO_L24P_T3_32|UNUSED||32|||||||||
Y17|||GND||||||||||||
Y18||IOB18S|IO_L15N_T2_DQS_32|UNUSED||32|||||||||
Y19||IOB18M|IO_L15P_T2_DQS_32|UNUSED||32|||||||||
Y20||IOB33|IO_0_12|UNUSED||12|||||||||
Y21||IOB33M|IO_L2P_T0_12|UNUSED||12|||||||||
Y22|||VCCO_12|||12|||||any******||||
Y23||IOB33M|IO_L1P_T0_12|UNUSED||12|||||||||
Y24||IOB33S|IO_L1N_T0_12|UNUSED||12|||||||||
Y25||IOB33|IO_0_13|UNUSED||13|||||||||
Y26||IOB33M|IO_L1P_T0_13|UNUSED||13|||||||||
Y27|||GND||||||||||||
Y28||IOB33M|IO_L3P_T0_DQS_13|UNUSED||13|||||||||
Y29||IOB33S|IO_L4N_T0_13|UNUSED||13|||||||||
Y30|tg_compare_error|IOB33|IO_L8P_T1_13|OUTPUT|LVCMOS33|13|12|SLOW||||LOCATED|NO|NONE|
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
All RSVD_0 pins must be tied to GROUND.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
top/x300/coregen/ddr3_32bit/example_design/par/example_top.par
+1647
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.pcf
+59949
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.ptwx
+332
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top.syr
+15162
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.twr
+5430
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top.twx
+473
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top.ucf
+180
View File
@@ -0,0 +1,180 @@
##################################################################################################
##
## Xilinx, Inc. 2010 www.xilinx.com
## Thu Jan 17 15:55:53 2013
## Generated by MIG Version 1.8
##
##################################################################################################
## File name : example_top.ucf
## Details : Constraints file
## FPGA Family: KINTEX7
## FPGA Part: XC7K410T-FFG900
## Speedgrade: -2
## Design Entry: VERILOG
## Frequency: 500 MHz
## Time Period: 2000 ps
##################################################################################################
##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-125
## Data Width: 32
## Time Period: 2000
## Data Mask: 1
##################################################################################################
NET "sys_clk_i" TNM_NET = TNM_sys_clk;
TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 10 ns;
#NET "clk_ref_i" TNM_NET = TNM_clk_ref;
#TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;
# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
# to the following:
# WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
# placed at an optimal clock IOB / PLL site pair.
# This warning can be ignored. See the Users Guide for more information.
NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
PIN "*/u_ddr3_infrastructure/plle2_i.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;
############## NET - IOSTANDARD ##################
NET "ddr3_dq[0]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_34
NET "ddr3_dq[1]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_34
NET "ddr3_dq[2]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_34
NET "ddr3_dq[3]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_34
NET "ddr3_dq[4]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_34
NET "ddr3_dq[5]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_34
NET "ddr3_dq[6]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_34
NET "ddr3_dq[7]" LOC = "AC7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_34
NET "ddr3_dq[8]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_34
NET "ddr3_dq[9]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_34
NET "ddr3_dq[10]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_34
NET "ddr3_dq[11]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_34
NET "ddr3_dq[12]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_34
NET "ddr3_dq[13]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_34
NET "ddr3_dq[14]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_34
NET "ddr3_dq[15]" LOC = "AF6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_34
NET "ddr3_dq[16]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34
NET "ddr3_dq[17]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34
NET "ddr3_dq[18]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34
NET "ddr3_dq[19]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_34
NET "ddr3_dq[20]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_34
NET "ddr3_dq[21]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17P_T2_34
NET "ddr3_dq[22]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17N_T2_34
NET "ddr3_dq[23]" LOC = "AJ3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_34
NET "ddr3_dq[24]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_34
NET "ddr3_dq[25]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_34
NET "ddr3_dq[26]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_34
NET "ddr3_dq[27]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_34
NET "ddr3_dq[28]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_34
NET "ddr3_dq[29]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_34
NET "ddr3_dq[30]" LOC = "AK5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_34
NET "ddr3_dq[31]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_34
NET "ddr3_addr[14]" LOC = "AA12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_33
NET "ddr3_addr[13]" LOC = "AB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_33
NET "ddr3_addr[12]" LOC = "AA8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_33
NET "ddr3_addr[11]" LOC = "AB8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_33
NET "ddr3_addr[10]" LOC = "Y11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_33
NET "ddr3_addr[9]" LOC = "Y10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_33
NET "ddr3_addr[8]" LOC = "AA11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_33
NET "ddr3_addr[7]" LOC = "AA10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_33
NET "ddr3_addr[6]" LOC = "AA13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_33
NET "ddr3_addr[5]" LOC = "AB13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6N_T0_VREF_33
NET "ddr3_addr[4]" LOC = "AB10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_33
NET "ddr3_addr[3]" LOC = "AC10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_33
NET "ddr3_addr[2]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_33
NET "ddr3_addr[1]" LOC = "AE8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_33
NET "ddr3_addr[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_33
NET "ddr3_ba[2]" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_33
NET "ddr3_ba[1]" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_33
NET "ddr3_ba[0]" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_33
NET "ddr3_ras_n" LOC = "AE11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_33
NET "ddr3_cas_n" LOC = "AF11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_33
NET "ddr3_we_n" LOC = "AD12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_33
NET "ddr3_reset_n" LOC = "AG5" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_34
NET "ddr3_cke[0]" LOC = "AJ9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_33
NET "ddr3_odt[0]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_33
NET "ddr3_cs_n[0]" LOC = "AD11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_33
NET "ddr3_dm[0]" LOC = "AD4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_34
NET "ddr3_dm[1]" LOC = "AF3" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_34
NET "ddr3_dm[2]" LOC = "AH4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34
NET "ddr3_dm[3]" LOC = "AF8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_34
#NET "sys_clk_i" LOC = "AD17" | IOSTANDARD = LVCMOS18 | VCCAUX_IO = DONTCARE ; # Pad function: IO_L14P_T2_SRCC_32
NET "sys_clk_i" LOC = "AE10" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL ; # Manual change that wasn't allowed by MIG v1.8
NET "ddr3_dqs_p[0]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34
NET "ddr3_dqs_n[0]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34
NET "ddr3_dqs_p[1]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_34
NET "ddr3_dqs_n[1]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_34
NET "ddr3_dqs_p[2]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34
NET "ddr3_dqs_n[2]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34
NET "ddr3_dqs_p[3]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_34
NET "ddr3_dqs_n[3]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_34
NET "ddr3_ck_p[0]" LOC = "AB9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_33
NET "ddr3_ck_n[0]" LOC = "AC9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_33
NET "sys_rst" IOSTANDARD = LVCMOS33 | LOC = AC29 | PULLUP;
NET "tg_compare_error" IOSTANDARD = LVCMOS33 | LOC = Y30;
NET "init_calib_complete" IOSTANDARD = LVCMOS33 | LOC = AA30;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107;
INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y1;
NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2000 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;
INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;
top/x300/coregen/ddr3_32bit/example_design/par/example_top.unroutes
+181
View File
@@ -0,0 +1,181 @@
Release 14.4 - par P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Tue Jan 22 18:32:42 2013
All signals are completely routed.
WARNING:ParHelpers:361 - There are 169 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_19_ML_NEW_IBUFDISABLE
V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_21_ML_NEW_IBUFDISABLE
V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_23_ML_NEW_IBUFDISABLE
V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_25_ML_NEW_IBUFDISABLE
u_ddr3_32bit/u_ddr3_infrastructure/rst_phaser_ref_sync_r<0>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMC_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r<65>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r<7>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r<7>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r<7>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_carry3<4>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_carry3<4>
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.status_ram.RAM32M0_RAMB_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.status_ram.RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O
u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O
top/x300/coregen/ddr3_32bit/example_design/par/example_top.xdc
+547
View File
@@ -0,0 +1,547 @@
##################################################################################################
##
## Xilinx, Inc. 2010 www.xilinx.com
## Thu Jan 24 15:58:25 2013
## Generated by MIG Version 1.8
##
##################################################################################################
## File name : example_top.xdc
## Details : Constraints file
## FPGA Family: KINTEX7
## FPGA Part: XC7K410T-FFG900
## Speedgrade: -2
## Design Entry: VERILOG
## Frequency: 500 MHz
## Time Period: 2000 ps
##################################################################################################
##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-125
## Data Width: 32
## Time Period: 2000
## Data Mask: 1
##################################################################################################
create_clock -name sys_clk_i -period 10 [get_ports sys_clk_i]
#set_propagated_clock sys_clk_i
#create_clock -name clk_ref_i -period 5 [get_ports clk_ref_i]
#set_propagated_clock clk_ref_i
# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
# to the following:
# WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
# placed at an optimal clock IOB / PLL site pair.
# This warning can be ignored. See the Users Guide for more information.
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_i]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
############## NET - IOSTANDARD ##################
# PadFunction: IO_L1N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]
set_property LOC AD3 [get_ports {ddr3_dq[0]}]
# PadFunction: IO_L2P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]
set_property LOC AC2 [get_ports {ddr3_dq[1]}]
# PadFunction: IO_L2N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]
set_property LOC AC1 [get_ports {ddr3_dq[2]}]
# PadFunction: IO_L4P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]
set_property LOC AC5 [get_ports {ddr3_dq[3]}]
# PadFunction: IO_L4N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]
set_property LOC AC4 [get_ports {ddr3_dq[4]}]
# PadFunction: IO_L5P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]
set_property LOC AD6 [get_ports {ddr3_dq[5]}]
# PadFunction: IO_L5N_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]
set_property LOC AE6 [get_ports {ddr3_dq[6]}]
# PadFunction: IO_L6P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]
set_property LOC AC7 [get_ports {ddr3_dq[7]}]
# PadFunction: IO_L7N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]
set_property LOC AF2 [get_ports {ddr3_dq[8]}]
# PadFunction: IO_L8P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]
set_property LOC AE1 [get_ports {ddr3_dq[9]}]
# PadFunction: IO_L8N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]
set_property LOC AF1 [get_ports {ddr3_dq[10]}]
# PadFunction: IO_L10P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]
set_property LOC AE4 [get_ports {ddr3_dq[11]}]
# PadFunction: IO_L10N_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]
set_property LOC AE3 [get_ports {ddr3_dq[12]}]
# PadFunction: IO_L11P_T1_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]
set_property LOC AE5 [get_ports {ddr3_dq[13]}]
# PadFunction: IO_L11N_T1_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]
set_property LOC AF5 [get_ports {ddr3_dq[14]}]
# PadFunction: IO_L12P_T1_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]
set_property LOC AF6 [get_ports {ddr3_dq[15]}]
# PadFunction: IO_L13N_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]
set_property LOC AJ4 [get_ports {ddr3_dq[16]}]
# PadFunction: IO_L14P_T2_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]
set_property LOC AH6 [get_ports {ddr3_dq[17]}]
# PadFunction: IO_L14N_T2_SRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]
set_property LOC AH5 [get_ports {ddr3_dq[18]}]
# PadFunction: IO_L16P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]
set_property LOC AH2 [get_ports {ddr3_dq[19]}]
# PadFunction: IO_L16N_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]
set_property LOC AJ2 [get_ports {ddr3_dq[20]}]
# PadFunction: IO_L17P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]
set_property LOC AJ1 [get_ports {ddr3_dq[21]}]
# PadFunction: IO_L17N_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]
set_property LOC AK1 [get_ports {ddr3_dq[22]}]
# PadFunction: IO_L18P_T2_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]
set_property LOC AJ3 [get_ports {ddr3_dq[23]}]
# PadFunction: IO_L20P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]
set_property LOC AF7 [get_ports {ddr3_dq[24]}]
# PadFunction: IO_L20N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]
set_property LOC AG7 [get_ports {ddr3_dq[25]}]
# PadFunction: IO_L22P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]
set_property LOC AJ6 [get_ports {ddr3_dq[26]}]
# PadFunction: IO_L22N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]
set_property LOC AK6 [get_ports {ddr3_dq[27]}]
# PadFunction: IO_L23P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]
set_property LOC AJ8 [get_ports {ddr3_dq[28]}]
# PadFunction: IO_L23N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]
set_property LOC AK8 [get_ports {ddr3_dq[29]}]
# PadFunction: IO_L24P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]
set_property LOC AK5 [get_ports {ddr3_dq[30]}]
# PadFunction: IO_L24N_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]
set_property LOC AK4 [get_ports {ddr3_dq[31]}]
# PadFunction: IO_L1P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
set_property LOC AA12 [get_ports {ddr3_addr[14]}]
# PadFunction: IO_L1N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
set_property LOC AB12 [get_ports {ddr3_addr[13]}]
# PadFunction: IO_L2P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
set_property LOC AA8 [get_ports {ddr3_addr[12]}]
# PadFunction: IO_L2N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
set_property LOC AB8 [get_ports {ddr3_addr[11]}]
# PadFunction: IO_L4P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
set_property LOC Y11 [get_ports {ddr3_addr[10]}]
# PadFunction: IO_L4N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
set_property LOC Y10 [get_ports {ddr3_addr[9]}]
# PadFunction: IO_L5P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
set_property LOC AA11 [get_ports {ddr3_addr[8]}]
# PadFunction: IO_L5N_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
set_property LOC AA10 [get_ports {ddr3_addr[7]}]
# PadFunction: IO_L6P_T0_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
set_property LOC AA13 [get_ports {ddr3_addr[6]}]
# PadFunction: IO_L6N_T0_VREF_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
set_property LOC AB13 [get_ports {ddr3_addr[5]}]
# PadFunction: IO_L7P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
set_property LOC AB10 [get_ports {ddr3_addr[4]}]
# PadFunction: IO_L7N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
set_property LOC AC10 [get_ports {ddr3_addr[3]}]
# PadFunction: IO_L8P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
set_property LOC AD8 [get_ports {ddr3_addr[2]}]
# PadFunction: IO_L8N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
set_property LOC AE8 [get_ports {ddr3_addr[1]}]
# PadFunction: IO_L9P_T1_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property LOC AC12 [get_ports {ddr3_addr[0]}]
# PadFunction: IO_L9N_T1_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
set_property LOC AC11 [get_ports {ddr3_ba[2]}]
# PadFunction: IO_L10P_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
set_property LOC AD9 [get_ports {ddr3_ba[1]}]
# PadFunction: IO_L10N_T1_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
set_property LOC AE9 [get_ports {ddr3_ba[0]}]
# PadFunction: IO_L11P_T1_SRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ras_n}]
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property LOC AE11 [get_ports {ddr3_ras_n}]
# PadFunction: IO_L11N_T1_SRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cas_n}]
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property LOC AF11 [get_ports {ddr3_cas_n}]
# PadFunction: IO_L12P_T1_MRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_we_n}]
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property LOC AD12 [get_ports {ddr3_we_n}]
# PadFunction: IO_L12N_T1_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_reset_n}]
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
set_property LOC AG5 [get_ports {ddr3_reset_n}]
# PadFunction: IO_L15P_T2_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cke[0]}]
set_property SLEW FAST [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
set_property LOC AJ9 [get_ports {ddr3_cke[0]}]
# PadFunction: IO_L15N_T2_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_odt[0]}]
set_property SLEW FAST [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
set_property LOC AK9 [get_ports {ddr3_odt[0]}]
# PadFunction: IO_L12N_T1_MRCC_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_cs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
set_property LOC AD11 [get_ports {ddr3_cs_n[0]}]
# PadFunction: IO_L1P_T0_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[0]}]
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
set_property LOC AD4 [get_ports {ddr3_dm[0]}]
# PadFunction: IO_L7P_T1_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[1]}]
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
set_property LOC AF3 [get_ports {ddr3_dm[1]}]
# PadFunction: IO_L13P_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[2]}]
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
set_property LOC AH4 [get_ports {ddr3_dm[2]}]
# PadFunction: IO_L19P_T3_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dm[3]}]
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
set_property LOC AF8 [get_ports {ddr3_dm[3]}]
# PadFunction: IO_L14P_T2_SRCC_32
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_i}]
set_property IOSTANDARD LVCMOS18 [get_ports {sys_clk_i}]
set_property LOC AD17 [get_ports {sys_clk_i}]
# PadFunction: IO_L3P_T0_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]
set_property LOC AD2 [get_ports {ddr3_dqs_p[0]}]
# PadFunction: IO_L3N_T0_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]
set_property LOC AD1 [get_ports {ddr3_dqs_n[0]}]
# PadFunction: IO_L9P_T1_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]
set_property LOC AG4 [get_ports {ddr3_dqs_p[1]}]
# PadFunction: IO_L9N_T1_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]
set_property LOC AG3 [get_ports {ddr3_dqs_n[1]}]
# PadFunction: IO_L15P_T2_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]
set_property LOC AG2 [get_ports {ddr3_dqs_p[2]}]
# PadFunction: IO_L15N_T2_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]
set_property LOC AH1 [get_ports {ddr3_dqs_n[2]}]
# PadFunction: IO_L21P_T3_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]
set_property LOC AH7 [get_ports {ddr3_dqs_p[3]}]
# PadFunction: IO_L21N_T3_DQS_34
set_property VCCAUX_IO NORMAL [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]
set_property LOC AJ7 [get_ports {ddr3_dqs_n[3]}]
# PadFunction: IO_L3P_T0_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ck_p[0]}]
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
set_property LOC AB9 [get_ports {ddr3_ck_p[0]}]
# PadFunction: IO_L3N_T0_DQS_33
set_property VCCAUX_IO NORMAL [get_ports {ddr3_ck_n[0]}]
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
set_property LOC AC9 [get_ports {ddr3_ck_n[0]}]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out]
set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out]
## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in]
## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in]
## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in]
set_property LOC PHASER_IN_PHY_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in]
set_property LOC OUT_FIFO_X1Y7 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo]
set_property LOC OUT_FIFO_X1Y6 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo]
set_property LOC OUT_FIFO_X1Y5 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo]
set_property LOC OUT_FIFO_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo]
set_property LOC OUT_FIFO_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo]
set_property LOC OUT_FIFO_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo]
set_property LOC OUT_FIFO_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo]
set_property LOC IN_FIFO_X1Y11 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y10 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y9 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo]
set_property LOC IN_FIFO_X1Y8 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo]
set_property LOC PHY_CONTROL_X1Y1 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i]
set_property LOC PHY_CONTROL_X1Y2 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i]
set_property LOC PHASER_REF_X1Y1 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i]
set_property LOC PHASER_REF_X1Y2 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i]
set_property LOC OLOGIC_X1Y143 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y131 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y119 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts]
set_property LOC OLOGIC_X1Y107 [get_cells u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts]
set_property LOC PLLE2_ADV_X1Y1 [get_cells u_ddr3_32bit/u_ddr3_infrastructure/plle2_i]
set_property LOC MMCME2_ADV_X1Y1 [get_cells u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i]
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-setup 6
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-hold 5
set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/device_temp_sync_r1*}] \
-setup 12 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/device_temp_sync_r1*}] \
-hold 11 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/xadc_supplied_temperature.rst_r1*}] \
-setup 2 -end
set_multicycle_path -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_mig_7series_v1_8_tempmon/xadc_supplied_temperature.rst_r1*}] \
-hold 1 -end
top/x300/coregen/ddr3_32bit/example_design/par/example_top.xpi
+3
View File
@@ -0,0 +1,3 @@
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
top/x300/coregen/ddr3_32bit/example_design/par/example_top_bitgen.xwbt
+8
View File
@@ -0,0 +1,8 @@
INTSTYLE=ise
INFILE=/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/example_design/par/example_top.ncd
OUTFILE=/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/example_design/par/example_top.bit
FAMILY=Kintex7
PART=xc7k410t-2ffg900
WORKINGDIR=/disk2/ianb/ettus/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_32bit/example_design/par
LICENSE=ISE
USER_INFO=174231325_175453155_210544338_549
top/x300/coregen/ddr3_32bit/example_design/par/example_top_map.map
+981
View File
@@ -0,0 +1,981 @@
Release 14.4 Map P.49d (lin64)
Xilinx Map Application Log File for Design 'example_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc7k410t-ffg900-2 -w -ol high -xe n
-register_duplication off -ir off -pr off -lc off -power off -o
example_top_map.ncd example_top.ngd example_top.pcf
Target Device : xc7k410t
Target Package : ffg900
Target Speed : -2
Mapper Version : kintex7 -- $Revision: 1.55 $
Mapped Date : Tue Jan 22 18:25:00 2013
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 55 secs
Total CPU time at the beginning of Placer: 54 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:31f6fa36) REAL time: 1 mins 8 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:31f6fa36) REAL time: 1 mins 9 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f4af0eaa) REAL time: 1 mins 9 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:6b3f168) REAL time: 1 mins 28 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:6b3f168) REAL time: 1 mins 28 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:6b3f168) REAL time: 1 mins 29 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:6b3f168) REAL time: 1 mins 29 secs
Phase 8.8 Global Placement
........................................
.........................
.......................................................................................
..........................................................................................................................................
....................................................................................................................................
Phase 8.8 Global Placement (Checksum:86f68ff8) REAL time: 3 mins 42 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:86f68ff8) REAL time: 3 mins 43 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:e61b4100) REAL time: 4 mins 28 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:e61b4100) REAL time: 4 mins 28 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:e61b4100) REAL time: 4 mins 29 secs
Total REAL time to Placer completion: 5 mins 32 secs
Total CPU time to Placer completion: 5 mins 30 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_ca
rry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_FPGA_ADJUSTED_LEN.last_word_for_mask_dummy_
carry3<4>> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_23_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_21_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_25_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_19_ML_NEW_IBUFDISABLE> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<20>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<21>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<18>> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer
_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/M_MESG_I<19>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer
_ram.rams[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMB_D1_DPO> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.status_ram.RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMC_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/rea
d_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_ddr3_infrastructure/rst_phaser_ref_sync_r<0>> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_str
ict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_R
AMD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_D.ddr_byte_lane_D/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RA
MD_D1_O> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_B.ddr_byte_lane_B/rd_data_r<7>> is incomplete. The signal does not drive any
load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_dd
r_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane
_A.ddr_byte_lane_A/rd_data_r<65>> is incomplete. The signal does not drive
any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<u_ddr3_32bit/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_b
uffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:2487 - For MMCM_ADV block
u_ddr3_32bit/u_ddr3_infrastructure/mmcm_i, the CLKOUT0_DIVIDE_F programming
of <6.4> is not supported. CLKOUT0_DIVIDE_F will be adjusted to the hardware
granularity of a multiple of 0.125.
WARNING:PhysDesignRules:2245 - The PLLE2_ADV block
<u_ddr3_32bit/u_ddr3_infrastructure/plle2_i> has CLKOUT pins that do not
drive the same kind of BUFFER load. Routing from the different buffer types
will not be phase aligned.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 172
Slice Logic Utilization:
Number of Slice Registers: 12,744 out of 508,400 2%
Number used as Flip Flops: 12,721
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 22
Number of Slice LUTs: 10,803 out of 254,200 4%
Number used as logic: 8,544 out of 254,200 3%
Number using O6 output only: 7,472
Number using O5 output only: 59
Number using O5 and O6: 1,013
Number used as ROM: 0
Number used as Memory: 1,452 out of 90,600 1%
Number used as Dual Port RAM: 560
Number using O6 output only: 0
Number using O5 output only: 11
Number using O5 and O6: 549
Number used as Single Port RAM: 0
Number used as Shift Register: 892
Number using O6 output only: 806
Number using O5 output only: 0
Number using O5 and O6: 86
Number used exclusively as route-thrus: 807
Number with same-slice register load: 684
Number with same-slice carry load: 123
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,317 out of 63,550 6%
Number of LUT Flip Flop pairs used: 14,415
Number with an unused Flip Flop: 3,027 out of 14,415 20%
Number with an unused LUT: 3,612 out of 14,415 25%
Number of fully used LUT-FF pairs: 7,776 out of 14,415 53%
Number of unique control sets: 528
Number of slice register sites lost
to control set restrictions: 2,031 out of 508,400 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 75 out of 500 15%
Number of LOCed IOBs: 75 out of 75 100%
IOB Flip Flops: 9
IOB Master Pads: 5
IOB Slave Pads: 5
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 5 out of 795 1%
Number using RAMB36E1 only: 5
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 1 out of 1,590 1%
Number using RAMB18E1 only: 1
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 3 out of 32 9%
Number used as BUFGs: 3
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 32 out of 500 6%
Number used as IDELAYE2s: 32
Number used as IDELAYE2_FINEDELAYs: 0
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 32 out of 500 6%
Number used as ILOGICE2s: 0
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 32
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 150 0%
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 69 out of 500 13%
Number used as OLOGICE2s: 5
Number used as OLOGICE3s: 0
Number used as OSERDESE2s: 64
Number of PHASER_IN/PHASER_IN_PHYs: 4 out of 40 10%
Number used as PHASER_INs: 0
Number used as PHASER_IN_PHYs: 4
Number of LOCed PHASER_IN_PHYs: 4 out of 4 100%
Number of PHASER_OUT/PHASER_OUT_PHYs: 7 out of 40 17%
Number used as PHASER_OUTs: 0
Number used as PHASER_OUT_PHYs: 7
Number of LOCed PHASER_OUT_PHYs: 7 out of 7 100%
Number of BSCANs: 1 out of 4 25%
Number of BUFHCEs: 0 out of 168 0%
Number of BUFRs: 0 out of 40 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 1,540 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTXE2_CHANNELs: 0 out of 16 0%
Number of GTXE2_COMMONs: 0 out of 4 0%
Number of IBUFDS_GTE2s: 0 out of 8 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 1 out of 10 10%
Number of IN_FIFOs: 4 out of 40 10%
Number of LOCed IN_FIFOs: 4 out of 4 100%
Number of MMCME2_ADVs: 1 out of 10 10%
Number of LOCed MMCME2_ADVs: 1 out of 1 100%
Number of OUT_FIFOs: 7 out of 40 17%
Number of LOCed OUT_FIFOs: 7 out of 7 100%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 2 out of 10 20%
Number of LOCed PHASER_REFs: 2 out of 2 100%
Number of PHY_CONTROLs: 2 out of 10 20%
Number of LOCed PHY_CONTROLs: 2 out of 2 100%
Number of PLLE2_ADVs: 1 out of 10 10%
Number of LOCed PLLE2_ADVs: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 1 out of 1 100%
Average Fanout of Non-Clock Nets: 3.35
Peak Memory Usage: 2125 MB
Total REAL time to MAP completion: 5 mins 43 secs
Total CPU time to MAP completion: 5 mins 42 secs
Mapping completed.
See MAP report file "example_top_map.mrp" for details.
top/x300/coregen/ddr3_32bit/example_design/par/example_top_map.mrp
+2595
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top_map.ncd
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top_map.ngm
+3
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top_map.xrpt
+1064
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top_ngdbuild.xrpt
+227
View File
File diff suppressed because one or more lines are too long
top/x300/coregen/ddr3_32bit/example_design/par/example_top_pad.csv
+932
View File
@@ -0,0 +1,932 @@
#Release 14.4 - par P.49d (lin64)
#Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
#Tue Jan 22 18:32:42 2013
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: example_top_map.ncd
#OUTPUT FILE: example_top_pad.csv
#PART TYPE: xc7k410t
#SPEED GRADE: -2
#PACKAGE: ffg900
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,
A2,,,GND,,,,,,,,,,,,
A3,,OPAD,MGTXTXN3_118,UNUSED,,,,,,,,,,,
A4,,OPAD,MGTXTXP3_118,UNUSED,,,,,,,,,,,
A5,,,GND,,,,,,,,,,,,
A6,,,GND,,,,,,,,,,,,
A7,,IPAD,MGTXRXN3_118,UNUSED,,,,,,,,,,,
A8,,IPAD,MGTXRXP3_118,UNUSED,,,,,,,,,,,
A9,,,GND,,,,,,,,,,,,
A10,,,INIT_B_0,,,,,,,,,,,,
A11,,IOB33M,IO_L17P_T2_18,UNUSED,,18,,,,,,,,,
A12,,IOB33S,IO_L17N_T2_18,UNUSED,,18,,,,,,,,,
A13,,IOB33S,IO_L22N_T3_18,UNUSED,,18,,,,,,,,,
A14,,,GND,,,,,,,,,,,,
A15,,IOB33S,IO_L24N_T3_18,UNUSED,,18,,,,,,,,,
A16,,IOB33M,IO_L20P_T3_17,UNUSED,,17,,,,,,,,,
A17,,IOB33S,IO_L20N_T3_17,UNUSED,,17,,,,,,,,,
A18,,IOB33S,IO_L22N_T3_17,UNUSED,,17,,,,,,,,,
A19,,,VCCO_17,,,17,,,,,any******,,,,
A20,,IOB33M,IO_L21P_T3_DQS_17,UNUSED,,17,,,,,,,,,
A21,,IOB33S,IO_L21N_T3_DQS_17,UNUSED,,17,,,,,,,,,
A22,,IOB33S,IO_L23N_T3_17,UNUSED,,17,,,,,,,,,
A23,,IOB33S,IO_L1N_T0_16,UNUSED,,16,,,,,,,,,
A24,,,GND,,,,,,,,,,,,
A25,,IOB33M,IO_L10P_T1_16,UNUSED,,16,,,,,,,,,
A26,,IOB33S,IO_L10N_T1_16,UNUSED,,16,,,,,,,,,
A27,,IOB33S,IO_L7N_T1_16,UNUSED,,16,,,,,,,,,
A28,,IOB33S,IO_L9N_T1_DQS_16,UNUSED,,16,,,,,,,,,
A29,,,VCCO_16,,,16,,,,,any******,,,,
A30,,IOB33S,IO_L17N_T2_16,UNUSED,,16,,,,,,,,,
AA1,,,GND,,,,,,,,,,,,
AA2,,,GND,,,,,,,,,,,,
AA3,,IPAD,MGTXRXN0_115,UNUSED,,,,,,,,,,,
AA4,,IPAD,MGTXRXP0_115,UNUSED,,,,,,,,,,,
AA5,,,GND,,,,,,,,,,,,
AA6,,,GND,,,,,,,,,,,,
AA7,,,GND,,,,,,,,,,,,
AA8,ddr3_addr<12>,IOB18,IO_L2P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AA9,,,VCCO_33,,,33,,,,,1.50,,,,
AA10,ddr3_addr<7>,IOB18,IO_L5N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AA11,ddr3_addr<8>,IOB18,IO_L5P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AA12,ddr3_addr<14>,IOB18,IO_L1P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AA13,ddr3_addr<6>,IOB18,IO_L6P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AA14,,,GND,,,,,,,,,,,,
AA15,,IOB18M,IO_L20P_T3_32,UNUSED,,32,,,,,,,,,
AA16,,IOB18S,IO_L23N_T3_32,UNUSED,,32,,,,,,,,,
AA17,,IOB18M,IO_L23P_T3_32,UNUSED,,32,,,,,,,,,
AA18,,IOB18M,IO_L16P_T2_32,UNUSED,,32,,,,,,,,,
AA19,,,VCCO_32,,,32,,,,,any******,,,,
AA20,,IOB33M,IO_L6P_T0_12,UNUSED,,12,,,,,,,,,
AA21,,IOB33S,IO_L2N_T0_12,UNUSED,,12,,,,,,,,,
AA22,,IOB33M,IO_L4P_T0_12,UNUSED,,12,,,,,,,,,
AA23,,IOB33S,IO_L4N_T0_12,UNUSED,,12,,,,,,,,,
AA24,,,GND,,,,,,,,,,,,
AA25,,IOB33M,IO_L6P_T0_13,UNUSED,,13,,,,,,,,,
AA26,,IOB33S,IO_L1N_T0_13,UNUSED,,13,,,,,,,,,
AA27,,IOB33M,IO_L5P_T0_13,UNUSED,,13,,,,,,,,,
AA28,,IOB33S,IO_L3N_T0_DQS_13,UNUSED,,13,,,,,,,,,
AA29,,,VCCO_13,,,13,,,,,3.30,,,,
AA30,init_calib_complete,IOB33,IO_L8N_T1_13,OUTPUT,LVCMOS33,13,12,SLOW,,,,LOCATED,NO,NONE,
AB1,,,M2_0,,,,,,,,,,,,
AB2,,,M1_0,,,,,,,,,,,,
AB3,,,GND,,,,,,,,,,,,
AB4,,,GND,,,,,,,,,,,,
AB5,,,M0_0,,,,,,,,,,,,
AB6,,,VCCO_0,,,0,,,,,any******,,,,
AB7,,IOB18,IO_25_VRP_34,Termination Required,,34,,,TERMINATION,,,,,,
AB8,ddr3_addr<11>,IOB18,IO_L2N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AB9,ddr3_ck_p<0>,IOB18M,IO_L3P_T0_DQS_33,OUTPUT,DIFF_SSTL15,33,,FAST,,,,LOCATED,YES,NONE,
AB10,ddr3_addr<4>,IOB18,IO_L7P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AB11,,,GND,,,,,,,,,,,,
AB12,ddr3_addr<13>,IOB18,IO_L1N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AB13,ddr3_addr<5>,IOB18,IO_L6N_T0_VREF_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AB14,,IOB18,IO_25_VRP_32,UNUSED,,32,,,,,,,,,
AB15,,IOB18S,IO_L20N_T3_32,UNUSED,,32,,,,,,,,,
AB16,,,VCCO_32,,,32,,,,,any******,,,,
AB17,,IOB18M,IO_L18P_T2_32,UNUSED,,32,,,,,,,,,
AB18,,IOB18S,IO_L16N_T2_32,UNUSED,,32,,,,,,,,,
AB19,,IOB18M,IO_L17P_T2_32,UNUSED,,32,,,,,,,,,
AB20,,IOB33S,IO_L6N_T0_VREF_12,UNUSED,,12,,,,,,,,,
AB21,,,GND,,,,,,,,,,,,
AB22,,IOB33M,IO_L3P_T0_DQS_12,UNUSED,,12,,,,,,,,,
AB23,,IOB33S,IO_L3N_T0_DQS_12,UNUSED,,12,,,,,,,,,
AB24,,IOB33M,IO_L7P_T1_12,UNUSED,,12,,,,,,,,,
AB25,,IOB33S,IO_L6N_T0_VREF_13,UNUSED,,13,,,,,,,,,
AB26,,,VCCO_13,,,13,,,,,3.30,,,,
AB27,,IOB33M,IO_L12P_T1_MRCC_13,UNUSED,,13,,,,,,,,,
AB28,,IOB33S,IO_L5N_T0_13,UNUSED,,13,,,,,,,,,
AB29,,IOB33M,IO_L10P_T1_13,UNUSED,,13,,,,,,,,,
AB30,,IOB33S,IO_L10N_T1_13,UNUSED,,13,,,,,,,,,
AC1,ddr3_dq<2>,IOB18,IO_L2N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AC2,ddr3_dq<1>,IOB18,IO_L2P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AC3,,,VCCO_34,,,34,,,,,1.50,,,,
AC4,ddr3_dq<4>,IOB18,IO_L4N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AC5,ddr3_dq<3>,IOB18,IO_L4P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AC6,,IOB18,IO_0_VRN_34,Termination Required,,34,,,TERMINATION,,,,,,
AC7,ddr3_dq<7>,IOB18,IO_L6P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AC8,,,GND,,,,,,,,,,,,
AC9,ddr3_ck_n<0>,IOB18S,IO_L3N_T0_DQS_33,OUTPUT,DIFF_SSTL15,33,,FAST,,,,LOCATED,YES,NONE,
AC10,ddr3_addr<3>,IOB18,IO_L7N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AC11,ddr3_ba<2>,IOB18,IO_L9N_T1_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AC12,ddr3_addr<0>,IOB18,IO_L9P_T1_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AC13,,,VCCO_33,,,33,,,,,1.50,,,,
AC14,,IOB18M,IO_L22P_T3_32,UNUSED,,32,,,,,,,,,
AC15,,IOB18S,IO_L21N_T3_DQS_32,UNUSED,,32,,,,,,,,,
AC16,,IOB18M,IO_L21P_T3_DQS_32,UNUSED,,32,,,,,,,,,
AC17,,IOB18S,IO_L18N_T2_32,UNUSED,,32,,,,,,,,,
AC18,,,GND,,,,,,,,,,,,
AC19,,IOB18S,IO_L17N_T2_32,UNUSED,,32,,,,,,,,,
AC20,,IOB33M,IO_L5P_T0_12,UNUSED,,12,,,,,,,,,
AC21,,IOB33S,IO_L5N_T0_12,UNUSED,,12,,,,,,,,,
AC22,,IOB33M,IO_L8P_T1_12,UNUSED,,12,,,,,,,,,
AC23,,,VCCO_12,,,12,,,,,any******,,,,
AC24,,IOB33M,IO_L9P_T1_DQS_12,UNUSED,,12,,,,,,,,,
AC25,,IOB33S,IO_L7N_T1_12,UNUSED,,12,,,,,,,,,
AC26,,IOB33M,IO_L19P_T3_13,UNUSED,,13,,,,,,,,,
AC27,,IOB33S,IO_L12N_T1_MRCC_13,UNUSED,,13,,,,,,,,,
AC28,,,GND,,,,,,,,,,,,
AC29,sys_rst,IOB33,IO_L7P_T1_13,INPUT,LVCMOS33,13,,,PULLUP,NONE,,LOCATED,NO,NONE,
AC30,,IOB33S,IO_L7N_T1_13,UNUSED,,13,,,,,,,,,
AD1,ddr3_dqs_n<0>,IOB18S,IO_L3N_T0_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AD2,ddr3_dqs_p<0>,IOB18M,IO_L3P_T0_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AD3,ddr3_dq<0>,IOB18,IO_L1N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AD4,ddr3_dm<0>,IOB18,IO_L1P_T0_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
AD5,,,GND,,,,,,,,,,,,
AD6,ddr3_dq<5>,IOB18,IO_L5P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AD7,,IOB18S,IO_L6N_T0_VREF_34,VREF Required,,34,,,,,0.75,,,,
AD8,ddr3_addr<2>,IOB18,IO_L8P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AD9,ddr3_ba<1>,IOB18,IO_L10P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AD10,,,VCCO_33,,,33,,,,,1.50,,,,
AD11,ddr3_cs_n<0>,IOB18,IO_L12N_T1_MRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AD12,ddr3_we_n,IOB18,IO_L12P_T1_MRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AD13,,IOB18,IO_25_VRP_33,UNUSED,,33,,,,,,,,,
AD14,,IOB18S,IO_L22N_T3_32,UNUSED,,32,,,,,,,,,
AD15,,,GND,,,,,,,,,,,,
AD16,,IOB18S,IO_L14N_T2_SRCC_32,UNUSED,,32,,,,,,,,,
AD17,,IOB18M,IO_L14P_T2_SRCC_32,UNUSED,,32,,,,,,,,,
AD18,,IOB18M,IO_L13P_T2_MRCC_32,UNUSED,,32,,,,,,,,,
AD19,,IOB18M,IO_L10P_T1_32,UNUSED,,32,,,,,,,,,
AD20,,,VCCO_12,,,12,,,,,any******,,,,
AD21,,IOB33M,IO_L10P_T1_12,UNUSED,,12,,,,,,,,,
AD22,,IOB33S,IO_L8N_T1_12,UNUSED,,12,,,,,,,,,
AD23,,IOB33M,IO_L12P_T1_MRCC_12,UNUSED,,12,,,,,,,,,
AD24,,IOB33S,IO_L9N_T1_DQS_12,UNUSED,,12,,,,,,,,,
AD25,,,GND,,,,,,,,,,,,
AD26,,IOB33S,IO_L19N_T3_VREF_13,UNUSED,,13,,,,,,,,,
AD27,,IOB33M,IO_L11P_T1_SRCC_13,UNUSED,,13,,,,,,,,,
AD28,,IOB33S,IO_L11N_T1_SRCC_13,UNUSED,,13,,,,,,,,,
AD29,,IOB33M,IO_L9P_T1_DQS_13,UNUSED,,13,,,,,,,,,
AD30,,,VCCO_13,,,13,,,,,3.30,,,,
AE1,ddr3_dq<9>,IOB18,IO_L8P_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AE2,,,GND,,,,,,,,,,,,
AE3,ddr3_dq<12>,IOB18,IO_L10N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AE4,ddr3_dq<11>,IOB18,IO_L10P_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AE5,ddr3_dq<13>,IOB18,IO_L11P_T1_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AE6,ddr3_dq<6>,IOB18,IO_L5N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AE7,,,VCCO_34,,,34,,,,,1.50,,,,
AE8,ddr3_addr<1>,IOB18,IO_L8N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AE9,ddr3_ba<0>,IOB18,IO_L10N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AE10,sys_clk_i,IOB18,IO_L14P_T2_SRCC_33,INPUT,LVCMOS15,33,,,,NONE,,LOCATED,NO,NONE,
AE11,ddr3_ras_n,IOB18,IO_L11P_T1_SRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AE12,,,GND,,,,,,,,,,,,
AE13,,IOB18M,IO_L19P_T3_33,UNUSED,,33,,,,,,,,,
AE14,,IOB18S,IO_L19N_T3_VREF_32,UNUSED,,32,,,,,,,,,
AE15,,IOB18M,IO_L19P_T3_32,UNUSED,,32,,,,,,,,,
AE16,,IOB18M,IO_L6P_T0_32,UNUSED,,32,,,,,,,,,
AE17,,,VCCO_32,,,32,,,,,any******,,,,
AE18,,IOB18S,IO_L13N_T2_MRCC_32,UNUSED,,32,,,,,,,,,
AE19,,IOB18S,IO_L10N_T1_32,UNUSED,,32,,,,,,,,,
AE20,,IOB33,IO_25_12,UNUSED,,12,,,,,,,,,
AE21,,IOB33S,IO_L10N_T1_12,UNUSED,,12,,,,,,,,,
AE22,,,GND,,,,,,,,,,,,
AE23,,IOB33M,IO_L11P_T1_SRCC_12,UNUSED,,12,,,,,,,,,
AE24,,IOB33S,IO_L12N_T1_MRCC_12,UNUSED,,12,,,,,,,,,
AE25,,IOB33M,IO_L16P_T2_12,UNUSED,,12,,,,,,,,,
AE26,,IOB33,IO_25_13,UNUSED,,13,,,,,,,,,
AE27,,,VCCO_13,,,13,,,,,3.30,,,,
AE28,,IOB33M,IO_L14P_T2_SRCC_13,UNUSED,,13,,,,,,,,,
AE29,,IOB33S,IO_L9N_T1_DQS_13,UNUSED,,13,,,,,,,,,
AE30,,IOB33M,IO_L16P_T2_13,UNUSED,,13,,,,,,,,,
AF1,ddr3_dq<10>,IOB18,IO_L8N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AF2,ddr3_dq<8>,IOB18,IO_L7N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AF3,ddr3_dm<1>,IOB18,IO_L7P_T1_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
AF4,,,VCCO_34,,,34,,,,,1.50,,,,
AF5,ddr3_dq<14>,IOB18,IO_L11N_T1_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AF6,ddr3_dq<15>,IOB18,IO_L12P_T1_MRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AF7,ddr3_dq<24>,IOB18,IO_L20P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AF8,ddr3_dm<3>,IOB18,IO_L19P_T3_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
AF9,,,GND,,,,,,,,,,,,
AF10,,IOB18S,IO_L14N_T2_SRCC_33,UNUSED,,33,,,,,,,,,
AF11,ddr3_cas_n,IOB18,IO_L11N_T1_SRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AF12,,IOB18M,IO_L23P_T3_33,UNUSED,,33,,,,,,,,,
AF13,,IOB18S,IO_L19N_T3_VREF_33,UNUSED,,33,,,,,,,,,
AF14,,,VCCO_32,,,32,,,,,any******,,,,
AF15,,IOB18M,IO_L4P_T0_32,UNUSED,,32,,,,,,,,,
AF16,,IOB18S,IO_L6N_T0_VREF_32,UNUSED,,32,,,,,,,,,
AF17,,IOB18M,IO_L12P_T1_MRCC_32,UNUSED,,32,,,,,,,,,
AF18,,IOB18M,IO_L11P_T1_SRCC_32,UNUSED,,32,,,,,,,,,
AF19,,,GND,,,,,,,,,,,,
AF20,,IOB33M,IO_L19P_T3_12,UNUSED,,12,,,,,,,,,
AF21,,IOB33S,IO_L19N_T3_VREF_12,UNUSED,,12,,,,,,,,,
AF22,,IOB33M,IO_L13P_T2_MRCC_12,UNUSED,,12,,,,,,,,,
AF23,,IOB33S,IO_L11N_T1_SRCC_12,UNUSED,,12,,,,,,,,,
AF24,,,VCCO_12,,,12,,,,,any******,,,,
AF25,,IOB33S,IO_L16N_T2_12,UNUSED,,12,,,,,,,,,
AF26,,IOB33M,IO_L23P_T3_13,UNUSED,,13,,,,,,,,,
AF27,,IOB33S,IO_L23N_T3_13,UNUSED,,13,,,,,,,,,
AF28,,IOB33S,IO_L14N_T2_SRCC_13,UNUSED,,13,,,,,,,,,
AF29,,,GND,,,,,,,,,,,,
AF30,,IOB33S,IO_L16N_T2_13,UNUSED,,13,,,,,,,,,
AG1,,,VCCO_34,,,34,,,,,1.50,,,,
AG2,ddr3_dqs_p<2>,IOB18M,IO_L15P_T2_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AG3,ddr3_dqs_n<1>,IOB18S,IO_L9N_T1_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AG4,ddr3_dqs_p<1>,IOB18M,IO_L9P_T1_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AG5,ddr3_reset_n,IOB18,IO_L12N_T1_MRCC_34,OUTPUT,LVCMOS15,34,12,FAST,,,,LOCATED,NO,NONE,
AG6,,,GND,,,,,,,,,,,,
AG7,ddr3_dq<25>,IOB18,IO_L20N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AG8,,IOB18S,IO_L19N_T3_VREF_34,VREF Required,,34,,,,,0.75,,,,
AG9,,IOB18M,IO_L16P_T2_33,UNUSED,,33,,,,,,,,,
AG10,,IOB18M,IO_L13P_T2_MRCC_33,UNUSED,,33,,,,,,,,,
AG11,,,VCCO_33,,,33,,,,,1.50,,,,
AG12,,IOB18S,IO_L23N_T3_33,UNUSED,,33,,,,,,,,,
AG13,,IOB18M,IO_L24P_T3_33,UNUSED,,33,,,,,,,,,
AG14,,IOB18S,IO_L4N_T0_32,UNUSED,,32,,,,,,,,,
AG15,,IOB18M,IO_L2P_T0_32,UNUSED,,32,,,,,,,,,
AG16,,,GND,,,,,,,,,,,,
AG17,,IOB18S,IO_L12N_T1_MRCC_32,UNUSED,,32,,,,,,,,,
AG18,,IOB18S,IO_L11N_T1_SRCC_32,UNUSED,,32,,,,,,,,,
AG19,,IOB18M,IO_L8P_T1_32,UNUSED,,32,,,,,,,,,
AG20,,IOB33M,IO_L22P_T3_12,UNUSED,,12,,,,,,,,,
AG21,,,VCCO_12,,,12,,,,,any******,,,,
AG22,,IOB33M,IO_L20P_T3_12,UNUSED,,12,,,,,,,,,
AG23,,IOB33S,IO_L13N_T2_MRCC_12,UNUSED,,12,,,,,,,,,
AG24,,IOB33M,IO_L14P_T2_SRCC_12,UNUSED,,12,,,,,,,,,
AG25,,IOB33M,IO_L18P_T2_12,UNUSED,,12,,,,,,,,,
AG26,,,GND,,,,,,,,,,,,
AG27,,IOB33M,IO_L21P_T3_DQS_13,UNUSED,,13,,,,,,,,,
AG28,,IOB33S,IO_L21N_T3_DQS_13,UNUSED,,13,,,,,,,,,
AG29,,IOB33M,IO_L13P_T2_MRCC_13,UNUSED,,13,,,,,,,,,
AG30,,IOB33M,IO_L18P_T2_13,UNUSED,,13,,,,,,,,,
AH1,ddr3_dqs_n<2>,IOB18S,IO_L15N_T2_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AH2,ddr3_dq<19>,IOB18,IO_L16P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AH3,,,GND,,,,,,,,,,,,
AH4,ddr3_dm<2>,IOB18,IO_L13P_T2_MRCC_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
AH5,ddr3_dq<18>,IOB18,IO_L14N_T2_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AH6,ddr3_dq<17>,IOB18,IO_L14P_T2_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AH7,ddr3_dqs_p<3>,IOB18M,IO_L21P_T3_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AH8,,,VCCO_34,,,34,,,,,1.50,,,,
AH9,,IOB18S,IO_L16N_T2_33,UNUSED,,33,,,,,,,,,
AH10,,IOB18S,IO_L13N_T2_MRCC_33,UNUSED,,33,,,,,,,,,
AH11,,IOB18M,IO_L18P_T2_33,UNUSED,,33,,,,,,,,,
AH12,,IOB18S,IO_L24N_T3_33,UNUSED,,33,,,,,,,,,
AH13,,,GND,,,,,,,,,,,,
AH14,,IOB18M,IO_L21P_T3_DQS_33,UNUSED,,33,,,,,,,,,
AH15,,IOB18S,IO_L2N_T0_32,UNUSED,,32,,,,,,,,,
AH16,,IOB18M,IO_L3P_T0_DQS_32,UNUSED,,32,,,,,,,,,
AH17,,IOB18M,IO_L5P_T0_32,UNUSED,,32,,,,,,,,,
AH18,,,VCCO_32,,,32,,,,,any******,,,,
AH19,,IOB18S,IO_L8N_T1_32,UNUSED,,32,,,,,,,,,
AH20,,IOB33S,IO_L22N_T3_12,UNUSED,,12,,,,,,,,,
AH21,,IOB33M,IO_L23P_T3_12,UNUSED,,12,,,,,,,,,
AH22,,IOB33S,IO_L20N_T3_12,UNUSED,,12,,,,,,,,,
AH23,,,GND,,,,,,,,,,,,
AH24,,IOB33S,IO_L14N_T2_SRCC_12,UNUSED,,12,,,,,,,,,
AH25,,IOB33S,IO_L18N_T2_12,UNUSED,,12,,,,,,,,,
AH26,,IOB33M,IO_L22P_T3_13,UNUSED,,13,,,,,,,,,
AH27,,IOB33S,IO_L22N_T3_13,UNUSED,,13,,,,,,,,,
AH28,,,VCCO_13,,,13,,,,,3.30,,,,
AH29,,IOB33S,IO_L13N_T2_MRCC_13,UNUSED,,13,,,,,,,,,
AH30,,IOB33S,IO_L18N_T2_13,UNUSED,,13,,,,,,,,,
AJ1,ddr3_dq<21>,IOB18,IO_L17P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ2,ddr3_dq<20>,IOB18,IO_L16N_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ3,ddr3_dq<23>,IOB18,IO_L18P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ4,ddr3_dq<16>,IOB18,IO_L13N_T2_MRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ5,,,VCCO_34,,,34,,,,,1.50,,,,
AJ6,ddr3_dq<26>,IOB18,IO_L22P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ7,ddr3_dqs_n<3>,IOB18S,IO_L21N_T3_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
AJ8,ddr3_dq<28>,IOB18,IO_L23P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AJ9,ddr3_cke<0>,IOB18,IO_L15P_T2_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AJ10,,,GND,,,,,,,,,,,,
AJ11,,IOB18S,IO_L18N_T2_33,UNUSED,,33,,,,,,,,,
AJ12,,IOB18S,IO_L22N_T3_33,UNUSED,,33,,,,,,,,,
AJ13,,IOB18M,IO_L22P_T3_33,UNUSED,,33,,,,,,,,,
AJ14,,IOB18S,IO_L21N_T3_DQS_33,UNUSED,,33,,,,,,,,,
AJ15,,,VCCO_32,,,32,,,,,any******,,,,
AJ16,,IOB18S,IO_L3N_T0_DQS_32,UNUSED,,32,,,,,,,,,
AJ17,,IOB18S,IO_L5N_T0_32,UNUSED,,32,,,,,,,,,
AJ18,,IOB18M,IO_L9P_T1_DQS_32,UNUSED,,32,,,,,,,,,
AJ19,,IOB18M,IO_L7P_T1_32,UNUSED,,32,,,,,,,,,
AJ20,,,GND,,,,,,,,,,,,
AJ21,,IOB33S,IO_L23N_T3_12,UNUSED,,12,,,,,,,,,
AJ22,,IOB33M,IO_L21P_T3_DQS_12,UNUSED,,12,,,,,,,,,
AJ23,,IOB33S,IO_L21N_T3_DQS_12,UNUSED,,12,,,,,,,,,
AJ24,,IOB33M,IO_L15P_T2_DQS_12,UNUSED,,12,,,,,,,,,
AJ25,,,VCCO_13,,,13,,,,,3.30,,,,
AJ26,,IOB33M,IO_L24P_T3_13,UNUSED,,13,,,,,,,,,
AJ27,,IOB33M,IO_L20P_T3_13,UNUSED,,13,,,,,,,,,
AJ28,,IOB33M,IO_L17P_T2_13,UNUSED,,13,,,,,,,,,
AJ29,,IOB33S,IO_L17N_T2_13,UNUSED,,13,,,,,,,,,
AJ30,,,GND,,,,,,,,,,,,
AK1,ddr3_dq<22>,IOB18,IO_L17N_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AK2,,,VCCO_34,,,34,,,,,1.50,,,,
AK3,,IOB18S,IO_L18N_T2_34,UNUSED,,34,,,,,,,,,
AK4,ddr3_dq<31>,IOB18,IO_L24N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AK5,ddr3_dq<30>,IOB18,IO_L24P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AK6,ddr3_dq<27>,IOB18,IO_L22N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AK7,,,GND,,,,,,,,,,,,
AK8,ddr3_dq<29>,IOB18,IO_L23N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
AK9,ddr3_odt<0>,IOB18,IO_L15N_T2_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
AK10,,IOB18S,IO_L17N_T2_33,UNUSED,,33,,,,,,,,,
AK11,,IOB18M,IO_L17P_T2_33,UNUSED,,33,,,,,,,,,
AK12,,,VCCO_33,,,33,,,,,1.50,,,,
AK13,,IOB18S,IO_L20N_T3_33,UNUSED,,33,,,,,,,,,
AK14,,IOB18M,IO_L20P_T3_33,UNUSED,,33,,,,,,,,,
AK15,,IOB18S,IO_L1N_T0_32,UNUSED,,32,,,,,,,,,
AK16,,IOB18M,IO_L1P_T0_32,UNUSED,,32,,,,,,,,,
AK17,,,GND,,,,,,,,,,,,
AK18,,IOB18S,IO_L9N_T1_DQS_32,UNUSED,,32,,,,,,,,,
AK19,,IOB18S,IO_L7N_T1_32,UNUSED,,32,,,,,,,,,
AK20,,IOB33M,IO_L24P_T3_12,UNUSED,,12,,,,,,,,,
AK21,,IOB33S,IO_L24N_T3_12,UNUSED,,12,,,,,,,,,
AK22,,,VCCO_12,,,12,,,,,any******,,,,
AK23,,IOB33M,IO_L17P_T2_12,UNUSED,,12,,,,,,,,,
AK24,,IOB33S,IO_L17N_T2_12,UNUSED,,12,,,,,,,,,
AK25,,IOB33S,IO_L15N_T2_DQS_12,UNUSED,,12,,,,,,,,,
AK26,,IOB33S,IO_L24N_T3_13,UNUSED,,13,,,,,,,,,
AK27,,,GND,,,,,,,,,,,,
AK28,,IOB33S,IO_L20N_T3_13,UNUSED,,13,,,,,,,,,
AK29,,IOB33M,IO_L15P_T2_DQS_13,UNUSED,,13,,,,,,,,,
AK30,,IOB33S,IO_L15N_T2_DQS_13,UNUSED,,13,,,,,,,,,
B1,,OPAD,MGTXTXN2_118,UNUSED,,,,,,,,,,,
B2,,OPAD,MGTXTXP2_118,UNUSED,,,,,,,,,,,
B3,,,MGTAVTT,,,,,,,,,,,,
B4,,,GND,,,,,,,,,,,,
B5,,IPAD,MGTXRXN2_118,UNUSED,,,,,,,,,,,
B6,,IPAD,MGTXRXP2_118,UNUSED,,,,,,,,,,,
B7,,,MGTAVCC,,,,,,,,,,,,
B8,,,GND,,,,,,,,,,,,
B9,,,GND,,,,,,,,,,,,
B10,,,CCLK_0,,,,,,,,,,,,
B11,,,GND,,,,,,,,,,,,
B12,,IOB33S,IO_L15N_T2_DQS_18,UNUSED,,18,,,,,,,,,
B13,,IOB33M,IO_L22P_T3_18,UNUSED,,18,,,,,,,,,
B14,,IOB33M,IO_L24P_T3_18,UNUSED,,18,,,,,,,,,
B15,,IOB33S,IO_L23N_T3_18,UNUSED,,18,,,,,,,,,
B16,,,VCCO_17,,,17,,,,,any******,,,,
B17,,IOB33S,IO_L17N_T2_17,UNUSED,,17,,,,,,,,,
B18,,IOB33M,IO_L22P_T3_17,UNUSED,,17,,,,,,,,,
B19,,IOB33S,IO_L24N_T3_17,UNUSED,,17,,,,,,,,,
B20,,IOB33S,IO_L19N_T3_VREF_17,UNUSED,,17,,,,,,,,,
B21,,,GND,,,,,,,,,,,,
B22,,IOB33M,IO_L23P_T3_17,UNUSED,,17,,,,,,,,,
B23,,IOB33M,IO_L1P_T0_16,UNUSED,,16,,,,,,,,,
B24,,IOB33S,IO_L8N_T1_16,UNUSED,,16,,,,,,,,,
B25,,IOB33S,IO_L12N_T1_MRCC_16,UNUSED,,16,,,,,,,,,
B26,,,VCCO_16,,,16,,,,,any******,,,,
B27,,IOB33M,IO_L7P_T1_16,UNUSED,,16,,,,,,,,,
B28,,IOB33M,IO_L9P_T1_DQS_16,UNUSED,,16,,,,,,,,,
B29,,IOB33S,IO_L15N_T2_DQS_16,UNUSED,,16,,,,,,,,,
B30,,IOB33M,IO_L17P_T2_16,UNUSED,,16,,,,,,,,,
C1,,,GND,,,,,,,,,,,,
C2,,,GND,,,,,,,,,,,,
C3,,OPAD,MGTXTXN1_118,UNUSED,,,,,,,,,,,
C4,,OPAD,MGTXTXP1_118,UNUSED,,,,,,,,,,,
C5,,,MGTAVTT,,,,,,,,,,,,
C6,,,GND,,,,,,,,,,,,
C7,,IPAD,MGTREFCLK0N_118,UNUSED,,,,,,,,,,,
C8,,IPAD,MGTREFCLK0P_118,UNUSED,,,,,,,,,,,
C9,,,GND,,,,,,,,,,,,
C10,,,VCCBATT_0,,,,,,,,,,,,
C11,,IOB33S,IO_L18N_T2_18,UNUSED,,18,,,,,,,,,
C12,,IOB33M,IO_L15P_T2_DQS_18,UNUSED,,18,,,,,,,,,
C13,,,VCCO_18,,,18,,,,,any******,,,,
C14,,IOB33S,IO_L21N_T3_DQS_18,UNUSED,,18,,,,,,,,,
C15,,IOB33M,IO_L23P_T3_18,UNUSED,,18,,,,,,,,,
C16,,IOB33S,IO_L15N_T2_DQS_17,UNUSED,,17,,,,,,,,,
C17,,IOB33M,IO_L17P_T2_17,UNUSED,,17,,,,,,,,,
C18,,,GND,,,,,,,,,,,,
C19,,IOB33M,IO_L24P_T3_17,UNUSED,,17,,,,,,,,,
C20,,IOB33M,IO_L19P_T3_17,UNUSED,,17,,,,,,,,,
C21,,IOB33S,IO_L8N_T1_17,UNUSED,,17,,,,,,,,,
C22,,IOB33S,IO_L10N_T1_17,UNUSED,,17,,,,,,,,,
C23,,,VCCO_16,,,16,,,,,any******,,,,
C24,,IOB33M,IO_L8P_T1_16,UNUSED,,16,,,,,,,,,
C25,,IOB33M,IO_L12P_T1_MRCC_16,UNUSED,,16,,,,,,,,,
C26,,IOB33S,IO_L11N_T1_SRCC_16,UNUSED,,16,,,,,,,,,
C27,,IOB33S,IO_L13N_T2_MRCC_16,UNUSED,,16,,,,,,,,,
C28,,,GND,,,,,,,,,,,,
C29,,IOB33M,IO_L15P_T2_DQS_16,UNUSED,,16,,,,,,,,,
C30,,IOB33S,IO_L16N_T2_16,UNUSED,,16,,,,,,,,,
D1,,OPAD,MGTXTXN0_118,UNUSED,,,,,,,,,,,
D2,,OPAD,MGTXTXP0_118,UNUSED,,,,,,,,,,,
D3,,,MGTAVTT,,,,,,,,,,,,
D4,,,GND,,,,,,,,,,,,
D5,,IPAD,MGTXRXN1_118,UNUSED,,,,,,,,,,,
D6,,IPAD,MGTXRXP1_118,UNUSED,,,,,,,,,,,
D7,,,MGTAVCC,,,,,,,,,,,,
D8,,,GND,,,,,,,,,,,,
D9,,,GND,,,,,,,,,,,,
D10,,,VCCO_18,,,18,,,,,any******,,,,
D11,,IOB33M,IO_L18P_T2_18,UNUSED,,18,,,,,,,,,
D12,,IOB33M,IO_L13P_T2_MRCC_18,UNUSED,,18,,,,,,,,,
D13,,IOB33S,IO_L13N_T2_MRCC_18,UNUSED,,18,,,,,,,,,
D14,,IOB33M,IO_L21P_T3_DQS_18,UNUSED,,18,,,,,,,,,
D15,,,GND,,,,,,,,,,,,
D16,,IOB33M,IO_L15P_T2_DQS_17,UNUSED,,17,,,,,,,,,
D17,,IOB33M,IO_L13P_T2_MRCC_17,UNUSED,,17,,,,,,,,,
D18,,IOB33S,IO_L13N_T2_MRCC_17,UNUSED,,17,,,,,,,,,
D19,,IOB33S,IO_L14N_T2_SRCC_17,UNUSED,,17,,,,,,,,,
D20,,,VCCO_17,,,17,,,,,any******,,,,
D21,,IOB33M,IO_L8P_T1_17,UNUSED,,17,,,,,,,,,
D22,,IOB33M,IO_L10P_T1_17,UNUSED,,17,,,,,,,,,
D23,,IOB33S,IO_L2N_T0_16,UNUSED,,16,,,,,,,,,
D24,,IOB33S,IO_L4N_T0_16,UNUSED,,16,,,,,,,,,
D25,,,GND,,,,,,,,,,,,
D26,,IOB33M,IO_L11P_T1_SRCC_16,UNUSED,,16,,,,,,,,,
D27,,IOB33M,IO_L13P_T2_MRCC_16,UNUSED,,16,,,,,,,,,
D28,,IOB33S,IO_L14N_T2_SRCC_16,UNUSED,,16,,,,,,,,,
D29,,IOB33M,IO_L16P_T2_16,UNUSED,,16,,,,,,,,,
D30,,,VCCO_16,,,16,,,,,any******,,,,
E1,,,GND,,,,,,,,,,,,
E2,,,GND,,,,,,,,,,,,
E3,,IPAD,MGTXRXN0_118,UNUSED,,,,,,,,,,,
E4,,IPAD,MGTXRXP0_118,UNUSED,,,,,,,,,,,
E5,,,MGTAVTT,,,,,,,,,,,,
E6,,,GND,,,,,,,,,,,,
E7,,IPAD,MGTREFCLK1N_118,UNUSED,,,,,,,,,,,
E8,,IPAD,MGTREFCLK1P_118,UNUSED,,,,,,,,,,,
E9,,,GND,,,,,,,,,,,,
E10,,,TCK_0,,,,,,,,,,,,
E11,,IOB33S,IO_L16N_T2_18,UNUSED,,18,,,,,,,,,
E12,,,GND,,,,,,,,,,,,
E13,,IOB33S,IO_L14N_T2_SRCC_18,UNUSED,,18,,,,,,,,,
E14,,IOB33M,IO_L20P_T3_18,UNUSED,,18,,,,,,,,,
E15,,IOB33S,IO_L20N_T3_18,UNUSED,,18,,,,,,,,,
E16,,IOB33S,IO_L19N_T3_VREF_18,UNUSED,,18,,,,,,,,,
E17,,,VCCO_17,,,17,,,,,any******,,,,
E18,,IOB33,IO_25_17,UNUSED,,17,,,,,,,,,
E19,,IOB33M,IO_L14P_T2_SRCC_17,UNUSED,,17,,,,,,,,,
E20,,IOB33S,IO_L12N_T1_MRCC_17,UNUSED,,17,,,,,,,,,
E21,,IOB33S,IO_L11N_T1_SRCC_17,UNUSED,,17,,,,,,,,,
E22,,,GND,,,,,,,,,,,,
E23,,IOB33M,IO_L2P_T0_16,UNUSED,,16,,,,,,,,,
E24,,IOB33M,IO_L4P_T0_16,UNUSED,,16,,,,,,,,,
E25,,IOB33S,IO_L3N_T0_DQS_16,UNUSED,,16,,,,,,,,,
E26,,IOB33S,IO_L5N_T0_16,UNUSED,,16,,,,,,,,,
E27,,,VCCO_16,,,16,,,,,any******,,,,
E28,,IOB33M,IO_L14P_T2_SRCC_16,UNUSED,,16,,,,,,,,,
E29,,IOB33M,IO_L18P_T2_16,UNUSED,,16,,,,,,,,,
E30,,IOB33S,IO_L18N_T2_16,UNUSED,,16,,,,,,,,,
F1,,OPAD,MGTXTXN3_117,UNUSED,,,,,,,,,,,
F2,,OPAD,MGTXTXP3_117,UNUSED,,,,,,,,,,,
F3,,,MGTAVTT,,,,,,,,,,,,
F4,,,GND,,,,,,,,,,,,
F5,,IPAD,MGTXRXN3_117,UNUSED,,,,,,,,,,,
F6,,IPAD,MGTXRXP3_117,UNUSED,,,,,,,,,,,
F7,,,MGTAVCC,,,,,,,,,,,,
F8,,,GND,,,,,,,,,,,,
F9,,,GND,,,,,,,,,,,,
F10,,,TMS_0,,,,,,,,,,,,
F11,,IOB33M,IO_L16P_T2_18,UNUSED,,18,,,,,,,,,
F12,,IOB33M,IO_L14P_T2_SRCC_18,UNUSED,,18,,,,,,,,,
F13,,IOB33S,IO_L12N_T1_MRCC_18,UNUSED,,18,,,,,,,,,
F14,,,VCCO_18,,,18,,,,,any******,,,,
F15,,IOB33M,IO_L19P_T3_18,UNUSED,,18,,,,,,,,,
F16,,IOB33,IO_25_18,UNUSED,,18,,,,,,,,,
F17,,IOB33S,IO_L18N_T2_17,UNUSED,,17,,,,,,,,,
F18,,IOB33S,IO_L16N_T2_17,UNUSED,,17,,,,,,,,,
F19,,,GND,,,,,,,,,,,,
F20,,IOB33M,IO_L12P_T1_MRCC_17,UNUSED,,17,,,,,,,,,
F21,,IOB33M,IO_L11P_T1_SRCC_17,UNUSED,,17,,,,,,,,,
F22,,IOB33S,IO_L9N_T1_DQS_17,UNUSED,,17,,,,,,,,,
F23,,IOB33,IO_0_16,UNUSED,,16,,,,,,,,,
F24,,,VCCO_16,,,16,,,,,any******,,,,
F25,,IOB33M,IO_L3P_T0_DQS_16,UNUSED,,16,,,,,,,,,
F26,,IOB33M,IO_L5P_T0_16,UNUSED,,16,,,,,,,,,
F27,,IOB33S,IO_L21N_T3_DQS_16,UNUSED,,16,,,,,,,,,
F28,,IOB33S,IO_L20N_T3_16,UNUSED,,16,,,,,,,,,
F29,,,GND,,,,,,,,,,,,
F30,,IOB33S,IO_L22N_T3_16,UNUSED,,16,,,,,,,,,
G1,,,GND,,,,,,,,,,,,
G2,,,GND,,,,,,,,,,,,
G3,,IPAD,MGTXRXN2_117,UNUSED,,,,,,,,,,,
G4,,IPAD,MGTXRXP2_117,UNUSED,,,,,,,,,,,
G5,,,MGTAVTT,,,,,,,,,,,,
G6,,,GND,,,,,,,,,,,,
G7,,IPAD,MGTREFCLK0N_117,UNUSED,,,,,,,,,,,
G8,,IPAD,MGTREFCLK0P_117,UNUSED,,,,,,,,,,,
G9,,,GND,,,,,,,,,,,,
G10,,,TDO_0,,,,,,,,,,,,
G11,,,VCCO_18,,,18,,,,,any******,,,,
G12,,IOB33,IO_0_18,UNUSED,,18,,,,,,,,,
G13,,IOB33M,IO_L12P_T1_MRCC_18,UNUSED,,18,,,,,,,,,
G14,,IOB33S,IO_L11N_T1_SRCC_18,UNUSED,,18,,,,,,,,,
G15,,IOB33S,IO_L7N_T1_18,UNUSED,,18,,,,,,,,,
G16,,,GND,,,,,,,,,,,,
G17,,IOB33M,IO_L18P_T2_17,UNUSED,,17,,,,,,,,,
G18,,IOB33M,IO_L16P_T2_17,UNUSED,,17,,,,,,,,,
G19,,IOB33,IO_0_17,UNUSED,,17,,,,,,,,,
G20,,IOB33S,IO_L2N_T0_17,UNUSED,,17,,,,,,,,,
G21,,,VCCO_17,,,17,,,,,any******,,,,
G22,,IOB33M,IO_L9P_T1_DQS_17,UNUSED,,17,,,,,,,,,
G23,,IOB33M,IO_L6P_T0_16,UNUSED,,16,,,,,,,,,
G24,,IOB33S,IO_L6N_T0_VREF_16,UNUSED,,16,,,,,,,,,
G25,,IOB33,IO_25_16,UNUSED,,16,,,,,,,,,
G26,,,GND,,,,,,,,,,,,
G27,,IOB33M,IO_L21P_T3_DQS_16,UNUSED,,16,,,,,,,,,
G28,,IOB33M,IO_L20P_T3_16,UNUSED,,16,,,,,,,,,
G29,,IOB33M,IO_L22P_T3_16,UNUSED,,16,,,,,,,,,
G30,,IOB33S,IO_L24N_T3_16,UNUSED,,16,,,,,,,,,
H1,,OPAD,MGTXTXN2_117,UNUSED,,,,,,,,,,,
H2,,OPAD,MGTXTXP2_117,UNUSED,,,,,,,,,,,
H3,,,MGTAVTT,,,,,,,,,,,,
H4,,,GND,,,,,,,,,,,,
H5,,IPAD,MGTXRXN1_117,UNUSED,,,,,,,,,,,
H6,,IPAD,MGTXRXP1_117,UNUSED,,,,,,,,,,,
H7,,,MGTAVCC,,,,,,,,,,,,
H8,,,GND,,,,,,,,,,,,
H9,,,GND,,,,,,,,,,,,
H10,,,TDI_0,,,,,,,,,,,,
H11,,IOB33M,IO_L10P_T1_18,UNUSED,,18,,,,,,,,,
H12,,IOB33S,IO_L10N_T1_18,UNUSED,,18,,,,,,,,,
H13,,,GND,,,,,,,,,,,,
H14,,IOB33M,IO_L11P_T1_SRCC_18,UNUSED,,18,,,,,,,,,
H15,,IOB33M,IO_L7P_T1_18,UNUSED,,18,,,,,,,,,
H16,,IOB33S,IO_L9N_T1_DQS_18,UNUSED,,18,,,,,,,,,
H17,,IOB33S,IO_L3N_T0_DQS_17,UNUSED,,17,,,,,,,,,
H18,,,VCCO_17,,,17,,,,,any******,,,,
H19,,IOB33S,IO_L4N_T0_17,UNUSED,,17,,,,,,,,,
H20,,IOB33M,IO_L2P_T0_17,UNUSED,,17,,,,,,,,,
H21,,IOB33M,IO_L7P_T1_17,UNUSED,,17,,,,,,,,,
H22,,IOB33S,IO_L7N_T1_17,UNUSED,,17,,,,,,,,,
H23,,,GND,,,,,,,,,,,,
H24,,IOB33M,IO_L19P_T3_16,UNUSED,,16,,,,,,,,,
H25,,IOB33S,IO_L19N_T3_VREF_16,UNUSED,,16,,,,,,,,,
H26,,IOB33M,IO_L23P_T3_16,UNUSED,,16,,,,,,,,,
H27,,IOB33S,IO_L23N_T3_16,UNUSED,,16,,,,,,,,,
H28,,,VCCO_16,,,16,,,,,any******,,,,
H29,,IOB33S,IO_L7N_T1_AD10N_15,UNUSED,,15,,,,,,,,,
H30,,IOB33M,IO_L24P_T3_16,UNUSED,,16,,,,,,,,,
J1,,,GND,,,,,,,,,,,,
J2,,,GND,,,,,,,,,,,,
J3,,OPAD,MGTXTXN1_117,UNUSED,,,,,,,,,,,
J4,,OPAD,MGTXTXP1_117,UNUSED,,,,,,,,,,,
J5,,,MGTAVTT,,,,,,,,,,,,
J6,,,GND,,,,,,,,,,,,
J7,,IPAD,MGTREFCLK1N_117,UNUSED,,,,,,,,,,,
J8,,IPAD,MGTREFCLK1P_117,UNUSED,,,,,,,,,,,
J9,,,GND,,,,,,,,,,,,
J10,,,GND,,,,,,,,,,,,
J11,,IOB33M,IO_L8P_T1_18,UNUSED,,18,,,,,,,,,
J12,,IOB33S,IO_L8N_T1_18,UNUSED,,18,,,,,,,,,
J13,,IOB33S,IO_L4N_T0_18,UNUSED,,18,,,,,,,,,
J14,,IOB33S,IO_L5N_T0_18,UNUSED,,18,,,,,,,,,
J15,,,VCCO_18,,,18,,,,,any******,,,,
J16,,IOB33M,IO_L9P_T1_DQS_18,UNUSED,,18,,,,,,,,,
J17,,IOB33M,IO_L3P_T0_DQS_17,UNUSED,,17,,,,,,,,,
J18,,IOB33S,IO_L1N_T0_17,UNUSED,,17,,,,,,,,,
J19,,IOB33M,IO_L4P_T0_17,UNUSED,,17,,,,,,,,,
J20,,,GND,,,,,,,,,,,,
J21,,IOB33M,IO_L5P_T0_AD2P_15,UNUSED,,15,,,,,,,,,
J22,,IOB33S,IO_L5N_T0_AD2N_15,UNUSED,,15,,,,,,,,,
J23,,IOB33M,IO_L1P_T0_AD0P_15,UNUSED,,15,,,,,,,,,
J24,,IOB33S,IO_L1N_T0_AD0N_15,UNUSED,,15,,,,,,,,,
J25,,,VCCO_15,,,15,,,,,any******,,,,
J26,,IOB33S,IO_L10N_T1_AD4N_15,UNUSED,,15,,,,,,,,,
J27,,IOB33M,IO_L8P_T1_AD3P_15,UNUSED,,15,,,,,,,,,
J28,,IOB33S,IO_L8N_T1_AD3N_15,UNUSED,,15,,,,,,,,,
J29,,IOB33M,IO_L7P_T1_AD10P_15,UNUSED,,15,,,,,,,,,
J30,,,GND,,,,,,,,,,,,
K1,,OPAD,MGTXTXN0_117,UNUSED,,,,,,,,,,,
K2,,OPAD,MGTXTXP0_117,UNUSED,,,,,,,,,,,
K3,,,MGTAVTT,,,,,,,,,,,,
K4,,,GND,,,,,,,,,,,,
K5,,IPAD,MGTXRXN0_117,UNUSED,,,,,,,,,,,
K6,,IPAD,MGTXRXP0_117,UNUSED,,,,,,,,,,,
K7,,,MGTAVCC,,,,,,,,,,,,
K8,,,GND,,,,,,,,,,,,
K9,,,GND,,,,,,,,,,,,
K10,,,PROGRAM_B_0,,,,,,,,,,,,
K11,,IOB33S,IO_L6N_T0_VREF_18,UNUSED,,18,,,,,,,,,
K12,,,VCCO_18,,,18,,,,,any******,,,,
K13,,IOB33M,IO_L4P_T0_18,UNUSED,,18,,,,,,,,,
K14,,IOB33M,IO_L5P_T0_18,UNUSED,,18,,,,,,,,,
K15,,IOB33S,IO_L2N_T0_18,UNUSED,,18,,,,,,,,,
K16,,IOB33S,IO_L1N_T0_18,UNUSED,,18,,,,,,,,,
K17,,,GND,,,,,,,,,,,,
K18,,IOB33M,IO_L1P_T0_17,UNUSED,,17,,,,,,,,,
K19,,IOB33M,IO_L6P_T0_17,UNUSED,,17,,,,,,,,,
K20,,IOB33S,IO_L6N_T0_VREF_17,UNUSED,,17,,,,,,,,,
K21,,IOB33S,IO_L4N_T0_AD9N_15,UNUSED,,15,,,,,,,,,
K22,,,VCCO_15,,,15,,,,,any******,,,,
K23,,IOB33M,IO_L3P_T0_DQS_AD1P_15,UNUSED,,15,,,,,,,,,
K24,,IOB33S,IO_L3N_T0_DQS_AD1N_15,UNUSED,,15,,,,,,,,,
K25,,IOB33S,IO_L12N_T1_MRCC_AD5N_15,UNUSED,,15,,,,,,,,,
K26,,IOB33M,IO_L10P_T1_AD4P_15,UNUSED,,15,,,,,,,,,
K27,,,GND,,,,,,,,,,,,
K28,,IOB33M,IO_L13P_T2_MRCC_15,UNUSED,,15,,,,,,,,,
K29,,IOB33S,IO_L13N_T2_MRCC_15,UNUSED,,15,,,,,,,,,
K30,,IOB33S,IO_L9N_T1_DQS_AD11N_15,UNUSED,,15,,,,,,,,,
L1,,,GND,,,,,,,,,,,,
L2,,,GND,,,,,,,,,,,,
L3,,OPAD,MGTXTXN3_116,UNUSED,,,,,,,,,,,
L4,,OPAD,MGTXTXP3_116,UNUSED,,,,,,,,,,,
L5,,,MGTAVTT,,,,,,,,,,,,
L6,,,GND,,,,,,,,,,,,
L7,,IPAD,MGTREFCLK0N_116,UNUSED,,,,,,,,,,,
L8,,IPAD,MGTREFCLK0P_116,UNUSED,,,,,,,,,,,
L9,,,GND,,,,,,,,,,,,
L10,,,CFGBVS_0,,,,,,,,,,,,
L11,,IOB33M,IO_L6P_T0_18,UNUSED,,18,,,,,,,,,
L12,,IOB33M,IO_L3P_T0_DQS_18,UNUSED,,18,,,,,,,,,
L13,,IOB33S,IO_L3N_T0_DQS_18,UNUSED,,18,,,,,,,,,
L14,,,GND,,,,,,,,,,,,
L15,,IOB33M,IO_L2P_T0_18,UNUSED,,18,,,,,,,,,
L16,,IOB33M,IO_L1P_T0_18,UNUSED,,18,,,,,,,,,
L17,,IOB33M,IO_L5P_T0_17,UNUSED,,17,,,,,,,,,
L18,,IOB33S,IO_L5N_T0_17,UNUSED,,17,,,,,,,,,
L19,,,VCCO_17,,,17,,,,,any******,,,,
L20,,IOB33S,IO_L6N_T0_VREF_15,UNUSED,,15,,,,,,,,,
L21,,IOB33M,IO_L4P_T0_AD9P_15,UNUSED,,15,,,,,,,,,
L22,,IOB33M,IO_L2P_T0_AD8P_15,UNUSED,,15,,,,,,,,,
L23,,IOB33S,IO_L2N_T0_AD8N_15,UNUSED,,15,,,,,,,,,
L24,,,GND,,,,,,,,,,,,
L25,,IOB33M,IO_L12P_T1_MRCC_AD5P_15,UNUSED,,15,,,,,,,,,
L26,,IOB33M,IO_L11P_T1_SRCC_AD12P_15,UNUSED,,15,,,,,,,,,
L27,,IOB33S,IO_L11N_T1_SRCC_AD12N_15,UNUSED,,15,,,,,,,,,
L28,,IOB33S,IO_L14N_T2_SRCC_15,UNUSED,,15,,,,,,,,,
L29,,,VCCO_15,,,15,,,,,any******,,,,
L30,,IOB33M,IO_L9P_T1_DQS_AD11P_15,UNUSED,,15,,,,,,,,,
M1,,OPAD,MGTXTXN2_116,UNUSED,,,,,,,,,,,
M2,,OPAD,MGTXTXP2_116,UNUSED,,,,,,,,,,,
M3,,,MGTAVTT,,,,,,,,,,,,
M4,,,GND,,,,,,,,,,,,
M5,,IPAD,MGTXRXN3_116,UNUSED,,,,,,,,,,,
M6,,IPAD,MGTXRXP3_116,UNUSED,,,,,,,,,,,
M7,,,MGTAVCC,,,,,,,,,,,,
M8,,,GND,,,,,,,,,,,,
M9,,,GND,,,,,,,,,,,,
M10,,,DONE_0,,,,,,,,,,,,
M11,,,VCCINT,,,,,,,,1.0,,,,
M12,,,GND,,,,,,,,,,,,
M13,,,VCCINT,,,,,,,,1.0,,,,
M14,,,GND,,,,,,,,,,,,
M15,,,VCCINT,,,,,,,,1.0,,,,
M16,,,GND,,,,,,,,,,,,
M17,,,VCCINT,,,,,,,,1.0,,,,
M18,,,GND,,,,,,,,,,,,
M19,,IOB33,IO_0_15,UNUSED,,15,,,,,,,,,
M20,,IOB33M,IO_L6P_T0_15,UNUSED,,15,,,,,,,,,
M21,,,GND,,,,,,,,,,,,
M22,,IOB33M,IO_L24P_T3_RS1_15,UNUSED,,15,,,,,,,,,
M23,,IOB33S,IO_L24N_T3_RS0_15,UNUSED,,15,,,,,,,,,
M24,,IOB33M,IO_L23P_T3_FOE_B_15,UNUSED,,15,,,,,,,,,
M25,,IOB33S,IO_L23N_T3_FWE_B_15,UNUSED,,15,,,,,,,,,
M26,,,VCCO_15,,,15,,,,,any******,,,,
M27,,IOB33S,IO_L16N_T2_A27_15,UNUSED,,15,,,,,,,,,
M28,,IOB33M,IO_L14P_T2_SRCC_15,UNUSED,,15,,,,,,,,,
M29,,IOB33M,IO_L15P_T2_DQS_15,UNUSED,,15,,,,,,,,,
M30,,IOB33S,IO_L15N_T2_DQS_ADV_B_15,UNUSED,,15,,,,,,,,,
N1,,,GND,,,,,,,,,,,,
N2,,,GND,,,,,,,,,,,,
N3,,OPAD,MGTXTXN1_116,UNUSED,,,,,,,,,,,
N4,,OPAD,MGTXTXP1_116,UNUSED,,,,,,,,,,,
N5,,,MGTAVTT,,,,,,,,,,,,
N6,,,GND,,,,,,,,,,,,
N7,,IPAD,MGTREFCLK1N_116,UNUSED,,,,,,,,,,,
N8,,IPAD,MGTREFCLK1P_116,UNUSED,,,,,,,,,,,
N9,,,GND,,,,,,,,,,,,
N10,,,VCCINT,,,,,,,,1.0,,,,
N11,,,GND,,,,,,,,,,,,
N12,,,VCCINT,,,,,,,,1.0,,,,
N13,,,GND,,,,,,,,,,,,
N14,,,VCCINT,,,,,,,,1.0,,,,
N15,,,GND,,,,,,,,,,,,
N16,,,VCCBRAM,,,,,,,,,,,,
N17,,,GND,,,,,,,,,,,,
N18,,,VCCINT,,,,,,,,1.0,,,,
N19,,IOB33M,IO_L19P_T3_A22_15,UNUSED,,15,,,,,,,,,
N20,,IOB33S,IO_L19N_T3_A21_VREF_15,UNUSED,,15,,,,,,,,,
N21,,IOB33M,IO_L20P_T3_A20_15,UNUSED,,15,,,,,,,,,
N22,,IOB33S,IO_L20N_T3_A19_15,UNUSED,,15,,,,,,,,,
N23,,,VCCO_15,,,15,,,,,any******,,,,
N24,,IOB33S,IO_L21N_T3_DQS_A18_15,UNUSED,,15,,,,,,,,,
N25,,IOB33M,IO_L18P_T2_A24_15,UNUSED,,15,,,,,,,,,
N26,,IOB33S,IO_L18N_T2_A23_15,UNUSED,,15,,,,,,,,,
N27,,IOB33M,IO_L16P_T2_A28_15,UNUSED,,15,,,,,,,,,
N28,,,GND,,,,,,,,,,,,
N29,,IOB33M,IO_L17P_T2_A26_15,UNUSED,,15,,,,,,,,,
N30,,IOB33S,IO_L17N_T2_A25_15,UNUSED,,15,,,,,,,,,
P1,,OPAD,MGTXTXN0_116,UNUSED,,,,,,,,,,,
P2,,OPAD,MGTXTXP0_116,UNUSED,,,,,,,,,,,
P3,,,MGTAVTT,,,,,,,,,,,,
P4,,,GND,,,,,,,,,,,,
P5,,IPAD,MGTXRXN2_116,UNUSED,,,,,,,,,,,
P6,,IPAD,MGTXRXP2_116,UNUSED,,,,,,,,,,,
P7,,,MGTAVCC,,,,,,,,,,,,
P8,,,GND,,,,,,,,,,,,
P9,,,GND,,,,,,,,,,,,
P10,,,GND,,,,,,,,,,,,
P11,,,VCCINT,,,,,,,,1.0,,,,
P12,,,GND,,,,,,,,,,,,
P13,,,VCCAUX,,,,,,,,1.8,,,,
P14,,,GNDADC_0,,,,,,,,,,,,
P15,,,VCCADC_0,,,,,,,,,,,,
P16,,,GND,,,,,,,,,,,,
P17,,,VCCINT,,,,,,,,1.0,,,,
P18,,,GND,,,,,,,,,,,,
P19,,IOB33,IO_25_15,UNUSED,,15,,,,,,,,,
P20,,,VCCO_15,,,15,,,,,any******,,,,
P21,,IOB33M,IO_L22P_T3_A17_15,UNUSED,,15,,,,,,,,,
P22,,IOB33S,IO_L22N_T3_A16_15,UNUSED,,15,,,,,,,,,
P23,,IOB33M,IO_L21P_T3_DQS_15,UNUSED,,15,,,,,,,,,
P24,,IOB33M,IO_L1P_T0_D00_MOSI_14,UNUSED,,14,,,,,,,,,
P25,,,GND,,,,,,,,,,,,
P26,,IOB33M,IO_L10P_T1_D14_14,UNUSED,,14,,,,,,,,,
P27,,IOB33M,IO_L8P_T1_D11_14,UNUSED,,14,,,,,,,,,
P28,,IOB33S,IO_L8N_T1_D12_14,UNUSED,,14,,,,,,,,,
P29,,IOB33M,IO_L7P_T1_D09_14,UNUSED,,14,,,,,,,,,
P30,,,VCCO_14,,,14,,,,,any******,,,,
R1,,,GND,,,,,,,,,,,,
R2,,,GND,,,,,,,,,,,,
R3,,IPAD,MGTXRXN1_116,UNUSED,,,,,,,,,,,
R4,,IPAD,MGTXRXP1_116,UNUSED,,,,,,,,,,,
R5,,,MGTAVTT,,,,,,,,,,,,
R6,,,GND,,,,,,,,,,,,
R7,,IPAD,MGTREFCLK0N_115,UNUSED,,,,,,,,,,,
R8,,IPAD,MGTREFCLK0P_115,UNUSED,,,,,,,,,,,
R9,,,GND,,,,,,,,,,,,
R10,,,VCCINT,,,,,,,,1.0,,,,
R11,,,GND,,,,,,,,,,,,
R12,,,VCCINT,,,,,,,,1.0,,,,
R13,,,GND,,,,,,,,,,,,
R14,,,VREFN_0,,,,,,,,,,,,
R15,,IPAD,VP_0,UNUSED,,0,,,,,,,,,
R16,,,VCCBRAM,,,,,,,,,,,,
R17,,,GND,,,,,,,,,,,,
R18,,,VCCINT,,,,,,,,1.0,,,,
R19,,IOB33,IO_0_14,UNUSED,,14,,,,,,,,,
R20,,IOB33M,IO_L2P_T0_D02_14,UNUSED,,14,,,,,,,,,
R21,,IOB33S,IO_L2N_T0_D03_14,UNUSED,,14,,,,,,,,,
R22,,,GND,,,,,,,,,,,,
R23,,IOB33M,IO_L3P_T0_DQS_PUDC_B_14,UNUSED,,14,,,,,,,,,
R24,,IOB33S,IO_L3N_T0_DQS_EMCCLK_14,UNUSED,,14,,,,,,,,,
R25,,IOB33S,IO_L1N_T0_D01_DIN_14,UNUSED,,14,,,,,,,,,
R26,,IOB33S,IO_L10N_T1_D15_14,UNUSED,,14,,,,,,,,,
R27,,,VCCO_14,,,14,,,,,any******,,,,
R28,,IOB33M,IO_L11P_T1_SRCC_14,UNUSED,,14,,,,,,,,,
R29,,IOB33S,IO_L7N_T1_D10_14,UNUSED,,14,,,,,,,,,
R30,,IOB33M,IO_L9P_T1_DQS_14,UNUSED,,14,,,,,,,,,
T1,,OPAD,MGTXTXN3_115,UNUSED,,,,,,,,,,,
T2,,OPAD,MGTXTXP3_115,UNUSED,,,,,,,,,,,
T3,,,MGTAVTT,,,,,,,,,,,,
T4,,,GND,,,,,,,,,,,,
T5,,IPAD,MGTXRXN0_116,UNUSED,,,,,,,,,,,
T6,,IPAD,MGTXRXP0_116,UNUSED,,,,,,,,,,,
T7,,,MGTVCCAUX,,,,,,,,,,,,
T8,,,GND,,,,,,,,,,,,
T9,,,VCCO_0,,,0,,,,,any******,,,,
T10,,,GND,,,,,,,,,,,,
T11,,,VCCINT,,,,,,,,1.0,,,,
T12,,,GND,,,,,,,,,,,,
T13,,,VCCAUX,,,,,,,,1.8,,,,
T14,,IPAD,VN_0,UNUSED,,0,,,,,,,,,
T15,,,VREFP_0,,,,,,,,,,,,
T16,,,GND,,,,,,,,,,,,
T17,,,VCCINT,,,,,,,,1.0,,,,
T18,,,GND,,,,,,,,,,,,
T19,,,GND,,,,,,,,,,,,
T20,,IOB33M,IO_L4P_T0_D04_14,UNUSED,,14,,,,,,,,,
T21,,IOB33S,IO_L4N_T0_D05_14,UNUSED,,14,,,,,,,,,
T22,,IOB33M,IO_L5P_T0_D06_14,UNUSED,,14,,,,,,,,,
T23,,IOB33S,IO_L5N_T0_D07_14,UNUSED,,14,,,,,,,,,
T24,,,VCCO_14,,,14,,,,,any******,,,,
T25,,IOB33M,IO_L14P_T2_SRCC_14,UNUSED,,14,,,,,,,,,
T26,,IOB33M,IO_L12P_T1_MRCC_14,UNUSED,,14,,,,,,,,,
T27,,IOB33S,IO_L12N_T1_MRCC_14,UNUSED,,14,,,,,,,,,
T28,,IOB33S,IO_L11N_T1_SRCC_14,UNUSED,,14,,,,,,,,,
T29,,,GND,,,,,,,,,,,,
T30,,IOB33S,IO_L9N_T1_DQS_D13_14,UNUSED,,14,,,,,,,,,
U1,,,GND,,,,,,,,,,,,
U2,,,GND,,,,,,,,,,,,
U3,,OPAD,MGTXTXN2_115,UNUSED,,,,,,,,,,,
U4,,OPAD,MGTXTXP2_115,UNUSED,,,,,,,,,,,
U5,,,MGTAVTT,,,,,,,,,,,,
U6,,,GND,,,,,,,,,,,,
U7,,IPAD,MGTREFCLK1N_115,UNUSED,,,,,,,,,,,
U8,,IPAD,MGTREFCLK1P_115,UNUSED,,,,,,,,,,,
U9,,,GND,,,,,,,,,,,,
U10,,,VCCINT,,,,,,,,1.0,,,,
U11,,,GND,,,,,,,,,,,,
U12,,,VCCINT,,,,,,,,1.0,,,,
U13,,,GND,,,,,,,,,,,,
U14,,,DXN_0,,,,,,,,,,,,
U15,,,DXP_0,,,,,,,,,,,,
U16,,,VCCBRAM,,,,,,,,,,,,
U17,,,GND,,,,,,,,,,,,
U18,,,VCCINT,,,,,,,,1.0,,,,
U19,,IOB33M,IO_L6P_T0_FCS_B_14,UNUSED,,14,,,,,,,,,
U20,,IOB33S,IO_L6N_T0_D08_VREF_14,UNUSED,,14,,,,,,,,,
U21,,,VCCO_14,,,14,,,,,any******,,,,
U22,,IOB33M,IO_L21P_T3_DQS_14,UNUSED,,14,,,,,,,,,
U23,,IOB33S,IO_L21N_T3_DQS_A06_D22_14,UNUSED,,14,,,,,,,,,
U24,,IOB33M,IO_L23P_T3_A03_D19_14,UNUSED,,14,,,,,,,,,
U25,,IOB33S,IO_L14N_T2_SRCC_14,UNUSED,,14,,,,,,,,,
U26,,,GND,,,,,,,,,,,,
U27,,IOB33M,IO_L13P_T2_MRCC_14,UNUSED,,14,,,,,,,,,
U28,,IOB33S,IO_L13N_T2_MRCC_14,UNUSED,,14,,,,,,,,,
U29,,IOB33M,IO_L15P_T2_DQS_RDWR_B_14,UNUSED,,14,,,,,,,,,
U30,,IOB33S,IO_L15N_T2_DQS_DOUT_CSO_B_14,UNUSED,,14,,,,,,,,,
V1,,OPAD,MGTXTXN1_115,UNUSED,,,,,,,,,,,
V2,,OPAD,MGTXTXP1_115,UNUSED,,,,,,,,,,,
V3,,,MGTAVTT,,,,,,,,,,,,
V4,,,GND,,,,,,,,,,,,
V5,,IPAD,MGTXRXN3_115,UNUSED,,,,,,,,,,,
V6,,IPAD,MGTXRXP3_115,UNUSED,,,,,,,,,,,
V7,,,MGTVCCAUX,,,,,,,,,,,,
V8,,,GND,,,,,,,,,,,,
V9,,,GND,,,,,,,,,,,,
V10,,,GND,,,,,,,,,,,,
V11,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
V12,,,GND,,,,,,,,,,,,
V13,,,VCCAUX,,,,,,,,1.8,,,,
V14,,,GND,,,,,,,,,,,,
V15,,,VCCAUX,,,,,,,,1.8,,,,
V16,,,GND,,,,,,,,,,,,
V17,,,VCCINT,,,,,,,,1.0,,,,
V18,,,GND,,,,,,,,,,,,
V19,,IOB33M,IO_L19P_T3_A10_D26_14,UNUSED,,14,,,,,,,,,
V20,,IOB33S,IO_L19N_T3_A09_D25_VREF_14,UNUSED,,14,,,,,,,,,
V21,,IOB33M,IO_L22P_T3_A05_D21_14,UNUSED,,14,,,,,,,,,
V22,,IOB33S,IO_L22N_T3_A04_D20_14,UNUSED,,14,,,,,,,,,
V23,,,GND,,,,,,,,,,,,
V24,,IOB33S,IO_L23N_T3_A02_D18_14,UNUSED,,14,,,,,,,,,
V25,,IOB33M,IO_L18P_T2_A12_D28_14,UNUSED,,14,,,,,,,,,
V26,,IOB33M,IO_L16P_T2_CSI_B_14,UNUSED,,14,,,,,,,,,
V27,,IOB33S,IO_L16N_T2_A15_D31_14,UNUSED,,14,,,,,,,,,
V28,,,VCCO_14,,,14,,,,,any******,,,,
V29,,IOB33M,IO_L17P_T2_A14_D30_14,UNUSED,,14,,,,,,,,,
V30,,IOB33S,IO_L17N_T2_A13_D29_14,UNUSED,,14,,,,,,,,,
W1,,,GND,,,,,,,,,,,,
W2,,,GND,,,,,,,,,,,,
W3,,IPAD,MGTXRXN2_115,UNUSED,,,,,,,,,,,
W4,,IPAD,MGTXRXP2_115,UNUSED,,,,,,,,,,,
W5,,,MGTAVTT,,,,,,,,,,,,
W6,,,GND,,,,,,,,,,,,
W7,,,MGTAVTTRCAL_115,,,,,,,,,,,,
W8,,,MGTRREF_115,,,,,,,,,,,,
W9,,,GND,,,,,,,,,,,,
W10,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
W11,,,GND,,,,,,,,,,,,
W12,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
W13,,,GND,,,,,,,,,,,,
W14,,,VCCAUX,,,,,,,,1.8,,,,
W15,,,GND,,,,,,,,,,,,
W16,,,VCCBRAM,,,,,,,,,,,,
W17,,,GND,,,,,,,,,,,,
W18,,,VCCINT,,,,,,,,1.0,,,,
W19,,IOB33,IO_25_14,UNUSED,,14,,,,,,,,,
W20,,,GND,,,,,,,,,,,,
W21,,IOB33M,IO_L24P_T3_A01_D17_14,UNUSED,,14,,,,,,,,,
W22,,IOB33S,IO_L24N_T3_A00_D16_14,UNUSED,,14,,,,,,,,,
W23,,IOB33M,IO_L20P_T3_A08_D24_14,UNUSED,,14,,,,,,,,,
W24,,IOB33S,IO_L20N_T3_A07_D23_14,UNUSED,,14,,,,,,,,,
W25,,,VCCO_14,,,14,,,,,any******,,,,
W26,,IOB33S,IO_L18N_T2_A11_D27_14,UNUSED,,14,,,,,,,,,
W27,,IOB33M,IO_L2P_T0_13,UNUSED,,13,,,,,,,,,
W28,,IOB33S,IO_L2N_T0_13,UNUSED,,13,,,,,,,,,
W29,,IOB33M,IO_L4P_T0_13,UNUSED,,13,,,,,,,,,
W30,,,GND,,,,,,,,,,,,
Y1,,OPAD,MGTXTXN0_115,UNUSED,,,,,,,,,,,
Y2,,OPAD,MGTXTXP0_115,UNUSED,,,,,,,,,,,
Y3,,,GND,,,,,,,,,,,,
Y4,,,GND,,,,,,,,,,,,
Y5,,IPAD,MGTXRXN1_115,UNUSED,,,,,,,,,,,
Y6,,IPAD,MGTXRXP1_115,UNUSED,,,,,,,,,,,
Y7,,,GND,,,,,,,,,,,,
Y8,,,GND,,,,,,,,,,,,
Y9,,,GND,,,,,,,,,,,,
Y10,ddr3_addr<9>,IOB18,IO_L4N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
Y11,ddr3_addr<10>,IOB18,IO_L4P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
Y12,,,VCCO_33,,,33,,,,,1.50,,,,
Y13,,IOB18,IO_0_VRN_33,UNUSED,,33,,,,,,,,,
Y14,,IOB18,IO_0_VRN_32,UNUSED,,32,,,,,,,,,
Y15,,IOB18S,IO_L24N_T3_32,UNUSED,,32,,,,,,,,,
Y16,,IOB18M,IO_L24P_T3_32,UNUSED,,32,,,,,,,,,
Y17,,,GND,,,,,,,,,,,,
Y18,,IOB18S,IO_L15N_T2_DQS_32,UNUSED,,32,,,,,,,,,
Y19,,IOB18M,IO_L15P_T2_DQS_32,UNUSED,,32,,,,,,,,,
Y20,,IOB33,IO_0_12,UNUSED,,12,,,,,,,,,
Y21,,IOB33M,IO_L2P_T0_12,UNUSED,,12,,,,,,,,,
Y22,,,VCCO_12,,,12,,,,,any******,,,,
Y23,,IOB33M,IO_L1P_T0_12,UNUSED,,12,,,,,,,,,
Y24,,IOB33S,IO_L1N_T0_12,UNUSED,,12,,,,,,,,,
Y25,,IOB33,IO_0_13,UNUSED,,13,,,,,,,,,
Y26,,IOB33M,IO_L1P_T0_13,UNUSED,,13,,,,,,,,,
Y27,,,GND,,,,,,,,,,,,
Y28,,IOB33M,IO_L3P_T0_DQS_13,UNUSED,,13,,,,,,,,,
Y29,,IOB33S,IO_L4N_T0_13,UNUSED,,13,,,,,,,,,
Y30,tg_compare_error,IOB33,IO_L8P_T1_13,OUTPUT,LVCMOS33,13,12,SLOW,,,,LOCATED,NO,NONE,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#All RSVD_0 pins must be tied to GROUND.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
1 #Release 14.4 - par P.49d (lin64)
2 #Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
3 #Tue Jan 22 18:32:42 2013
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
8 # to support parsing.
9 #
10 #INPUT FILE: example_top_map.ncd
11 #OUTPUT FILE: example_top_pad.csv
12 #PART TYPE: xc7k410t
13 #SPEED GRADE: -2
14 #PACKAGE: ffg900
15 #
16 # Pinout by Pin Number:
17 #
18 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
19 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
20 A1,,,GND,,,,,,,,,,,,
21 A2,,,GND,,,,,,,,,,,,
22 A3,,OPAD,MGTXTXN3_118,UNUSED,,,,,,,,,,,
23 A4,,OPAD,MGTXTXP3_118,UNUSED,,,,,,,,,,,
24 A5,,,GND,,,,,,,,,,,,
25 A6,,,GND,,,,,,,,,,,,
26 A7,,IPAD,MGTXRXN3_118,UNUSED,,,,,,,,,,,
27 A8,,IPAD,MGTXRXP3_118,UNUSED,,,,,,,,,,,
28 A9,,,GND,,,,,,,,,,,,
29 A10,,,INIT_B_0,,,,,,,,,,,,
30 A11,,IOB33M,IO_L17P_T2_18,UNUSED,,18,,,,,,,,,
31 A12,,IOB33S,IO_L17N_T2_18,UNUSED,,18,,,,,,,,,
32 A13,,IOB33S,IO_L22N_T3_18,UNUSED,,18,,,,,,,,,
33 A14,,,GND,,,,,,,,,,,,
34 A15,,IOB33S,IO_L24N_T3_18,UNUSED,,18,,,,,,,,,
35 A16,,IOB33M,IO_L20P_T3_17,UNUSED,,17,,,,,,,,,
36 A17,,IOB33S,IO_L20N_T3_17,UNUSED,,17,,,,,,,,,
37 A18,,IOB33S,IO_L22N_T3_17,UNUSED,,17,,,,,,,,,
38 A19,,,VCCO_17,,,17,,,,,any******,,,,
39 A20,,IOB33M,IO_L21P_T3_DQS_17,UNUSED,,17,,,,,,,,,
40 A21,,IOB33S,IO_L21N_T3_DQS_17,UNUSED,,17,,,,,,,,,
41 A22,,IOB33S,IO_L23N_T3_17,UNUSED,,17,,,,,,,,,
42 A23,,IOB33S,IO_L1N_T0_16,UNUSED,,16,,,,,,,,,
43 A24,,,GND,,,,,,,,,,,,
44 A25,,IOB33M,IO_L10P_T1_16,UNUSED,,16,,,,,,,,,
45 A26,,IOB33S,IO_L10N_T1_16,UNUSED,,16,,,,,,,,,
46 A27,,IOB33S,IO_L7N_T1_16,UNUSED,,16,,,,,,,,,
47 A28,,IOB33S,IO_L9N_T1_DQS_16,UNUSED,,16,,,,,,,,,
48 A29,,,VCCO_16,,,16,,,,,any******,,,,
49 A30,,IOB33S,IO_L17N_T2_16,UNUSED,,16,,,,,,,,,
50 AA1,,,GND,,,,,,,,,,,,
51 AA2,,,GND,,,,,,,,,,,,
52 AA3,,IPAD,MGTXRXN0_115,UNUSED,,,,,,,,,,,
53 AA4,,IPAD,MGTXRXP0_115,UNUSED,,,,,,,,,,,
54 AA5,,,GND,,,,,,,,,,,,
55 AA6,,,GND,,,,,,,,,,,,
56 AA7,,,GND,,,,,,,,,,,,
57 AA8,ddr3_addr<12>,IOB18,IO_L2P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
58 AA9,,,VCCO_33,,,33,,,,,1.50,,,,
59 AA10,ddr3_addr<7>,IOB18,IO_L5N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
60 AA11,ddr3_addr<8>,IOB18,IO_L5P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
61 AA12,ddr3_addr<14>,IOB18,IO_L1P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
62 AA13,ddr3_addr<6>,IOB18,IO_L6P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
63 AA14,,,GND,,,,,,,,,,,,
64 AA15,,IOB18M,IO_L20P_T3_32,UNUSED,,32,,,,,,,,,
65 AA16,,IOB18S,IO_L23N_T3_32,UNUSED,,32,,,,,,,,,
66 AA17,,IOB18M,IO_L23P_T3_32,UNUSED,,32,,,,,,,,,
67 AA18,,IOB18M,IO_L16P_T2_32,UNUSED,,32,,,,,,,,,
68 AA19,,,VCCO_32,,,32,,,,,any******,,,,
69 AA20,,IOB33M,IO_L6P_T0_12,UNUSED,,12,,,,,,,,,
70 AA21,,IOB33S,IO_L2N_T0_12,UNUSED,,12,,,,,,,,,
71 AA22,,IOB33M,IO_L4P_T0_12,UNUSED,,12,,,,,,,,,
72 AA23,,IOB33S,IO_L4N_T0_12,UNUSED,,12,,,,,,,,,
73 AA24,,,GND,,,,,,,,,,,,
74 AA25,,IOB33M,IO_L6P_T0_13,UNUSED,,13,,,,,,,,,
75 AA26,,IOB33S,IO_L1N_T0_13,UNUSED,,13,,,,,,,,,
76 AA27,,IOB33M,IO_L5P_T0_13,UNUSED,,13,,,,,,,,,
77 AA28,,IOB33S,IO_L3N_T0_DQS_13,UNUSED,,13,,,,,,,,,
78 AA29,,,VCCO_13,,,13,,,,,3.30,,,,
79 AA30,init_calib_complete,IOB33,IO_L8N_T1_13,OUTPUT,LVCMOS33,13,12,SLOW,,,,LOCATED,NO,NONE,
80 AB1,,,M2_0,,,,,,,,,,,,
81 AB2,,,M1_0,,,,,,,,,,,,
82 AB3,,,GND,,,,,,,,,,,,
83 AB4,,,GND,,,,,,,,,,,,
84 AB5,,,M0_0,,,,,,,,,,,,
85 AB6,,,VCCO_0,,,0,,,,,any******,,,,
86 AB7,,IOB18,IO_25_VRP_34,Termination Required,,34,,,TERMINATION,,,,,,
87 AB8,ddr3_addr<11>,IOB18,IO_L2N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
88 AB9,ddr3_ck_p<0>,IOB18M,IO_L3P_T0_DQS_33,OUTPUT,DIFF_SSTL15,33,,FAST,,,,LOCATED,YES,NONE,
89 AB10,ddr3_addr<4>,IOB18,IO_L7P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
90 AB11,,,GND,,,,,,,,,,,,
91 AB12,ddr3_addr<13>,IOB18,IO_L1N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
92 AB13,ddr3_addr<5>,IOB18,IO_L6N_T0_VREF_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
93 AB14,,IOB18,IO_25_VRP_32,UNUSED,,32,,,,,,,,,
94 AB15,,IOB18S,IO_L20N_T3_32,UNUSED,,32,,,,,,,,,
95 AB16,,,VCCO_32,,,32,,,,,any******,,,,
96 AB17,,IOB18M,IO_L18P_T2_32,UNUSED,,32,,,,,,,,,
97 AB18,,IOB18S,IO_L16N_T2_32,UNUSED,,32,,,,,,,,,
98 AB19,,IOB18M,IO_L17P_T2_32,UNUSED,,32,,,,,,,,,
99 AB20,,IOB33S,IO_L6N_T0_VREF_12,UNUSED,,12,,,,,,,,,
100 AB21,,,GND,,,,,,,,,,,,
101 AB22,,IOB33M,IO_L3P_T0_DQS_12,UNUSED,,12,,,,,,,,,
102 AB23,,IOB33S,IO_L3N_T0_DQS_12,UNUSED,,12,,,,,,,,,
103 AB24,,IOB33M,IO_L7P_T1_12,UNUSED,,12,,,,,,,,,
104 AB25,,IOB33S,IO_L6N_T0_VREF_13,UNUSED,,13,,,,,,,,,
105 AB26,,,VCCO_13,,,13,,,,,3.30,,,,
106 AB27,,IOB33M,IO_L12P_T1_MRCC_13,UNUSED,,13,,,,,,,,,
107 AB28,,IOB33S,IO_L5N_T0_13,UNUSED,,13,,,,,,,,,
108 AB29,,IOB33M,IO_L10P_T1_13,UNUSED,,13,,,,,,,,,
109 AB30,,IOB33S,IO_L10N_T1_13,UNUSED,,13,,,,,,,,,
110 AC1,ddr3_dq<2>,IOB18,IO_L2N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
111 AC2,ddr3_dq<1>,IOB18,IO_L2P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
112 AC3,,,VCCO_34,,,34,,,,,1.50,,,,
113 AC4,ddr3_dq<4>,IOB18,IO_L4N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
114 AC5,ddr3_dq<3>,IOB18,IO_L4P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
115 AC6,,IOB18,IO_0_VRN_34,Termination Required,,34,,,TERMINATION,,,,,,
116 AC7,ddr3_dq<7>,IOB18,IO_L6P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
117 AC8,,,GND,,,,,,,,,,,,
118 AC9,ddr3_ck_n<0>,IOB18S,IO_L3N_T0_DQS_33,OUTPUT,DIFF_SSTL15,33,,FAST,,,,LOCATED,YES,NONE,
119 AC10,ddr3_addr<3>,IOB18,IO_L7N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
120 AC11,ddr3_ba<2>,IOB18,IO_L9N_T1_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
121 AC12,ddr3_addr<0>,IOB18,IO_L9P_T1_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
122 AC13,,,VCCO_33,,,33,,,,,1.50,,,,
123 AC14,,IOB18M,IO_L22P_T3_32,UNUSED,,32,,,,,,,,,
124 AC15,,IOB18S,IO_L21N_T3_DQS_32,UNUSED,,32,,,,,,,,,
125 AC16,,IOB18M,IO_L21P_T3_DQS_32,UNUSED,,32,,,,,,,,,
126 AC17,,IOB18S,IO_L18N_T2_32,UNUSED,,32,,,,,,,,,
127 AC18,,,GND,,,,,,,,,,,,
128 AC19,,IOB18S,IO_L17N_T2_32,UNUSED,,32,,,,,,,,,
129 AC20,,IOB33M,IO_L5P_T0_12,UNUSED,,12,,,,,,,,,
130 AC21,,IOB33S,IO_L5N_T0_12,UNUSED,,12,,,,,,,,,
131 AC22,,IOB33M,IO_L8P_T1_12,UNUSED,,12,,,,,,,,,
132 AC23,,,VCCO_12,,,12,,,,,any******,,,,
133 AC24,,IOB33M,IO_L9P_T1_DQS_12,UNUSED,,12,,,,,,,,,
134 AC25,,IOB33S,IO_L7N_T1_12,UNUSED,,12,,,,,,,,,
135 AC26,,IOB33M,IO_L19P_T3_13,UNUSED,,13,,,,,,,,,
136 AC27,,IOB33S,IO_L12N_T1_MRCC_13,UNUSED,,13,,,,,,,,,
137 AC28,,,GND,,,,,,,,,,,,
138 AC29,sys_rst,IOB33,IO_L7P_T1_13,INPUT,LVCMOS33,13,,,PULLUP,NONE,,LOCATED,NO,NONE,
139 AC30,,IOB33S,IO_L7N_T1_13,UNUSED,,13,,,,,,,,,
140 AD1,ddr3_dqs_n<0>,IOB18S,IO_L3N_T0_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
141 AD2,ddr3_dqs_p<0>,IOB18M,IO_L3P_T0_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
142 AD3,ddr3_dq<0>,IOB18,IO_L1N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
143 AD4,ddr3_dm<0>,IOB18,IO_L1P_T0_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
144 AD5,,,GND,,,,,,,,,,,,
145 AD6,ddr3_dq<5>,IOB18,IO_L5P_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
146 AD7,,IOB18S,IO_L6N_T0_VREF_34,VREF Required,,34,,,,,0.75,,,,
147 AD8,ddr3_addr<2>,IOB18,IO_L8P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
148 AD9,ddr3_ba<1>,IOB18,IO_L10P_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
149 AD10,,,VCCO_33,,,33,,,,,1.50,,,,
150 AD11,ddr3_cs_n<0>,IOB18,IO_L12N_T1_MRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
151 AD12,ddr3_we_n,IOB18,IO_L12P_T1_MRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
152 AD13,,IOB18,IO_25_VRP_33,UNUSED,,33,,,,,,,,,
153 AD14,,IOB18S,IO_L22N_T3_32,UNUSED,,32,,,,,,,,,
154 AD15,,,GND,,,,,,,,,,,,
155 AD16,,IOB18S,IO_L14N_T2_SRCC_32,UNUSED,,32,,,,,,,,,
156 AD17,,IOB18M,IO_L14P_T2_SRCC_32,UNUSED,,32,,,,,,,,,
157 AD18,,IOB18M,IO_L13P_T2_MRCC_32,UNUSED,,32,,,,,,,,,
158 AD19,,IOB18M,IO_L10P_T1_32,UNUSED,,32,,,,,,,,,
159 AD20,,,VCCO_12,,,12,,,,,any******,,,,
160 AD21,,IOB33M,IO_L10P_T1_12,UNUSED,,12,,,,,,,,,
161 AD22,,IOB33S,IO_L8N_T1_12,UNUSED,,12,,,,,,,,,
162 AD23,,IOB33M,IO_L12P_T1_MRCC_12,UNUSED,,12,,,,,,,,,
163 AD24,,IOB33S,IO_L9N_T1_DQS_12,UNUSED,,12,,,,,,,,,
164 AD25,,,GND,,,,,,,,,,,,
165 AD26,,IOB33S,IO_L19N_T3_VREF_13,UNUSED,,13,,,,,,,,,
166 AD27,,IOB33M,IO_L11P_T1_SRCC_13,UNUSED,,13,,,,,,,,,
167 AD28,,IOB33S,IO_L11N_T1_SRCC_13,UNUSED,,13,,,,,,,,,
168 AD29,,IOB33M,IO_L9P_T1_DQS_13,UNUSED,,13,,,,,,,,,
169 AD30,,,VCCO_13,,,13,,,,,3.30,,,,
170 AE1,ddr3_dq<9>,IOB18,IO_L8P_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
171 AE2,,,GND,,,,,,,,,,,,
172 AE3,ddr3_dq<12>,IOB18,IO_L10N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
173 AE4,ddr3_dq<11>,IOB18,IO_L10P_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
174 AE5,ddr3_dq<13>,IOB18,IO_L11P_T1_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
175 AE6,ddr3_dq<6>,IOB18,IO_L5N_T0_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
176 AE7,,,VCCO_34,,,34,,,,,1.50,,,,
177 AE8,ddr3_addr<1>,IOB18,IO_L8N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
178 AE9,ddr3_ba<0>,IOB18,IO_L10N_T1_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
179 AE10,sys_clk_i,IOB18,IO_L14P_T2_SRCC_33,INPUT,LVCMOS15,33,,,,NONE,,LOCATED,NO,NONE,
180 AE11,ddr3_ras_n,IOB18,IO_L11P_T1_SRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
181 AE12,,,GND,,,,,,,,,,,,
182 AE13,,IOB18M,IO_L19P_T3_33,UNUSED,,33,,,,,,,,,
183 AE14,,IOB18S,IO_L19N_T3_VREF_32,UNUSED,,32,,,,,,,,,
184 AE15,,IOB18M,IO_L19P_T3_32,UNUSED,,32,,,,,,,,,
185 AE16,,IOB18M,IO_L6P_T0_32,UNUSED,,32,,,,,,,,,
186 AE17,,,VCCO_32,,,32,,,,,any******,,,,
187 AE18,,IOB18S,IO_L13N_T2_MRCC_32,UNUSED,,32,,,,,,,,,
188 AE19,,IOB18S,IO_L10N_T1_32,UNUSED,,32,,,,,,,,,
189 AE20,,IOB33,IO_25_12,UNUSED,,12,,,,,,,,,
190 AE21,,IOB33S,IO_L10N_T1_12,UNUSED,,12,,,,,,,,,
191 AE22,,,GND,,,,,,,,,,,,
192 AE23,,IOB33M,IO_L11P_T1_SRCC_12,UNUSED,,12,,,,,,,,,
193 AE24,,IOB33S,IO_L12N_T1_MRCC_12,UNUSED,,12,,,,,,,,,
194 AE25,,IOB33M,IO_L16P_T2_12,UNUSED,,12,,,,,,,,,
195 AE26,,IOB33,IO_25_13,UNUSED,,13,,,,,,,,,
196 AE27,,,VCCO_13,,,13,,,,,3.30,,,,
197 AE28,,IOB33M,IO_L14P_T2_SRCC_13,UNUSED,,13,,,,,,,,,
198 AE29,,IOB33S,IO_L9N_T1_DQS_13,UNUSED,,13,,,,,,,,,
199 AE30,,IOB33M,IO_L16P_T2_13,UNUSED,,13,,,,,,,,,
200 AF1,ddr3_dq<10>,IOB18,IO_L8N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
201 AF2,ddr3_dq<8>,IOB18,IO_L7N_T1_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
202 AF3,ddr3_dm<1>,IOB18,IO_L7P_T1_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
203 AF4,,,VCCO_34,,,34,,,,,1.50,,,,
204 AF5,ddr3_dq<14>,IOB18,IO_L11N_T1_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
205 AF6,ddr3_dq<15>,IOB18,IO_L12P_T1_MRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
206 AF7,ddr3_dq<24>,IOB18,IO_L20P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
207 AF8,ddr3_dm<3>,IOB18,IO_L19P_T3_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
208 AF9,,,GND,,,,,,,,,,,,
209 AF10,,IOB18S,IO_L14N_T2_SRCC_33,UNUSED,,33,,,,,,,,,
210 AF11,ddr3_cas_n,IOB18,IO_L11N_T1_SRCC_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
211 AF12,,IOB18M,IO_L23P_T3_33,UNUSED,,33,,,,,,,,,
212 AF13,,IOB18S,IO_L19N_T3_VREF_33,UNUSED,,33,,,,,,,,,
213 AF14,,,VCCO_32,,,32,,,,,any******,,,,
214 AF15,,IOB18M,IO_L4P_T0_32,UNUSED,,32,,,,,,,,,
215 AF16,,IOB18S,IO_L6N_T0_VREF_32,UNUSED,,32,,,,,,,,,
216 AF17,,IOB18M,IO_L12P_T1_MRCC_32,UNUSED,,32,,,,,,,,,
217 AF18,,IOB18M,IO_L11P_T1_SRCC_32,UNUSED,,32,,,,,,,,,
218 AF19,,,GND,,,,,,,,,,,,
219 AF20,,IOB33M,IO_L19P_T3_12,UNUSED,,12,,,,,,,,,
220 AF21,,IOB33S,IO_L19N_T3_VREF_12,UNUSED,,12,,,,,,,,,
221 AF22,,IOB33M,IO_L13P_T2_MRCC_12,UNUSED,,12,,,,,,,,,
222 AF23,,IOB33S,IO_L11N_T1_SRCC_12,UNUSED,,12,,,,,,,,,
223 AF24,,,VCCO_12,,,12,,,,,any******,,,,
224 AF25,,IOB33S,IO_L16N_T2_12,UNUSED,,12,,,,,,,,,
225 AF26,,IOB33M,IO_L23P_T3_13,UNUSED,,13,,,,,,,,,
226 AF27,,IOB33S,IO_L23N_T3_13,UNUSED,,13,,,,,,,,,
227 AF28,,IOB33S,IO_L14N_T2_SRCC_13,UNUSED,,13,,,,,,,,,
228 AF29,,,GND,,,,,,,,,,,,
229 AF30,,IOB33S,IO_L16N_T2_13,UNUSED,,13,,,,,,,,,
230 AG1,,,VCCO_34,,,34,,,,,1.50,,,,
231 AG2,ddr3_dqs_p<2>,IOB18M,IO_L15P_T2_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
232 AG3,ddr3_dqs_n<1>,IOB18S,IO_L9N_T1_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
233 AG4,ddr3_dqs_p<1>,IOB18M,IO_L9P_T1_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
234 AG5,ddr3_reset_n,IOB18,IO_L12N_T1_MRCC_34,OUTPUT,LVCMOS15,34,12,FAST,,,,LOCATED,NO,NONE,
235 AG6,,,GND,,,,,,,,,,,,
236 AG7,ddr3_dq<25>,IOB18,IO_L20N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
237 AG8,,IOB18S,IO_L19N_T3_VREF_34,VREF Required,,34,,,,,0.75,,,,
238 AG9,,IOB18M,IO_L16P_T2_33,UNUSED,,33,,,,,,,,,
239 AG10,,IOB18M,IO_L13P_T2_MRCC_33,UNUSED,,33,,,,,,,,,
240 AG11,,,VCCO_33,,,33,,,,,1.50,,,,
241 AG12,,IOB18S,IO_L23N_T3_33,UNUSED,,33,,,,,,,,,
242 AG13,,IOB18M,IO_L24P_T3_33,UNUSED,,33,,,,,,,,,
243 AG14,,IOB18S,IO_L4N_T0_32,UNUSED,,32,,,,,,,,,
244 AG15,,IOB18M,IO_L2P_T0_32,UNUSED,,32,,,,,,,,,
245 AG16,,,GND,,,,,,,,,,,,
246 AG17,,IOB18S,IO_L12N_T1_MRCC_32,UNUSED,,32,,,,,,,,,
247 AG18,,IOB18S,IO_L11N_T1_SRCC_32,UNUSED,,32,,,,,,,,,
248 AG19,,IOB18M,IO_L8P_T1_32,UNUSED,,32,,,,,,,,,
249 AG20,,IOB33M,IO_L22P_T3_12,UNUSED,,12,,,,,,,,,
250 AG21,,,VCCO_12,,,12,,,,,any******,,,,
251 AG22,,IOB33M,IO_L20P_T3_12,UNUSED,,12,,,,,,,,,
252 AG23,,IOB33S,IO_L13N_T2_MRCC_12,UNUSED,,12,,,,,,,,,
253 AG24,,IOB33M,IO_L14P_T2_SRCC_12,UNUSED,,12,,,,,,,,,
254 AG25,,IOB33M,IO_L18P_T2_12,UNUSED,,12,,,,,,,,,
255 AG26,,,GND,,,,,,,,,,,,
256 AG27,,IOB33M,IO_L21P_T3_DQS_13,UNUSED,,13,,,,,,,,,
257 AG28,,IOB33S,IO_L21N_T3_DQS_13,UNUSED,,13,,,,,,,,,
258 AG29,,IOB33M,IO_L13P_T2_MRCC_13,UNUSED,,13,,,,,,,,,
259 AG30,,IOB33M,IO_L18P_T2_13,UNUSED,,13,,,,,,,,,
260 AH1,ddr3_dqs_n<2>,IOB18S,IO_L15N_T2_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
261 AH2,ddr3_dq<19>,IOB18,IO_L16P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
262 AH3,,,GND,,,,,,,,,,,,
263 AH4,ddr3_dm<2>,IOB18,IO_L13P_T2_MRCC_34,TRISTATE,SSTL15,34,,FAST,,,,LOCATED,NO,NONE,
264 AH5,ddr3_dq<18>,IOB18,IO_L14N_T2_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
265 AH6,ddr3_dq<17>,IOB18,IO_L14P_T2_SRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
266 AH7,ddr3_dqs_p<3>,IOB18M,IO_L21P_T3_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
267 AH8,,,VCCO_34,,,34,,,,,1.50,,,,
268 AH9,,IOB18S,IO_L16N_T2_33,UNUSED,,33,,,,,,,,,
269 AH10,,IOB18S,IO_L13N_T2_MRCC_33,UNUSED,,33,,,,,,,,,
270 AH11,,IOB18M,IO_L18P_T2_33,UNUSED,,33,,,,,,,,,
271 AH12,,IOB18S,IO_L24N_T3_33,UNUSED,,33,,,,,,,,,
272 AH13,,,GND,,,,,,,,,,,,
273 AH14,,IOB18M,IO_L21P_T3_DQS_33,UNUSED,,33,,,,,,,,,
274 AH15,,IOB18S,IO_L2N_T0_32,UNUSED,,32,,,,,,,,,
275 AH16,,IOB18M,IO_L3P_T0_DQS_32,UNUSED,,32,,,,,,,,,
276 AH17,,IOB18M,IO_L5P_T0_32,UNUSED,,32,,,,,,,,,
277 AH18,,,VCCO_32,,,32,,,,,any******,,,,
278 AH19,,IOB18S,IO_L8N_T1_32,UNUSED,,32,,,,,,,,,
279 AH20,,IOB33S,IO_L22N_T3_12,UNUSED,,12,,,,,,,,,
280 AH21,,IOB33M,IO_L23P_T3_12,UNUSED,,12,,,,,,,,,
281 AH22,,IOB33S,IO_L20N_T3_12,UNUSED,,12,,,,,,,,,
282 AH23,,,GND,,,,,,,,,,,,
283 AH24,,IOB33S,IO_L14N_T2_SRCC_12,UNUSED,,12,,,,,,,,,
284 AH25,,IOB33S,IO_L18N_T2_12,UNUSED,,12,,,,,,,,,
285 AH26,,IOB33M,IO_L22P_T3_13,UNUSED,,13,,,,,,,,,
286 AH27,,IOB33S,IO_L22N_T3_13,UNUSED,,13,,,,,,,,,
287 AH28,,,VCCO_13,,,13,,,,,3.30,,,,
288 AH29,,IOB33S,IO_L13N_T2_MRCC_13,UNUSED,,13,,,,,,,,,
289 AH30,,IOB33S,IO_L18N_T2_13,UNUSED,,13,,,,,,,,,
290 AJ1,ddr3_dq<21>,IOB18,IO_L17P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
291 AJ2,ddr3_dq<20>,IOB18,IO_L16N_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
292 AJ3,ddr3_dq<23>,IOB18,IO_L18P_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
293 AJ4,ddr3_dq<16>,IOB18,IO_L13N_T2_MRCC_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
294 AJ5,,,VCCO_34,,,34,,,,,1.50,,,,
295 AJ6,ddr3_dq<26>,IOB18,IO_L22P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
296 AJ7,ddr3_dqs_n<3>,IOB18S,IO_L21N_T3_DQS_34,BIDIR,DIFF_SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,YES,SPLIT,
297 AJ8,ddr3_dq<28>,IOB18,IO_L23P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
298 AJ9,ddr3_cke<0>,IOB18,IO_L15P_T2_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
299 AJ10,,,GND,,,,,,,,,,,,
300 AJ11,,IOB18S,IO_L18N_T2_33,UNUSED,,33,,,,,,,,,
301 AJ12,,IOB18S,IO_L22N_T3_33,UNUSED,,33,,,,,,,,,
302 AJ13,,IOB18M,IO_L22P_T3_33,UNUSED,,33,,,,,,,,,
303 AJ14,,IOB18S,IO_L21N_T3_DQS_33,UNUSED,,33,,,,,,,,,
304 AJ15,,,VCCO_32,,,32,,,,,any******,,,,
305 AJ16,,IOB18S,IO_L3N_T0_DQS_32,UNUSED,,32,,,,,,,,,
306 AJ17,,IOB18S,IO_L5N_T0_32,UNUSED,,32,,,,,,,,,
307 AJ18,,IOB18M,IO_L9P_T1_DQS_32,UNUSED,,32,,,,,,,,,
308 AJ19,,IOB18M,IO_L7P_T1_32,UNUSED,,32,,,,,,,,,
309 AJ20,,,GND,,,,,,,,,,,,
310 AJ21,,IOB33S,IO_L23N_T3_12,UNUSED,,12,,,,,,,,,
311 AJ22,,IOB33M,IO_L21P_T3_DQS_12,UNUSED,,12,,,,,,,,,
312 AJ23,,IOB33S,IO_L21N_T3_DQS_12,UNUSED,,12,,,,,,,,,
313 AJ24,,IOB33M,IO_L15P_T2_DQS_12,UNUSED,,12,,,,,,,,,
314 AJ25,,,VCCO_13,,,13,,,,,3.30,,,,
315 AJ26,,IOB33M,IO_L24P_T3_13,UNUSED,,13,,,,,,,,,
316 AJ27,,IOB33M,IO_L20P_T3_13,UNUSED,,13,,,,,,,,,
317 AJ28,,IOB33M,IO_L17P_T2_13,UNUSED,,13,,,,,,,,,
318 AJ29,,IOB33S,IO_L17N_T2_13,UNUSED,,13,,,,,,,,,
319 AJ30,,,GND,,,,,,,,,,,,
320 AK1,ddr3_dq<22>,IOB18,IO_L17N_T2_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
321 AK2,,,VCCO_34,,,34,,,,,1.50,,,,
322 AK3,,IOB18S,IO_L18N_T2_34,UNUSED,,34,,,,,,,,,
323 AK4,ddr3_dq<31>,IOB18,IO_L24N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
324 AK5,ddr3_dq<30>,IOB18,IO_L24P_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
325 AK6,ddr3_dq<27>,IOB18,IO_L22N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
326 AK7,,,GND,,,,,,,,,,,,
327 AK8,ddr3_dq<29>,IOB18,IO_L23N_T3_34,BIDIR,SSTL15_T_DCI,34,,FAST,,NONE,,LOCATED,NO,SPLIT,
328 AK9,ddr3_odt<0>,IOB18,IO_L15N_T2_DQS_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
329 AK10,,IOB18S,IO_L17N_T2_33,UNUSED,,33,,,,,,,,,
330 AK11,,IOB18M,IO_L17P_T2_33,UNUSED,,33,,,,,,,,,
331 AK12,,,VCCO_33,,,33,,,,,1.50,,,,
332 AK13,,IOB18S,IO_L20N_T3_33,UNUSED,,33,,,,,,,,,
333 AK14,,IOB18M,IO_L20P_T3_33,UNUSED,,33,,,,,,,,,
334 AK15,,IOB18S,IO_L1N_T0_32,UNUSED,,32,,,,,,,,,
335 AK16,,IOB18M,IO_L1P_T0_32,UNUSED,,32,,,,,,,,,
336 AK17,,,GND,,,,,,,,,,,,
337 AK18,,IOB18S,IO_L9N_T1_DQS_32,UNUSED,,32,,,,,,,,,
338 AK19,,IOB18S,IO_L7N_T1_32,UNUSED,,32,,,,,,,,,
339 AK20,,IOB33M,IO_L24P_T3_12,UNUSED,,12,,,,,,,,,
340 AK21,,IOB33S,IO_L24N_T3_12,UNUSED,,12,,,,,,,,,
341 AK22,,,VCCO_12,,,12,,,,,any******,,,,
342 AK23,,IOB33M,IO_L17P_T2_12,UNUSED,,12,,,,,,,,,
343 AK24,,IOB33S,IO_L17N_T2_12,UNUSED,,12,,,,,,,,,
344 AK25,,IOB33S,IO_L15N_T2_DQS_12,UNUSED,,12,,,,,,,,,
345 AK26,,IOB33S,IO_L24N_T3_13,UNUSED,,13,,,,,,,,,
346 AK27,,,GND,,,,,,,,,,,,
347 AK28,,IOB33S,IO_L20N_T3_13,UNUSED,,13,,,,,,,,,
348 AK29,,IOB33M,IO_L15P_T2_DQS_13,UNUSED,,13,,,,,,,,,
349 AK30,,IOB33S,IO_L15N_T2_DQS_13,UNUSED,,13,,,,,,,,,
350 B1,,OPAD,MGTXTXN2_118,UNUSED,,,,,,,,,,,
351 B2,,OPAD,MGTXTXP2_118,UNUSED,,,,,,,,,,,
352 B3,,,MGTAVTT,,,,,,,,,,,,
353 B4,,,GND,,,,,,,,,,,,
354 B5,,IPAD,MGTXRXN2_118,UNUSED,,,,,,,,,,,
355 B6,,IPAD,MGTXRXP2_118,UNUSED,,,,,,,,,,,
356 B7,,,MGTAVCC,,,,,,,,,,,,
357 B8,,,GND,,,,,,,,,,,,
358 B9,,,GND,,,,,,,,,,,,
359 B10,,,CCLK_0,,,,,,,,,,,,
360 B11,,,GND,,,,,,,,,,,,
361 B12,,IOB33S,IO_L15N_T2_DQS_18,UNUSED,,18,,,,,,,,,
362 B13,,IOB33M,IO_L22P_T3_18,UNUSED,,18,,,,,,,,,
363 B14,,IOB33M,IO_L24P_T3_18,UNUSED,,18,,,,,,,,,
364 B15,,IOB33S,IO_L23N_T3_18,UNUSED,,18,,,,,,,,,
365 B16,,,VCCO_17,,,17,,,,,any******,,,,
366 B17,,IOB33S,IO_L17N_T2_17,UNUSED,,17,,,,,,,,,
367 B18,,IOB33M,IO_L22P_T3_17,UNUSED,,17,,,,,,,,,
368 B19,,IOB33S,IO_L24N_T3_17,UNUSED,,17,,,,,,,,,
369 B20,,IOB33S,IO_L19N_T3_VREF_17,UNUSED,,17,,,,,,,,,
370 B21,,,GND,,,,,,,,,,,,
371 B22,,IOB33M,IO_L23P_T3_17,UNUSED,,17,,,,,,,,,
372 B23,,IOB33M,IO_L1P_T0_16,UNUSED,,16,,,,,,,,,
373 B24,,IOB33S,IO_L8N_T1_16,UNUSED,,16,,,,,,,,,
374 B25,,IOB33S,IO_L12N_T1_MRCC_16,UNUSED,,16,,,,,,,,,
375 B26,,,VCCO_16,,,16,,,,,any******,,,,
376 B27,,IOB33M,IO_L7P_T1_16,UNUSED,,16,,,,,,,,,
377 B28,,IOB33M,IO_L9P_T1_DQS_16,UNUSED,,16,,,,,,,,,
378 B29,,IOB33S,IO_L15N_T2_DQS_16,UNUSED,,16,,,,,,,,,
379 B30,,IOB33M,IO_L17P_T2_16,UNUSED,,16,,,,,,,,,
380 C1,,,GND,,,,,,,,,,,,
381 C2,,,GND,,,,,,,,,,,,
382 C3,,OPAD,MGTXTXN1_118,UNUSED,,,,,,,,,,,
383 C4,,OPAD,MGTXTXP1_118,UNUSED,,,,,,,,,,,
384 C5,,,MGTAVTT,,,,,,,,,,,,
385 C6,,,GND,,,,,,,,,,,,
386 C7,,IPAD,MGTREFCLK0N_118,UNUSED,,,,,,,,,,,
387 C8,,IPAD,MGTREFCLK0P_118,UNUSED,,,,,,,,,,,
388 C9,,,GND,,,,,,,,,,,,
389 C10,,,VCCBATT_0,,,,,,,,,,,,
390 C11,,IOB33S,IO_L18N_T2_18,UNUSED,,18,,,,,,,,,
391 C12,,IOB33M,IO_L15P_T2_DQS_18,UNUSED,,18,,,,,,,,,
392 C13,,,VCCO_18,,,18,,,,,any******,,,,
393 C14,,IOB33S,IO_L21N_T3_DQS_18,UNUSED,,18,,,,,,,,,
394 C15,,IOB33M,IO_L23P_T3_18,UNUSED,,18,,,,,,,,,
395 C16,,IOB33S,IO_L15N_T2_DQS_17,UNUSED,,17,,,,,,,,,
396 C17,,IOB33M,IO_L17P_T2_17,UNUSED,,17,,,,,,,,,
397 C18,,,GND,,,,,,,,,,,,
398 C19,,IOB33M,IO_L24P_T3_17,UNUSED,,17,,,,,,,,,
399 C20,,IOB33M,IO_L19P_T3_17,UNUSED,,17,,,,,,,,,
400 C21,,IOB33S,IO_L8N_T1_17,UNUSED,,17,,,,,,,,,
401 C22,,IOB33S,IO_L10N_T1_17,UNUSED,,17,,,,,,,,,
402 C23,,,VCCO_16,,,16,,,,,any******,,,,
403 C24,,IOB33M,IO_L8P_T1_16,UNUSED,,16,,,,,,,,,
404 C25,,IOB33M,IO_L12P_T1_MRCC_16,UNUSED,,16,,,,,,,,,
405 C26,,IOB33S,IO_L11N_T1_SRCC_16,UNUSED,,16,,,,,,,,,
406 C27,,IOB33S,IO_L13N_T2_MRCC_16,UNUSED,,16,,,,,,,,,
407 C28,,,GND,,,,,,,,,,,,
408 C29,,IOB33M,IO_L15P_T2_DQS_16,UNUSED,,16,,,,,,,,,
409 C30,,IOB33S,IO_L16N_T2_16,UNUSED,,16,,,,,,,,,
410 D1,,OPAD,MGTXTXN0_118,UNUSED,,,,,,,,,,,
411 D2,,OPAD,MGTXTXP0_118,UNUSED,,,,,,,,,,,
412 D3,,,MGTAVTT,,,,,,,,,,,,
413 D4,,,GND,,,,,,,,,,,,
414 D5,,IPAD,MGTXRXN1_118,UNUSED,,,,,,,,,,,
415 D6,,IPAD,MGTXRXP1_118,UNUSED,,,,,,,,,,,
416 D7,,,MGTAVCC,,,,,,,,,,,,
417 D8,,,GND,,,,,,,,,,,,
418 D9,,,GND,,,,,,,,,,,,
419 D10,,,VCCO_18,,,18,,,,,any******,,,,
420 D11,,IOB33M,IO_L18P_T2_18,UNUSED,,18,,,,,,,,,
421 D12,,IOB33M,IO_L13P_T2_MRCC_18,UNUSED,,18,,,,,,,,,
422 D13,,IOB33S,IO_L13N_T2_MRCC_18,UNUSED,,18,,,,,,,,,
423 D14,,IOB33M,IO_L21P_T3_DQS_18,UNUSED,,18,,,,,,,,,
424 D15,,,GND,,,,,,,,,,,,
425 D16,,IOB33M,IO_L15P_T2_DQS_17,UNUSED,,17,,,,,,,,,
426 D17,,IOB33M,IO_L13P_T2_MRCC_17,UNUSED,,17,,,,,,,,,
427 D18,,IOB33S,IO_L13N_T2_MRCC_17,UNUSED,,17,,,,,,,,,
428 D19,,IOB33S,IO_L14N_T2_SRCC_17,UNUSED,,17,,,,,,,,,
429 D20,,,VCCO_17,,,17,,,,,any******,,,,
430 D21,,IOB33M,IO_L8P_T1_17,UNUSED,,17,,,,,,,,,
431 D22,,IOB33M,IO_L10P_T1_17,UNUSED,,17,,,,,,,,,
432 D23,,IOB33S,IO_L2N_T0_16,UNUSED,,16,,,,,,,,,
433 D24,,IOB33S,IO_L4N_T0_16,UNUSED,,16,,,,,,,,,
434 D25,,,GND,,,,,,,,,,,,
435 D26,,IOB33M,IO_L11P_T1_SRCC_16,UNUSED,,16,,,,,,,,,
436 D27,,IOB33M,IO_L13P_T2_MRCC_16,UNUSED,,16,,,,,,,,,
437 D28,,IOB33S,IO_L14N_T2_SRCC_16,UNUSED,,16,,,,,,,,,
438 D29,,IOB33M,IO_L16P_T2_16,UNUSED,,16,,,,,,,,,
439 D30,,,VCCO_16,,,16,,,,,any******,,,,
440 E1,,,GND,,,,,,,,,,,,
441 E2,,,GND,,,,,,,,,,,,
442 E3,,IPAD,MGTXRXN0_118,UNUSED,,,,,,,,,,,
443 E4,,IPAD,MGTXRXP0_118,UNUSED,,,,,,,,,,,
444 E5,,,MGTAVTT,,,,,,,,,,,,
445 E6,,,GND,,,,,,,,,,,,
446 E7,,IPAD,MGTREFCLK1N_118,UNUSED,,,,,,,,,,,
447 E8,,IPAD,MGTREFCLK1P_118,UNUSED,,,,,,,,,,,
448 E9,,,GND,,,,,,,,,,,,
449 E10,,,TCK_0,,,,,,,,,,,,
450 E11,,IOB33S,IO_L16N_T2_18,UNUSED,,18,,,,,,,,,
451 E12,,,GND,,,,,,,,,,,,
452 E13,,IOB33S,IO_L14N_T2_SRCC_18,UNUSED,,18,,,,,,,,,
453 E14,,IOB33M,IO_L20P_T3_18,UNUSED,,18,,,,,,,,,
454 E15,,IOB33S,IO_L20N_T3_18,UNUSED,,18,,,,,,,,,
455 E16,,IOB33S,IO_L19N_T3_VREF_18,UNUSED,,18,,,,,,,,,
456 E17,,,VCCO_17,,,17,,,,,any******,,,,
457 E18,,IOB33,IO_25_17,UNUSED,,17,,,,,,,,,
458 E19,,IOB33M,IO_L14P_T2_SRCC_17,UNUSED,,17,,,,,,,,,
459 E20,,IOB33S,IO_L12N_T1_MRCC_17,UNUSED,,17,,,,,,,,,
460 E21,,IOB33S,IO_L11N_T1_SRCC_17,UNUSED,,17,,,,,,,,,
461 E22,,,GND,,,,,,,,,,,,
462 E23,,IOB33M,IO_L2P_T0_16,UNUSED,,16,,,,,,,,,
463 E24,,IOB33M,IO_L4P_T0_16,UNUSED,,16,,,,,,,,,
464 E25,,IOB33S,IO_L3N_T0_DQS_16,UNUSED,,16,,,,,,,,,
465 E26,,IOB33S,IO_L5N_T0_16,UNUSED,,16,,,,,,,,,
466 E27,,,VCCO_16,,,16,,,,,any******,,,,
467 E28,,IOB33M,IO_L14P_T2_SRCC_16,UNUSED,,16,,,,,,,,,
468 E29,,IOB33M,IO_L18P_T2_16,UNUSED,,16,,,,,,,,,
469 E30,,IOB33S,IO_L18N_T2_16,UNUSED,,16,,,,,,,,,
470 F1,,OPAD,MGTXTXN3_117,UNUSED,,,,,,,,,,,
471 F2,,OPAD,MGTXTXP3_117,UNUSED,,,,,,,,,,,
472 F3,,,MGTAVTT,,,,,,,,,,,,
473 F4,,,GND,,,,,,,,,,,,
474 F5,,IPAD,MGTXRXN3_117,UNUSED,,,,,,,,,,,
475 F6,,IPAD,MGTXRXP3_117,UNUSED,,,,,,,,,,,
476 F7,,,MGTAVCC,,,,,,,,,,,,
477 F8,,,GND,,,,,,,,,,,,
478 F9,,,GND,,,,,,,,,,,,
479 F10,,,TMS_0,,,,,,,,,,,,
480 F11,,IOB33M,IO_L16P_T2_18,UNUSED,,18,,,,,,,,,
481 F12,,IOB33M,IO_L14P_T2_SRCC_18,UNUSED,,18,,,,,,,,,
482 F13,,IOB33S,IO_L12N_T1_MRCC_18,UNUSED,,18,,,,,,,,,
483 F14,,,VCCO_18,,,18,,,,,any******,,,,
484 F15,,IOB33M,IO_L19P_T3_18,UNUSED,,18,,,,,,,,,
485 F16,,IOB33,IO_25_18,UNUSED,,18,,,,,,,,,
486 F17,,IOB33S,IO_L18N_T2_17,UNUSED,,17,,,,,,,,,
487 F18,,IOB33S,IO_L16N_T2_17,UNUSED,,17,,,,,,,,,
488 F19,,,GND,,,,,,,,,,,,
489 F20,,IOB33M,IO_L12P_T1_MRCC_17,UNUSED,,17,,,,,,,,,
490 F21,,IOB33M,IO_L11P_T1_SRCC_17,UNUSED,,17,,,,,,,,,
491 F22,,IOB33S,IO_L9N_T1_DQS_17,UNUSED,,17,,,,,,,,,
492 F23,,IOB33,IO_0_16,UNUSED,,16,,,,,,,,,
493 F24,,,VCCO_16,,,16,,,,,any******,,,,
494 F25,,IOB33M,IO_L3P_T0_DQS_16,UNUSED,,16,,,,,,,,,
495 F26,,IOB33M,IO_L5P_T0_16,UNUSED,,16,,,,,,,,,
496 F27,,IOB33S,IO_L21N_T3_DQS_16,UNUSED,,16,,,,,,,,,
497 F28,,IOB33S,IO_L20N_T3_16,UNUSED,,16,,,,,,,,,
498 F29,,,GND,,,,,,,,,,,,
499 F30,,IOB33S,IO_L22N_T3_16,UNUSED,,16,,,,,,,,,
500 G1,,,GND,,,,,,,,,,,,
501 G2,,,GND,,,,,,,,,,,,
502 G3,,IPAD,MGTXRXN2_117,UNUSED,,,,,,,,,,,
503 G4,,IPAD,MGTXRXP2_117,UNUSED,,,,,,,,,,,
504 G5,,,MGTAVTT,,,,,,,,,,,,
505 G6,,,GND,,,,,,,,,,,,
506 G7,,IPAD,MGTREFCLK0N_117,UNUSED,,,,,,,,,,,
507 G8,,IPAD,MGTREFCLK0P_117,UNUSED,,,,,,,,,,,
508 G9,,,GND,,,,,,,,,,,,
509 G10,,,TDO_0,,,,,,,,,,,,
510 G11,,,VCCO_18,,,18,,,,,any******,,,,
511 G12,,IOB33,IO_0_18,UNUSED,,18,,,,,,,,,
512 G13,,IOB33M,IO_L12P_T1_MRCC_18,UNUSED,,18,,,,,,,,,
513 G14,,IOB33S,IO_L11N_T1_SRCC_18,UNUSED,,18,,,,,,,,,
514 G15,,IOB33S,IO_L7N_T1_18,UNUSED,,18,,,,,,,,,
515 G16,,,GND,,,,,,,,,,,,
516 G17,,IOB33M,IO_L18P_T2_17,UNUSED,,17,,,,,,,,,
517 G18,,IOB33M,IO_L16P_T2_17,UNUSED,,17,,,,,,,,,
518 G19,,IOB33,IO_0_17,UNUSED,,17,,,,,,,,,
519 G20,,IOB33S,IO_L2N_T0_17,UNUSED,,17,,,,,,,,,
520 G21,,,VCCO_17,,,17,,,,,any******,,,,
521 G22,,IOB33M,IO_L9P_T1_DQS_17,UNUSED,,17,,,,,,,,,
522 G23,,IOB33M,IO_L6P_T0_16,UNUSED,,16,,,,,,,,,
523 G24,,IOB33S,IO_L6N_T0_VREF_16,UNUSED,,16,,,,,,,,,
524 G25,,IOB33,IO_25_16,UNUSED,,16,,,,,,,,,
525 G26,,,GND,,,,,,,,,,,,
526 G27,,IOB33M,IO_L21P_T3_DQS_16,UNUSED,,16,,,,,,,,,
527 G28,,IOB33M,IO_L20P_T3_16,UNUSED,,16,,,,,,,,,
528 G29,,IOB33M,IO_L22P_T3_16,UNUSED,,16,,,,,,,,,
529 G30,,IOB33S,IO_L24N_T3_16,UNUSED,,16,,,,,,,,,
530 H1,,OPAD,MGTXTXN2_117,UNUSED,,,,,,,,,,,
531 H2,,OPAD,MGTXTXP2_117,UNUSED,,,,,,,,,,,
532 H3,,,MGTAVTT,,,,,,,,,,,,
533 H4,,,GND,,,,,,,,,,,,
534 H5,,IPAD,MGTXRXN1_117,UNUSED,,,,,,,,,,,
535 H6,,IPAD,MGTXRXP1_117,UNUSED,,,,,,,,,,,
536 H7,,,MGTAVCC,,,,,,,,,,,,
537 H8,,,GND,,,,,,,,,,,,
538 H9,,,GND,,,,,,,,,,,,
539 H10,,,TDI_0,,,,,,,,,,,,
540 H11,,IOB33M,IO_L10P_T1_18,UNUSED,,18,,,,,,,,,
541 H12,,IOB33S,IO_L10N_T1_18,UNUSED,,18,,,,,,,,,
542 H13,,,GND,,,,,,,,,,,,
543 H14,,IOB33M,IO_L11P_T1_SRCC_18,UNUSED,,18,,,,,,,,,
544 H15,,IOB33M,IO_L7P_T1_18,UNUSED,,18,,,,,,,,,
545 H16,,IOB33S,IO_L9N_T1_DQS_18,UNUSED,,18,,,,,,,,,
546 H17,,IOB33S,IO_L3N_T0_DQS_17,UNUSED,,17,,,,,,,,,
547 H18,,,VCCO_17,,,17,,,,,any******,,,,
548 H19,,IOB33S,IO_L4N_T0_17,UNUSED,,17,,,,,,,,,
549 H20,,IOB33M,IO_L2P_T0_17,UNUSED,,17,,,,,,,,,
550 H21,,IOB33M,IO_L7P_T1_17,UNUSED,,17,,,,,,,,,
551 H22,,IOB33S,IO_L7N_T1_17,UNUSED,,17,,,,,,,,,
552 H23,,,GND,,,,,,,,,,,,
553 H24,,IOB33M,IO_L19P_T3_16,UNUSED,,16,,,,,,,,,
554 H25,,IOB33S,IO_L19N_T3_VREF_16,UNUSED,,16,,,,,,,,,
555 H26,,IOB33M,IO_L23P_T3_16,UNUSED,,16,,,,,,,,,
556 H27,,IOB33S,IO_L23N_T3_16,UNUSED,,16,,,,,,,,,
557 H28,,,VCCO_16,,,16,,,,,any******,,,,
558 H29,,IOB33S,IO_L7N_T1_AD10N_15,UNUSED,,15,,,,,,,,,
559 H30,,IOB33M,IO_L24P_T3_16,UNUSED,,16,,,,,,,,,
560 J1,,,GND,,,,,,,,,,,,
561 J2,,,GND,,,,,,,,,,,,
562 J3,,OPAD,MGTXTXN1_117,UNUSED,,,,,,,,,,,
563 J4,,OPAD,MGTXTXP1_117,UNUSED,,,,,,,,,,,
564 J5,,,MGTAVTT,,,,,,,,,,,,
565 J6,,,GND,,,,,,,,,,,,
566 J7,,IPAD,MGTREFCLK1N_117,UNUSED,,,,,,,,,,,
567 J8,,IPAD,MGTREFCLK1P_117,UNUSED,,,,,,,,,,,
568 J9,,,GND,,,,,,,,,,,,
569 J10,,,GND,,,,,,,,,,,,
570 J11,,IOB33M,IO_L8P_T1_18,UNUSED,,18,,,,,,,,,
571 J12,,IOB33S,IO_L8N_T1_18,UNUSED,,18,,,,,,,,,
572 J13,,IOB33S,IO_L4N_T0_18,UNUSED,,18,,,,,,,,,
573 J14,,IOB33S,IO_L5N_T0_18,UNUSED,,18,,,,,,,,,
574 J15,,,VCCO_18,,,18,,,,,any******,,,,
575 J16,,IOB33M,IO_L9P_T1_DQS_18,UNUSED,,18,,,,,,,,,
576 J17,,IOB33M,IO_L3P_T0_DQS_17,UNUSED,,17,,,,,,,,,
577 J18,,IOB33S,IO_L1N_T0_17,UNUSED,,17,,,,,,,,,
578 J19,,IOB33M,IO_L4P_T0_17,UNUSED,,17,,,,,,,,,
579 J20,,,GND,,,,,,,,,,,,
580 J21,,IOB33M,IO_L5P_T0_AD2P_15,UNUSED,,15,,,,,,,,,
581 J22,,IOB33S,IO_L5N_T0_AD2N_15,UNUSED,,15,,,,,,,,,
582 J23,,IOB33M,IO_L1P_T0_AD0P_15,UNUSED,,15,,,,,,,,,
583 J24,,IOB33S,IO_L1N_T0_AD0N_15,UNUSED,,15,,,,,,,,,
584 J25,,,VCCO_15,,,15,,,,,any******,,,,
585 J26,,IOB33S,IO_L10N_T1_AD4N_15,UNUSED,,15,,,,,,,,,
586 J27,,IOB33M,IO_L8P_T1_AD3P_15,UNUSED,,15,,,,,,,,,
587 J28,,IOB33S,IO_L8N_T1_AD3N_15,UNUSED,,15,,,,,,,,,
588 J29,,IOB33M,IO_L7P_T1_AD10P_15,UNUSED,,15,,,,,,,,,
589 J30,,,GND,,,,,,,,,,,,
590 K1,,OPAD,MGTXTXN0_117,UNUSED,,,,,,,,,,,
591 K2,,OPAD,MGTXTXP0_117,UNUSED,,,,,,,,,,,
592 K3,,,MGTAVTT,,,,,,,,,,,,
593 K4,,,GND,,,,,,,,,,,,
594 K5,,IPAD,MGTXRXN0_117,UNUSED,,,,,,,,,,,
595 K6,,IPAD,MGTXRXP0_117,UNUSED,,,,,,,,,,,
596 K7,,,MGTAVCC,,,,,,,,,,,,
597 K8,,,GND,,,,,,,,,,,,
598 K9,,,GND,,,,,,,,,,,,
599 K10,,,PROGRAM_B_0,,,,,,,,,,,,
600 K11,,IOB33S,IO_L6N_T0_VREF_18,UNUSED,,18,,,,,,,,,
601 K12,,,VCCO_18,,,18,,,,,any******,,,,
602 K13,,IOB33M,IO_L4P_T0_18,UNUSED,,18,,,,,,,,,
603 K14,,IOB33M,IO_L5P_T0_18,UNUSED,,18,,,,,,,,,
604 K15,,IOB33S,IO_L2N_T0_18,UNUSED,,18,,,,,,,,,
605 K16,,IOB33S,IO_L1N_T0_18,UNUSED,,18,,,,,,,,,
606 K17,,,GND,,,,,,,,,,,,
607 K18,,IOB33M,IO_L1P_T0_17,UNUSED,,17,,,,,,,,,
608 K19,,IOB33M,IO_L6P_T0_17,UNUSED,,17,,,,,,,,,
609 K20,,IOB33S,IO_L6N_T0_VREF_17,UNUSED,,17,,,,,,,,,
610 K21,,IOB33S,IO_L4N_T0_AD9N_15,UNUSED,,15,,,,,,,,,
611 K22,,,VCCO_15,,,15,,,,,any******,,,,
612 K23,,IOB33M,IO_L3P_T0_DQS_AD1P_15,UNUSED,,15,,,,,,,,,
613 K24,,IOB33S,IO_L3N_T0_DQS_AD1N_15,UNUSED,,15,,,,,,,,,
614 K25,,IOB33S,IO_L12N_T1_MRCC_AD5N_15,UNUSED,,15,,,,,,,,,
615 K26,,IOB33M,IO_L10P_T1_AD4P_15,UNUSED,,15,,,,,,,,,
616 K27,,,GND,,,,,,,,,,,,
617 K28,,IOB33M,IO_L13P_T2_MRCC_15,UNUSED,,15,,,,,,,,,
618 K29,,IOB33S,IO_L13N_T2_MRCC_15,UNUSED,,15,,,,,,,,,
619 K30,,IOB33S,IO_L9N_T1_DQS_AD11N_15,UNUSED,,15,,,,,,,,,
620 L1,,,GND,,,,,,,,,,,,
621 L2,,,GND,,,,,,,,,,,,
622 L3,,OPAD,MGTXTXN3_116,UNUSED,,,,,,,,,,,
623 L4,,OPAD,MGTXTXP3_116,UNUSED,,,,,,,,,,,
624 L5,,,MGTAVTT,,,,,,,,,,,,
625 L6,,,GND,,,,,,,,,,,,
626 L7,,IPAD,MGTREFCLK0N_116,UNUSED,,,,,,,,,,,
627 L8,,IPAD,MGTREFCLK0P_116,UNUSED,,,,,,,,,,,
628 L9,,,GND,,,,,,,,,,,,
629 L10,,,CFGBVS_0,,,,,,,,,,,,
630 L11,,IOB33M,IO_L6P_T0_18,UNUSED,,18,,,,,,,,,
631 L12,,IOB33M,IO_L3P_T0_DQS_18,UNUSED,,18,,,,,,,,,
632 L13,,IOB33S,IO_L3N_T0_DQS_18,UNUSED,,18,,,,,,,,,
633 L14,,,GND,,,,,,,,,,,,
634 L15,,IOB33M,IO_L2P_T0_18,UNUSED,,18,,,,,,,,,
635 L16,,IOB33M,IO_L1P_T0_18,UNUSED,,18,,,,,,,,,
636 L17,,IOB33M,IO_L5P_T0_17,UNUSED,,17,,,,,,,,,
637 L18,,IOB33S,IO_L5N_T0_17,UNUSED,,17,,,,,,,,,
638 L19,,,VCCO_17,,,17,,,,,any******,,,,
639 L20,,IOB33S,IO_L6N_T0_VREF_15,UNUSED,,15,,,,,,,,,
640 L21,,IOB33M,IO_L4P_T0_AD9P_15,UNUSED,,15,,,,,,,,,
641 L22,,IOB33M,IO_L2P_T0_AD8P_15,UNUSED,,15,,,,,,,,,
642 L23,,IOB33S,IO_L2N_T0_AD8N_15,UNUSED,,15,,,,,,,,,
643 L24,,,GND,,,,,,,,,,,,
644 L25,,IOB33M,IO_L12P_T1_MRCC_AD5P_15,UNUSED,,15,,,,,,,,,
645 L26,,IOB33M,IO_L11P_T1_SRCC_AD12P_15,UNUSED,,15,,,,,,,,,
646 L27,,IOB33S,IO_L11N_T1_SRCC_AD12N_15,UNUSED,,15,,,,,,,,,
647 L28,,IOB33S,IO_L14N_T2_SRCC_15,UNUSED,,15,,,,,,,,,
648 L29,,,VCCO_15,,,15,,,,,any******,,,,
649 L30,,IOB33M,IO_L9P_T1_DQS_AD11P_15,UNUSED,,15,,,,,,,,,
650 M1,,OPAD,MGTXTXN2_116,UNUSED,,,,,,,,,,,
651 M2,,OPAD,MGTXTXP2_116,UNUSED,,,,,,,,,,,
652 M3,,,MGTAVTT,,,,,,,,,,,,
653 M4,,,GND,,,,,,,,,,,,
654 M5,,IPAD,MGTXRXN3_116,UNUSED,,,,,,,,,,,
655 M6,,IPAD,MGTXRXP3_116,UNUSED,,,,,,,,,,,
656 M7,,,MGTAVCC,,,,,,,,,,,,
657 M8,,,GND,,,,,,,,,,,,
658 M9,,,GND,,,,,,,,,,,,
659 M10,,,DONE_0,,,,,,,,,,,,
660 M11,,,VCCINT,,,,,,,,1.0,,,,
661 M12,,,GND,,,,,,,,,,,,
662 M13,,,VCCINT,,,,,,,,1.0,,,,
663 M14,,,GND,,,,,,,,,,,,
664 M15,,,VCCINT,,,,,,,,1.0,,,,
665 M16,,,GND,,,,,,,,,,,,
666 M17,,,VCCINT,,,,,,,,1.0,,,,
667 M18,,,GND,,,,,,,,,,,,
668 M19,,IOB33,IO_0_15,UNUSED,,15,,,,,,,,,
669 M20,,IOB33M,IO_L6P_T0_15,UNUSED,,15,,,,,,,,,
670 M21,,,GND,,,,,,,,,,,,
671 M22,,IOB33M,IO_L24P_T3_RS1_15,UNUSED,,15,,,,,,,,,
672 M23,,IOB33S,IO_L24N_T3_RS0_15,UNUSED,,15,,,,,,,,,
673 M24,,IOB33M,IO_L23P_T3_FOE_B_15,UNUSED,,15,,,,,,,,,
674 M25,,IOB33S,IO_L23N_T3_FWE_B_15,UNUSED,,15,,,,,,,,,
675 M26,,,VCCO_15,,,15,,,,,any******,,,,
676 M27,,IOB33S,IO_L16N_T2_A27_15,UNUSED,,15,,,,,,,,,
677 M28,,IOB33M,IO_L14P_T2_SRCC_15,UNUSED,,15,,,,,,,,,
678 M29,,IOB33M,IO_L15P_T2_DQS_15,UNUSED,,15,,,,,,,,,
679 M30,,IOB33S,IO_L15N_T2_DQS_ADV_B_15,UNUSED,,15,,,,,,,,,
680 N1,,,GND,,,,,,,,,,,,
681 N2,,,GND,,,,,,,,,,,,
682 N3,,OPAD,MGTXTXN1_116,UNUSED,,,,,,,,,,,
683 N4,,OPAD,MGTXTXP1_116,UNUSED,,,,,,,,,,,
684 N5,,,MGTAVTT,,,,,,,,,,,,
685 N6,,,GND,,,,,,,,,,,,
686 N7,,IPAD,MGTREFCLK1N_116,UNUSED,,,,,,,,,,,
687 N8,,IPAD,MGTREFCLK1P_116,UNUSED,,,,,,,,,,,
688 N9,,,GND,,,,,,,,,,,,
689 N10,,,VCCINT,,,,,,,,1.0,,,,
690 N11,,,GND,,,,,,,,,,,,
691 N12,,,VCCINT,,,,,,,,1.0,,,,
692 N13,,,GND,,,,,,,,,,,,
693 N14,,,VCCINT,,,,,,,,1.0,,,,
694 N15,,,GND,,,,,,,,,,,,
695 N16,,,VCCBRAM,,,,,,,,,,,,
696 N17,,,GND,,,,,,,,,,,,
697 N18,,,VCCINT,,,,,,,,1.0,,,,
698 N19,,IOB33M,IO_L19P_T3_A22_15,UNUSED,,15,,,,,,,,,
699 N20,,IOB33S,IO_L19N_T3_A21_VREF_15,UNUSED,,15,,,,,,,,,
700 N21,,IOB33M,IO_L20P_T3_A20_15,UNUSED,,15,,,,,,,,,
701 N22,,IOB33S,IO_L20N_T3_A19_15,UNUSED,,15,,,,,,,,,
702 N23,,,VCCO_15,,,15,,,,,any******,,,,
703 N24,,IOB33S,IO_L21N_T3_DQS_A18_15,UNUSED,,15,,,,,,,,,
704 N25,,IOB33M,IO_L18P_T2_A24_15,UNUSED,,15,,,,,,,,,
705 N26,,IOB33S,IO_L18N_T2_A23_15,UNUSED,,15,,,,,,,,,
706 N27,,IOB33M,IO_L16P_T2_A28_15,UNUSED,,15,,,,,,,,,
707 N28,,,GND,,,,,,,,,,,,
708 N29,,IOB33M,IO_L17P_T2_A26_15,UNUSED,,15,,,,,,,,,
709 N30,,IOB33S,IO_L17N_T2_A25_15,UNUSED,,15,,,,,,,,,
710 P1,,OPAD,MGTXTXN0_116,UNUSED,,,,,,,,,,,
711 P2,,OPAD,MGTXTXP0_116,UNUSED,,,,,,,,,,,
712 P3,,,MGTAVTT,,,,,,,,,,,,
713 P4,,,GND,,,,,,,,,,,,
714 P5,,IPAD,MGTXRXN2_116,UNUSED,,,,,,,,,,,
715 P6,,IPAD,MGTXRXP2_116,UNUSED,,,,,,,,,,,
716 P7,,,MGTAVCC,,,,,,,,,,,,
717 P8,,,GND,,,,,,,,,,,,
718 P9,,,GND,,,,,,,,,,,,
719 P10,,,GND,,,,,,,,,,,,
720 P11,,,VCCINT,,,,,,,,1.0,,,,
721 P12,,,GND,,,,,,,,,,,,
722 P13,,,VCCAUX,,,,,,,,1.8,,,,
723 P14,,,GNDADC_0,,,,,,,,,,,,
724 P15,,,VCCADC_0,,,,,,,,,,,,
725 P16,,,GND,,,,,,,,,,,,
726 P17,,,VCCINT,,,,,,,,1.0,,,,
727 P18,,,GND,,,,,,,,,,,,
728 P19,,IOB33,IO_25_15,UNUSED,,15,,,,,,,,,
729 P20,,,VCCO_15,,,15,,,,,any******,,,,
730 P21,,IOB33M,IO_L22P_T3_A17_15,UNUSED,,15,,,,,,,,,
731 P22,,IOB33S,IO_L22N_T3_A16_15,UNUSED,,15,,,,,,,,,
732 P23,,IOB33M,IO_L21P_T3_DQS_15,UNUSED,,15,,,,,,,,,
733 P24,,IOB33M,IO_L1P_T0_D00_MOSI_14,UNUSED,,14,,,,,,,,,
734 P25,,,GND,,,,,,,,,,,,
735 P26,,IOB33M,IO_L10P_T1_D14_14,UNUSED,,14,,,,,,,,,
736 P27,,IOB33M,IO_L8P_T1_D11_14,UNUSED,,14,,,,,,,,,
737 P28,,IOB33S,IO_L8N_T1_D12_14,UNUSED,,14,,,,,,,,,
738 P29,,IOB33M,IO_L7P_T1_D09_14,UNUSED,,14,,,,,,,,,
739 P30,,,VCCO_14,,,14,,,,,any******,,,,
740 R1,,,GND,,,,,,,,,,,,
741 R2,,,GND,,,,,,,,,,,,
742 R3,,IPAD,MGTXRXN1_116,UNUSED,,,,,,,,,,,
743 R4,,IPAD,MGTXRXP1_116,UNUSED,,,,,,,,,,,
744 R5,,,MGTAVTT,,,,,,,,,,,,
745 R6,,,GND,,,,,,,,,,,,
746 R7,,IPAD,MGTREFCLK0N_115,UNUSED,,,,,,,,,,,
747 R8,,IPAD,MGTREFCLK0P_115,UNUSED,,,,,,,,,,,
748 R9,,,GND,,,,,,,,,,,,
749 R10,,,VCCINT,,,,,,,,1.0,,,,
750 R11,,,GND,,,,,,,,,,,,
751 R12,,,VCCINT,,,,,,,,1.0,,,,
752 R13,,,GND,,,,,,,,,,,,
753 R14,,,VREFN_0,,,,,,,,,,,,
754 R15,,IPAD,VP_0,UNUSED,,0,,,,,,,,,
755 R16,,,VCCBRAM,,,,,,,,,,,,
756 R17,,,GND,,,,,,,,,,,,
757 R18,,,VCCINT,,,,,,,,1.0,,,,
758 R19,,IOB33,IO_0_14,UNUSED,,14,,,,,,,,,
759 R20,,IOB33M,IO_L2P_T0_D02_14,UNUSED,,14,,,,,,,,,
760 R21,,IOB33S,IO_L2N_T0_D03_14,UNUSED,,14,,,,,,,,,
761 R22,,,GND,,,,,,,,,,,,
762 R23,,IOB33M,IO_L3P_T0_DQS_PUDC_B_14,UNUSED,,14,,,,,,,,,
763 R24,,IOB33S,IO_L3N_T0_DQS_EMCCLK_14,UNUSED,,14,,,,,,,,,
764 R25,,IOB33S,IO_L1N_T0_D01_DIN_14,UNUSED,,14,,,,,,,,,
765 R26,,IOB33S,IO_L10N_T1_D15_14,UNUSED,,14,,,,,,,,,
766 R27,,,VCCO_14,,,14,,,,,any******,,,,
767 R28,,IOB33M,IO_L11P_T1_SRCC_14,UNUSED,,14,,,,,,,,,
768 R29,,IOB33S,IO_L7N_T1_D10_14,UNUSED,,14,,,,,,,,,
769 R30,,IOB33M,IO_L9P_T1_DQS_14,UNUSED,,14,,,,,,,,,
770 T1,,OPAD,MGTXTXN3_115,UNUSED,,,,,,,,,,,
771 T2,,OPAD,MGTXTXP3_115,UNUSED,,,,,,,,,,,
772 T3,,,MGTAVTT,,,,,,,,,,,,
773 T4,,,GND,,,,,,,,,,,,
774 T5,,IPAD,MGTXRXN0_116,UNUSED,,,,,,,,,,,
775 T6,,IPAD,MGTXRXP0_116,UNUSED,,,,,,,,,,,
776 T7,,,MGTVCCAUX,,,,,,,,,,,,
777 T8,,,GND,,,,,,,,,,,,
778 T9,,,VCCO_0,,,0,,,,,any******,,,,
779 T10,,,GND,,,,,,,,,,,,
780 T11,,,VCCINT,,,,,,,,1.0,,,,
781 T12,,,GND,,,,,,,,,,,,
782 T13,,,VCCAUX,,,,,,,,1.8,,,,
783 T14,,IPAD,VN_0,UNUSED,,0,,,,,,,,,
784 T15,,,VREFP_0,,,,,,,,,,,,
785 T16,,,GND,,,,,,,,,,,,
786 T17,,,VCCINT,,,,,,,,1.0,,,,
787 T18,,,GND,,,,,,,,,,,,
788 T19,,,GND,,,,,,,,,,,,
789 T20,,IOB33M,IO_L4P_T0_D04_14,UNUSED,,14,,,,,,,,,
790 T21,,IOB33S,IO_L4N_T0_D05_14,UNUSED,,14,,,,,,,,,
791 T22,,IOB33M,IO_L5P_T0_D06_14,UNUSED,,14,,,,,,,,,
792 T23,,IOB33S,IO_L5N_T0_D07_14,UNUSED,,14,,,,,,,,,
793 T24,,,VCCO_14,,,14,,,,,any******,,,,
794 T25,,IOB33M,IO_L14P_T2_SRCC_14,UNUSED,,14,,,,,,,,,
795 T26,,IOB33M,IO_L12P_T1_MRCC_14,UNUSED,,14,,,,,,,,,
796 T27,,IOB33S,IO_L12N_T1_MRCC_14,UNUSED,,14,,,,,,,,,
797 T28,,IOB33S,IO_L11N_T1_SRCC_14,UNUSED,,14,,,,,,,,,
798 T29,,,GND,,,,,,,,,,,,
799 T30,,IOB33S,IO_L9N_T1_DQS_D13_14,UNUSED,,14,,,,,,,,,
800 U1,,,GND,,,,,,,,,,,,
801 U2,,,GND,,,,,,,,,,,,
802 U3,,OPAD,MGTXTXN2_115,UNUSED,,,,,,,,,,,
803 U4,,OPAD,MGTXTXP2_115,UNUSED,,,,,,,,,,,
804 U5,,,MGTAVTT,,,,,,,,,,,,
805 U6,,,GND,,,,,,,,,,,,
806 U7,,IPAD,MGTREFCLK1N_115,UNUSED,,,,,,,,,,,
807 U8,,IPAD,MGTREFCLK1P_115,UNUSED,,,,,,,,,,,
808 U9,,,GND,,,,,,,,,,,,
809 U10,,,VCCINT,,,,,,,,1.0,,,,
810 U11,,,GND,,,,,,,,,,,,
811 U12,,,VCCINT,,,,,,,,1.0,,,,
812 U13,,,GND,,,,,,,,,,,,
813 U14,,,DXN_0,,,,,,,,,,,,
814 U15,,,DXP_0,,,,,,,,,,,,
815 U16,,,VCCBRAM,,,,,,,,,,,,
816 U17,,,GND,,,,,,,,,,,,
817 U18,,,VCCINT,,,,,,,,1.0,,,,
818 U19,,IOB33M,IO_L6P_T0_FCS_B_14,UNUSED,,14,,,,,,,,,
819 U20,,IOB33S,IO_L6N_T0_D08_VREF_14,UNUSED,,14,,,,,,,,,
820 U21,,,VCCO_14,,,14,,,,,any******,,,,
821 U22,,IOB33M,IO_L21P_T3_DQS_14,UNUSED,,14,,,,,,,,,
822 U23,,IOB33S,IO_L21N_T3_DQS_A06_D22_14,UNUSED,,14,,,,,,,,,
823 U24,,IOB33M,IO_L23P_T3_A03_D19_14,UNUSED,,14,,,,,,,,,
824 U25,,IOB33S,IO_L14N_T2_SRCC_14,UNUSED,,14,,,,,,,,,
825 U26,,,GND,,,,,,,,,,,,
826 U27,,IOB33M,IO_L13P_T2_MRCC_14,UNUSED,,14,,,,,,,,,
827 U28,,IOB33S,IO_L13N_T2_MRCC_14,UNUSED,,14,,,,,,,,,
828 U29,,IOB33M,IO_L15P_T2_DQS_RDWR_B_14,UNUSED,,14,,,,,,,,,
829 U30,,IOB33S,IO_L15N_T2_DQS_DOUT_CSO_B_14,UNUSED,,14,,,,,,,,,
830 V1,,OPAD,MGTXTXN1_115,UNUSED,,,,,,,,,,,
831 V2,,OPAD,MGTXTXP1_115,UNUSED,,,,,,,,,,,
832 V3,,,MGTAVTT,,,,,,,,,,,,
833 V4,,,GND,,,,,,,,,,,,
834 V5,,IPAD,MGTXRXN3_115,UNUSED,,,,,,,,,,,
835 V6,,IPAD,MGTXRXP3_115,UNUSED,,,,,,,,,,,
836 V7,,,MGTVCCAUX,,,,,,,,,,,,
837 V8,,,GND,,,,,,,,,,,,
838 V9,,,GND,,,,,,,,,,,,
839 V10,,,GND,,,,,,,,,,,,
840 V11,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
841 V12,,,GND,,,,,,,,,,,,
842 V13,,,VCCAUX,,,,,,,,1.8,,,,
843 V14,,,GND,,,,,,,,,,,,
844 V15,,,VCCAUX,,,,,,,,1.8,,,,
845 V16,,,GND,,,,,,,,,,,,
846 V17,,,VCCINT,,,,,,,,1.0,,,,
847 V18,,,GND,,,,,,,,,,,,
848 V19,,IOB33M,IO_L19P_T3_A10_D26_14,UNUSED,,14,,,,,,,,,
849 V20,,IOB33S,IO_L19N_T3_A09_D25_VREF_14,UNUSED,,14,,,,,,,,,
850 V21,,IOB33M,IO_L22P_T3_A05_D21_14,UNUSED,,14,,,,,,,,,
851 V22,,IOB33S,IO_L22N_T3_A04_D20_14,UNUSED,,14,,,,,,,,,
852 V23,,,GND,,,,,,,,,,,,
853 V24,,IOB33S,IO_L23N_T3_A02_D18_14,UNUSED,,14,,,,,,,,,
854 V25,,IOB33M,IO_L18P_T2_A12_D28_14,UNUSED,,14,,,,,,,,,
855 V26,,IOB33M,IO_L16P_T2_CSI_B_14,UNUSED,,14,,,,,,,,,
856 V27,,IOB33S,IO_L16N_T2_A15_D31_14,UNUSED,,14,,,,,,,,,
857 V28,,,VCCO_14,,,14,,,,,any******,,,,
858 V29,,IOB33M,IO_L17P_T2_A14_D30_14,UNUSED,,14,,,,,,,,,
859 V30,,IOB33S,IO_L17N_T2_A13_D29_14,UNUSED,,14,,,,,,,,,
860 W1,,,GND,,,,,,,,,,,,
861 W2,,,GND,,,,,,,,,,,,
862 W3,,IPAD,MGTXRXN2_115,UNUSED,,,,,,,,,,,
863 W4,,IPAD,MGTXRXP2_115,UNUSED,,,,,,,,,,,
864 W5,,,MGTAVTT,,,,,,,,,,,,
865 W6,,,GND,,,,,,,,,,,,
866 W7,,,MGTAVTTRCAL_115,,,,,,,,,,,,
867 W8,,,MGTRREF_115,,,,,,,,,,,,
868 W9,,,GND,,,,,,,,,,,,
869 W10,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
870 W11,,,GND,,,,,,,,,,,,
871 W12,,,VCCAUX_IO_G0,,,,,,,,1.8,,,,
872 W13,,,GND,,,,,,,,,,,,
873 W14,,,VCCAUX,,,,,,,,1.8,,,,
874 W15,,,GND,,,,,,,,,,,,
875 W16,,,VCCBRAM,,,,,,,,,,,,
876 W17,,,GND,,,,,,,,,,,,
877 W18,,,VCCINT,,,,,,,,1.0,,,,
878 W19,,IOB33,IO_25_14,UNUSED,,14,,,,,,,,,
879 W20,,,GND,,,,,,,,,,,,
880 W21,,IOB33M,IO_L24P_T3_A01_D17_14,UNUSED,,14,,,,,,,,,
881 W22,,IOB33S,IO_L24N_T3_A00_D16_14,UNUSED,,14,,,,,,,,,
882 W23,,IOB33M,IO_L20P_T3_A08_D24_14,UNUSED,,14,,,,,,,,,
883 W24,,IOB33S,IO_L20N_T3_A07_D23_14,UNUSED,,14,,,,,,,,,
884 W25,,,VCCO_14,,,14,,,,,any******,,,,
885 W26,,IOB33S,IO_L18N_T2_A11_D27_14,UNUSED,,14,,,,,,,,,
886 W27,,IOB33M,IO_L2P_T0_13,UNUSED,,13,,,,,,,,,
887 W28,,IOB33S,IO_L2N_T0_13,UNUSED,,13,,,,,,,,,
888 W29,,IOB33M,IO_L4P_T0_13,UNUSED,,13,,,,,,,,,
889 W30,,,GND,,,,,,,,,,,,
890 Y1,,OPAD,MGTXTXN0_115,UNUSED,,,,,,,,,,,
891 Y2,,OPAD,MGTXTXP0_115,UNUSED,,,,,,,,,,,
892 Y3,,,GND,,,,,,,,,,,,
893 Y4,,,GND,,,,,,,,,,,,
894 Y5,,IPAD,MGTXRXN1_115,UNUSED,,,,,,,,,,,
895 Y6,,IPAD,MGTXRXP1_115,UNUSED,,,,,,,,,,,
896 Y7,,,GND,,,,,,,,,,,,
897 Y8,,,GND,,,,,,,,,,,,
898 Y9,,,GND,,,,,,,,,,,,
899 Y10,ddr3_addr<9>,IOB18,IO_L4N_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
900 Y11,ddr3_addr<10>,IOB18,IO_L4P_T0_33,OUTPUT,SSTL15,33,,FAST,,,,LOCATED,NO,NONE,
901 Y12,,,VCCO_33,,,33,,,,,1.50,,,,
902 Y13,,IOB18,IO_0_VRN_33,UNUSED,,33,,,,,,,,,
903 Y14,,IOB18,IO_0_VRN_32,UNUSED,,32,,,,,,,,,
904 Y15,,IOB18S,IO_L24N_T3_32,UNUSED,,32,,,,,,,,,
905 Y16,,IOB18M,IO_L24P_T3_32,UNUSED,,32,,,,,,,,,
906 Y17,,,GND,,,,,,,,,,,,
907 Y18,,IOB18S,IO_L15N_T2_DQS_32,UNUSED,,32,,,,,,,,,
908 Y19,,IOB18M,IO_L15P_T2_DQS_32,UNUSED,,32,,,,,,,,,
909 Y20,,IOB33,IO_0_12,UNUSED,,12,,,,,,,,,
910 Y21,,IOB33M,IO_L2P_T0_12,UNUSED,,12,,,,,,,,,
911 Y22,,,VCCO_12,,,12,,,,,any******,,,,
912 Y23,,IOB33M,IO_L1P_T0_12,UNUSED,,12,,,,,,,,,
913 Y24,,IOB33S,IO_L1N_T0_12,UNUSED,,12,,,,,,,,,
914 Y25,,IOB33,IO_0_13,UNUSED,,13,,,,,,,,,
915 Y26,,IOB33M,IO_L1P_T0_13,UNUSED,,13,,,,,,,,,
916 Y27,,,GND,,,,,,,,,,,,
917 Y28,,IOB33M,IO_L3P_T0_DQS_13,UNUSED,,13,,,,,,,,,
918 Y29,,IOB33S,IO_L4N_T0_13,UNUSED,,13,,,,,,,,,
919 Y30,tg_compare_error,IOB33,IO_L8P_T1_13,OUTPUT,LVCMOS33,13,12,SLOW,,,,LOCATED,NO,NONE,
920 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
921 #
922 #* Default value.
923 #** This default Pullup/Pulldown value can be overridden in Bitgen.
924 #All RSVD_0 pins must be tied to GROUND.
925 #****** Special VCCO requirements may apply. Please consult the device
926 # family datasheet for specific guideline on VCCO requirements.
927 #
928 #
929 #
top/x300/coregen/ddr3_32bit/example_design/par/example_top_pad.txt
+931
View File
@@ -0,0 +1,931 @@
Release 14.4 - par P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Tue Jan 22 18:32:42 2013
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: example_top_map.ncd
OUTPUT FILE: example_top_pad.txt
PART TYPE: xc7k410t
SPEED GRADE: -2
PACKAGE: ffg900
Pinout by Pin Number:
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name |Pin Usage|Pin Name |Direction |IO Standard |IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | | |GND | | | | | | | | | | | |
|A3 | |OPAD |MGTXTXN3_118 |UNUSED | | | | | | | | | | |
|A4 | |OPAD |MGTXTXP3_118 |UNUSED | | | | | | | | | | |
|A5 | | |GND | | | | | | | | | | | |
|A6 | | |GND | | | | | | | | | | | |
|A7 | |IPAD |MGTXRXN3_118 |UNUSED | | | | | | | | | | |
|A8 | |IPAD |MGTXRXP3_118 |UNUSED | | | | | | | | | | |
|A9 | | |GND | | | | | | | | | | | |
|A10 | | |INIT_B_0 | | | | | | | | | | | |
|A11 | |IOB33M |IO_L17P_T2_18 |UNUSED | |18 | | | | | | | | |
|A12 | |IOB33S |IO_L17N_T2_18 |UNUSED | |18 | | | | | | | | |
|A13 | |IOB33S |IO_L22N_T3_18 |UNUSED | |18 | | | | | | | | |
|A14 | | |GND | | | | | | | | | | | |
|A15 | |IOB33S |IO_L24N_T3_18 |UNUSED | |18 | | | | | | | | |
|A16 | |IOB33M |IO_L20P_T3_17 |UNUSED | |17 | | | | | | | | |
|A17 | |IOB33S |IO_L20N_T3_17 |UNUSED | |17 | | | | | | | | |
|A18 | |IOB33S |IO_L22N_T3_17 |UNUSED | |17 | | | | | | | | |
|A19 | | |VCCO_17 | | |17 | | | | |any******| | | |
|A20 | |IOB33M |IO_L21P_T3_DQS_17 |UNUSED | |17 | | | | | | | | |
|A21 | |IOB33S |IO_L21N_T3_DQS_17 |UNUSED | |17 | | | | | | | | |
|A22 | |IOB33S |IO_L23N_T3_17 |UNUSED | |17 | | | | | | | | |
|A23 | |IOB33S |IO_L1N_T0_16 |UNUSED | |16 | | | | | | | | |
|A24 | | |GND | | | | | | | | | | | |
|A25 | |IOB33M |IO_L10P_T1_16 |UNUSED | |16 | | | | | | | | |
|A26 | |IOB33S |IO_L10N_T1_16 |UNUSED | |16 | | | | | | | | |
|A27 | |IOB33S |IO_L7N_T1_16 |UNUSED | |16 | | | | | | | | |
|A28 | |IOB33S |IO_L9N_T1_DQS_16 |UNUSED | |16 | | | | | | | | |
|A29 | | |VCCO_16 | | |16 | | | | |any******| | | |
|A30 | |IOB33S |IO_L17N_T2_16 |UNUSED | |16 | | | | | | | | |
|AA1 | | |GND | | | | | | | | | | | |
|AA2 | | |GND | | | | | | | | | | | |
|AA3 | |IPAD |MGTXRXN0_115 |UNUSED | | | | | | | | | | |
|AA4 | |IPAD |MGTXRXP0_115 |UNUSED | | | | | | | | | | |
|AA5 | | |GND | | | | | | | | | | | |
|AA6 | | |GND | | | | | | | | | | | |
|AA7 | | |GND | | | | | | | | | | | |
|AA8 |ddr3_addr<12> |IOB18 |IO_L2P_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AA9 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|AA10 |ddr3_addr<7> |IOB18 |IO_L5N_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AA11 |ddr3_addr<8> |IOB18 |IO_L5P_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AA12 |ddr3_addr<14> |IOB18 |IO_L1P_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AA13 |ddr3_addr<6> |IOB18 |IO_L6P_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AA14 | | |GND | | | | | | | | | | | |
|AA15 | |IOB18M |IO_L20P_T3_32 |UNUSED | |32 | | | | | | | | |
|AA16 | |IOB18S |IO_L23N_T3_32 |UNUSED | |32 | | | | | | | | |
|AA17 | |IOB18M |IO_L23P_T3_32 |UNUSED | |32 | | | | | | | | |
|AA18 | |IOB18M |IO_L16P_T2_32 |UNUSED | |32 | | | | | | | | |
|AA19 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AA20 | |IOB33M |IO_L6P_T0_12 |UNUSED | |12 | | | | | | | | |
|AA21 | |IOB33S |IO_L2N_T0_12 |UNUSED | |12 | | | | | | | | |
|AA22 | |IOB33M |IO_L4P_T0_12 |UNUSED | |12 | | | | | | | | |
|AA23 | |IOB33S |IO_L4N_T0_12 |UNUSED | |12 | | | | | | | | |
|AA24 | | |GND | | | | | | | | | | | |
|AA25 | |IOB33M |IO_L6P_T0_13 |UNUSED | |13 | | | | | | | | |
|AA26 | |IOB33S |IO_L1N_T0_13 |UNUSED | |13 | | | | | | | | |
|AA27 | |IOB33M |IO_L5P_T0_13 |UNUSED | |13 | | | | | | | | |
|AA28 | |IOB33S |IO_L3N_T0_DQS_13 |UNUSED | |13 | | | | | | | | |
|AA29 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AA30 |init_calib_complete|IOB33 |IO_L8N_T1_13 |OUTPUT |LVCMOS33 |13 |12 |SLOW | | | |LOCATED |NO |NONE |
|AB1 | | |M2_0 | | | | | | | | | | | |
|AB2 | | |M1_0 | | | | | | | | | | | |
|AB3 | | |GND | | | | | | | | | | | |
|AB4 | | |GND | | | | | | | | | | | |
|AB5 | | |M0_0 | | | | | | | | | | | |
|AB6 | | |VCCO_0 | | |0 | | | | |any******| | | |
|AB7 | |IOB18 |IO_25_VRP_34 |Termination Required| |34 | | |TERMINATION| | | | | |
|AB8 |ddr3_addr<11> |IOB18 |IO_L2N_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AB9 |ddr3_ck_p<0> |IOB18M |IO_L3P_T0_DQS_33 |OUTPUT |DIFF_SSTL15 |33 | |FAST | | | |LOCATED |YES |NONE |
|AB10 |ddr3_addr<4> |IOB18 |IO_L7P_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AB11 | | |GND | | | | | | | | | | | |
|AB12 |ddr3_addr<13> |IOB18 |IO_L1N_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AB13 |ddr3_addr<5> |IOB18 |IO_L6N_T0_VREF_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AB14 | |IOB18 |IO_25_VRP_32 |UNUSED | |32 | | | | | | | | |
|AB15 | |IOB18S |IO_L20N_T3_32 |UNUSED | |32 | | | | | | | | |
|AB16 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AB17 | |IOB18M |IO_L18P_T2_32 |UNUSED | |32 | | | | | | | | |
|AB18 | |IOB18S |IO_L16N_T2_32 |UNUSED | |32 | | | | | | | | |
|AB19 | |IOB18M |IO_L17P_T2_32 |UNUSED | |32 | | | | | | | | |
|AB20 | |IOB33S |IO_L6N_T0_VREF_12 |UNUSED | |12 | | | | | | | | |
|AB21 | | |GND | | | | | | | | | | | |
|AB22 | |IOB33M |IO_L3P_T0_DQS_12 |UNUSED | |12 | | | | | | | | |
|AB23 | |IOB33S |IO_L3N_T0_DQS_12 |UNUSED | |12 | | | | | | | | |
|AB24 | |IOB33M |IO_L7P_T1_12 |UNUSED | |12 | | | | | | | | |
|AB25 | |IOB33S |IO_L6N_T0_VREF_13 |UNUSED | |13 | | | | | | | | |
|AB26 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AB27 | |IOB33M |IO_L12P_T1_MRCC_13 |UNUSED | |13 | | | | | | | | |
|AB28 | |IOB33S |IO_L5N_T0_13 |UNUSED | |13 | | | | | | | | |
|AB29 | |IOB33M |IO_L10P_T1_13 |UNUSED | |13 | | | | | | | | |
|AB30 | |IOB33S |IO_L10N_T1_13 |UNUSED | |13 | | | | | | | | |
|AC1 |ddr3_dq<2> |IOB18 |IO_L2N_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AC2 |ddr3_dq<1> |IOB18 |IO_L2P_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AC3 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AC4 |ddr3_dq<4> |IOB18 |IO_L4N_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AC5 |ddr3_dq<3> |IOB18 |IO_L4P_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AC6 | |IOB18 |IO_0_VRN_34 |Termination Required| |34 | | |TERMINATION| | | | | |
|AC7 |ddr3_dq<7> |IOB18 |IO_L6P_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AC8 | | |GND | | | | | | | | | | | |
|AC9 |ddr3_ck_n<0> |IOB18S |IO_L3N_T0_DQS_33 |OUTPUT |DIFF_SSTL15 |33 | |FAST | | | |LOCATED |YES |NONE |
|AC10 |ddr3_addr<3> |IOB18 |IO_L7N_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AC11 |ddr3_ba<2> |IOB18 |IO_L9N_T1_DQS_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AC12 |ddr3_addr<0> |IOB18 |IO_L9P_T1_DQS_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AC13 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|AC14 | |IOB18M |IO_L22P_T3_32 |UNUSED | |32 | | | | | | | | |
|AC15 | |IOB18S |IO_L21N_T3_DQS_32 |UNUSED | |32 | | | | | | | | |
|AC16 | |IOB18M |IO_L21P_T3_DQS_32 |UNUSED | |32 | | | | | | | | |
|AC17 | |IOB18S |IO_L18N_T2_32 |UNUSED | |32 | | | | | | | | |
|AC18 | | |GND | | | | | | | | | | | |
|AC19 | |IOB18S |IO_L17N_T2_32 |UNUSED | |32 | | | | | | | | |
|AC20 | |IOB33M |IO_L5P_T0_12 |UNUSED | |12 | | | | | | | | |
|AC21 | |IOB33S |IO_L5N_T0_12 |UNUSED | |12 | | | | | | | | |
|AC22 | |IOB33M |IO_L8P_T1_12 |UNUSED | |12 | | | | | | | | |
|AC23 | | |VCCO_12 | | |12 | | | | |any******| | | |
|AC24 | |IOB33M |IO_L9P_T1_DQS_12 |UNUSED | |12 | | | | | | | | |
|AC25 | |IOB33S |IO_L7N_T1_12 |UNUSED | |12 | | | | | | | | |
|AC26 | |IOB33M |IO_L19P_T3_13 |UNUSED | |13 | | | | | | | | |
|AC27 | |IOB33S |IO_L12N_T1_MRCC_13 |UNUSED | |13 | | | | | | | | |
|AC28 | | |GND | | | | | | | | | | | |
|AC29 |sys_rst |IOB33 |IO_L7P_T1_13 |INPUT |LVCMOS33 |13 | | |PULLUP |NONE | |LOCATED |NO |NONE |
|AC30 | |IOB33S |IO_L7N_T1_13 |UNUSED | |13 | | | | | | | | |
|AD1 |ddr3_dqs_n<0> |IOB18S |IO_L3N_T0_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AD2 |ddr3_dqs_p<0> |IOB18M |IO_L3P_T0_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AD3 |ddr3_dq<0> |IOB18 |IO_L1N_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AD4 |ddr3_dm<0> |IOB18 |IO_L1P_T0_34 |TRISTATE |SSTL15 |34 | |FAST | | | |LOCATED |NO |NONE |
|AD5 | | |GND | | | | | | | | | | | |
|AD6 |ddr3_dq<5> |IOB18 |IO_L5P_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AD7 | |IOB18S |IO_L6N_T0_VREF_34 |VREF Required | |34 | | | | |0.75 | | | |
|AD8 |ddr3_addr<2> |IOB18 |IO_L8P_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AD9 |ddr3_ba<1> |IOB18 |IO_L10P_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AD10 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|AD11 |ddr3_cs_n<0> |IOB18 |IO_L12N_T1_MRCC_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AD12 |ddr3_we_n |IOB18 |IO_L12P_T1_MRCC_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AD13 | |IOB18 |IO_25_VRP_33 |UNUSED | |33 | | | | | | | | |
|AD14 | |IOB18S |IO_L22N_T3_32 |UNUSED | |32 | | | | | | | | |
|AD15 | | |GND | | | | | | | | | | | |
|AD16 | |IOB18S |IO_L14N_T2_SRCC_32 |UNUSED | |32 | | | | | | | | |
|AD17 | |IOB18M |IO_L14P_T2_SRCC_32 |UNUSED | |32 | | | | | | | | |
|AD18 | |IOB18M |IO_L13P_T2_MRCC_32 |UNUSED | |32 | | | | | | | | |
|AD19 | |IOB18M |IO_L10P_T1_32 |UNUSED | |32 | | | | | | | | |
|AD20 | | |VCCO_12 | | |12 | | | | |any******| | | |
|AD21 | |IOB33M |IO_L10P_T1_12 |UNUSED | |12 | | | | | | | | |
|AD22 | |IOB33S |IO_L8N_T1_12 |UNUSED | |12 | | | | | | | | |
|AD23 | |IOB33M |IO_L12P_T1_MRCC_12 |UNUSED | |12 | | | | | | | | |
|AD24 | |IOB33S |IO_L9N_T1_DQS_12 |UNUSED | |12 | | | | | | | | |
|AD25 | | |GND | | | | | | | | | | | |
|AD26 | |IOB33S |IO_L19N_T3_VREF_13 |UNUSED | |13 | | | | | | | | |
|AD27 | |IOB33M |IO_L11P_T1_SRCC_13 |UNUSED | |13 | | | | | | | | |
|AD28 | |IOB33S |IO_L11N_T1_SRCC_13 |UNUSED | |13 | | | | | | | | |
|AD29 | |IOB33M |IO_L9P_T1_DQS_13 |UNUSED | |13 | | | | | | | | |
|AD30 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AE1 |ddr3_dq<9> |IOB18 |IO_L8P_T1_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AE2 | | |GND | | | | | | | | | | | |
|AE3 |ddr3_dq<12> |IOB18 |IO_L10N_T1_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AE4 |ddr3_dq<11> |IOB18 |IO_L10P_T1_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AE5 |ddr3_dq<13> |IOB18 |IO_L11P_T1_SRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AE6 |ddr3_dq<6> |IOB18 |IO_L5N_T0_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AE7 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AE8 |ddr3_addr<1> |IOB18 |IO_L8N_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AE9 |ddr3_ba<0> |IOB18 |IO_L10N_T1_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AE10 |sys_clk_i |IOB18 |IO_L14P_T2_SRCC_33 |INPUT |LVCMOS15 |33 | | | |NONE | |LOCATED |NO |NONE |
|AE11 |ddr3_ras_n |IOB18 |IO_L11P_T1_SRCC_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AE12 | | |GND | | | | | | | | | | | |
|AE13 | |IOB18M |IO_L19P_T3_33 |UNUSED | |33 | | | | | | | | |
|AE14 | |IOB18S |IO_L19N_T3_VREF_32 |UNUSED | |32 | | | | | | | | |
|AE15 | |IOB18M |IO_L19P_T3_32 |UNUSED | |32 | | | | | | | | |
|AE16 | |IOB18M |IO_L6P_T0_32 |UNUSED | |32 | | | | | | | | |
|AE17 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AE18 | |IOB18S |IO_L13N_T2_MRCC_32 |UNUSED | |32 | | | | | | | | |
|AE19 | |IOB18S |IO_L10N_T1_32 |UNUSED | |32 | | | | | | | | |
|AE20 | |IOB33 |IO_25_12 |UNUSED | |12 | | | | | | | | |
|AE21 | |IOB33S |IO_L10N_T1_12 |UNUSED | |12 | | | | | | | | |
|AE22 | | |GND | | | | | | | | | | | |
|AE23 | |IOB33M |IO_L11P_T1_SRCC_12 |UNUSED | |12 | | | | | | | | |
|AE24 | |IOB33S |IO_L12N_T1_MRCC_12 |UNUSED | |12 | | | | | | | | |
|AE25 | |IOB33M |IO_L16P_T2_12 |UNUSED | |12 | | | | | | | | |
|AE26 | |IOB33 |IO_25_13 |UNUSED | |13 | | | | | | | | |
|AE27 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AE28 | |IOB33M |IO_L14P_T2_SRCC_13 |UNUSED | |13 | | | | | | | | |
|AE29 | |IOB33S |IO_L9N_T1_DQS_13 |UNUSED | |13 | | | | | | | | |
|AE30 | |IOB33M |IO_L16P_T2_13 |UNUSED | |13 | | | | | | | | |
|AF1 |ddr3_dq<10> |IOB18 |IO_L8N_T1_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AF2 |ddr3_dq<8> |IOB18 |IO_L7N_T1_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AF3 |ddr3_dm<1> |IOB18 |IO_L7P_T1_34 |TRISTATE |SSTL15 |34 | |FAST | | | |LOCATED |NO |NONE |
|AF4 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AF5 |ddr3_dq<14> |IOB18 |IO_L11N_T1_SRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AF6 |ddr3_dq<15> |IOB18 |IO_L12P_T1_MRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AF7 |ddr3_dq<24> |IOB18 |IO_L20P_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AF8 |ddr3_dm<3> |IOB18 |IO_L19P_T3_34 |TRISTATE |SSTL15 |34 | |FAST | | | |LOCATED |NO |NONE |
|AF9 | | |GND | | | | | | | | | | | |
|AF10 | |IOB18S |IO_L14N_T2_SRCC_33 |UNUSED | |33 | | | | | | | | |
|AF11 |ddr3_cas_n |IOB18 |IO_L11N_T1_SRCC_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AF12 | |IOB18M |IO_L23P_T3_33 |UNUSED | |33 | | | | | | | | |
|AF13 | |IOB18S |IO_L19N_T3_VREF_33 |UNUSED | |33 | | | | | | | | |
|AF14 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AF15 | |IOB18M |IO_L4P_T0_32 |UNUSED | |32 | | | | | | | | |
|AF16 | |IOB18S |IO_L6N_T0_VREF_32 |UNUSED | |32 | | | | | | | | |
|AF17 | |IOB18M |IO_L12P_T1_MRCC_32 |UNUSED | |32 | | | | | | | | |
|AF18 | |IOB18M |IO_L11P_T1_SRCC_32 |UNUSED | |32 | | | | | | | | |
|AF19 | | |GND | | | | | | | | | | | |
|AF20 | |IOB33M |IO_L19P_T3_12 |UNUSED | |12 | | | | | | | | |
|AF21 | |IOB33S |IO_L19N_T3_VREF_12 |UNUSED | |12 | | | | | | | | |
|AF22 | |IOB33M |IO_L13P_T2_MRCC_12 |UNUSED | |12 | | | | | | | | |
|AF23 | |IOB33S |IO_L11N_T1_SRCC_12 |UNUSED | |12 | | | | | | | | |
|AF24 | | |VCCO_12 | | |12 | | | | |any******| | | |
|AF25 | |IOB33S |IO_L16N_T2_12 |UNUSED | |12 | | | | | | | | |
|AF26 | |IOB33M |IO_L23P_T3_13 |UNUSED | |13 | | | | | | | | |
|AF27 | |IOB33S |IO_L23N_T3_13 |UNUSED | |13 | | | | | | | | |
|AF28 | |IOB33S |IO_L14N_T2_SRCC_13 |UNUSED | |13 | | | | | | | | |
|AF29 | | |GND | | | | | | | | | | | |
|AF30 | |IOB33S |IO_L16N_T2_13 |UNUSED | |13 | | | | | | | | |
|AG1 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AG2 |ddr3_dqs_p<2> |IOB18M |IO_L15P_T2_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AG3 |ddr3_dqs_n<1> |IOB18S |IO_L9N_T1_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AG4 |ddr3_dqs_p<1> |IOB18M |IO_L9P_T1_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AG5 |ddr3_reset_n |IOB18 |IO_L12N_T1_MRCC_34 |OUTPUT |LVCMOS15 |34 |12 |FAST | | | |LOCATED |NO |NONE |
|AG6 | | |GND | | | | | | | | | | | |
|AG7 |ddr3_dq<25> |IOB18 |IO_L20N_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AG8 | |IOB18S |IO_L19N_T3_VREF_34 |VREF Required | |34 | | | | |0.75 | | | |
|AG9 | |IOB18M |IO_L16P_T2_33 |UNUSED | |33 | | | | | | | | |
|AG10 | |IOB18M |IO_L13P_T2_MRCC_33 |UNUSED | |33 | | | | | | | | |
|AG11 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|AG12 | |IOB18S |IO_L23N_T3_33 |UNUSED | |33 | | | | | | | | |
|AG13 | |IOB18M |IO_L24P_T3_33 |UNUSED | |33 | | | | | | | | |
|AG14 | |IOB18S |IO_L4N_T0_32 |UNUSED | |32 | | | | | | | | |
|AG15 | |IOB18M |IO_L2P_T0_32 |UNUSED | |32 | | | | | | | | |
|AG16 | | |GND | | | | | | | | | | | |
|AG17 | |IOB18S |IO_L12N_T1_MRCC_32 |UNUSED | |32 | | | | | | | | |
|AG18 | |IOB18S |IO_L11N_T1_SRCC_32 |UNUSED | |32 | | | | | | | | |
|AG19 | |IOB18M |IO_L8P_T1_32 |UNUSED | |32 | | | | | | | | |
|AG20 | |IOB33M |IO_L22P_T3_12 |UNUSED | |12 | | | | | | | | |
|AG21 | | |VCCO_12 | | |12 | | | | |any******| | | |
|AG22 | |IOB33M |IO_L20P_T3_12 |UNUSED | |12 | | | | | | | | |
|AG23 | |IOB33S |IO_L13N_T2_MRCC_12 |UNUSED | |12 | | | | | | | | |
|AG24 | |IOB33M |IO_L14P_T2_SRCC_12 |UNUSED | |12 | | | | | | | | |
|AG25 | |IOB33M |IO_L18P_T2_12 |UNUSED | |12 | | | | | | | | |
|AG26 | | |GND | | | | | | | | | | | |
|AG27 | |IOB33M |IO_L21P_T3_DQS_13 |UNUSED | |13 | | | | | | | | |
|AG28 | |IOB33S |IO_L21N_T3_DQS_13 |UNUSED | |13 | | | | | | | | |
|AG29 | |IOB33M |IO_L13P_T2_MRCC_13 |UNUSED | |13 | | | | | | | | |
|AG30 | |IOB33M |IO_L18P_T2_13 |UNUSED | |13 | | | | | | | | |
|AH1 |ddr3_dqs_n<2> |IOB18S |IO_L15N_T2_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AH2 |ddr3_dq<19> |IOB18 |IO_L16P_T2_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AH3 | | |GND | | | | | | | | | | | |
|AH4 |ddr3_dm<2> |IOB18 |IO_L13P_T2_MRCC_34 |TRISTATE |SSTL15 |34 | |FAST | | | |LOCATED |NO |NONE |
|AH5 |ddr3_dq<18> |IOB18 |IO_L14N_T2_SRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AH6 |ddr3_dq<17> |IOB18 |IO_L14P_T2_SRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AH7 |ddr3_dqs_p<3> |IOB18M |IO_L21P_T3_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AH8 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AH9 | |IOB18S |IO_L16N_T2_33 |UNUSED | |33 | | | | | | | | |
|AH10 | |IOB18S |IO_L13N_T2_MRCC_33 |UNUSED | |33 | | | | | | | | |
|AH11 | |IOB18M |IO_L18P_T2_33 |UNUSED | |33 | | | | | | | | |
|AH12 | |IOB18S |IO_L24N_T3_33 |UNUSED | |33 | | | | | | | | |
|AH13 | | |GND | | | | | | | | | | | |
|AH14 | |IOB18M |IO_L21P_T3_DQS_33 |UNUSED | |33 | | | | | | | | |
|AH15 | |IOB18S |IO_L2N_T0_32 |UNUSED | |32 | | | | | | | | |
|AH16 | |IOB18M |IO_L3P_T0_DQS_32 |UNUSED | |32 | | | | | | | | |
|AH17 | |IOB18M |IO_L5P_T0_32 |UNUSED | |32 | | | | | | | | |
|AH18 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AH19 | |IOB18S |IO_L8N_T1_32 |UNUSED | |32 | | | | | | | | |
|AH20 | |IOB33S |IO_L22N_T3_12 |UNUSED | |12 | | | | | | | | |
|AH21 | |IOB33M |IO_L23P_T3_12 |UNUSED | |12 | | | | | | | | |
|AH22 | |IOB33S |IO_L20N_T3_12 |UNUSED | |12 | | | | | | | | |
|AH23 | | |GND | | | | | | | | | | | |
|AH24 | |IOB33S |IO_L14N_T2_SRCC_12 |UNUSED | |12 | | | | | | | | |
|AH25 | |IOB33S |IO_L18N_T2_12 |UNUSED | |12 | | | | | | | | |
|AH26 | |IOB33M |IO_L22P_T3_13 |UNUSED | |13 | | | | | | | | |
|AH27 | |IOB33S |IO_L22N_T3_13 |UNUSED | |13 | | | | | | | | |
|AH28 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AH29 | |IOB33S |IO_L13N_T2_MRCC_13 |UNUSED | |13 | | | | | | | | |
|AH30 | |IOB33S |IO_L18N_T2_13 |UNUSED | |13 | | | | | | | | |
|AJ1 |ddr3_dq<21> |IOB18 |IO_L17P_T2_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ2 |ddr3_dq<20> |IOB18 |IO_L16N_T2_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ3 |ddr3_dq<23> |IOB18 |IO_L18P_T2_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ4 |ddr3_dq<16> |IOB18 |IO_L13N_T2_MRCC_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ5 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AJ6 |ddr3_dq<26> |IOB18 |IO_L22P_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ7 |ddr3_dqs_n<3> |IOB18S |IO_L21N_T3_DQS_34 |BIDIR |DIFF_SSTL15_T_DCI|34 | |FAST | |NONE | |LOCATED |YES |SPLIT |
|AJ8 |ddr3_dq<28> |IOB18 |IO_L23P_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AJ9 |ddr3_cke<0> |IOB18 |IO_L15P_T2_DQS_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AJ10 | | |GND | | | | | | | | | | | |
|AJ11 | |IOB18S |IO_L18N_T2_33 |UNUSED | |33 | | | | | | | | |
|AJ12 | |IOB18S |IO_L22N_T3_33 |UNUSED | |33 | | | | | | | | |
|AJ13 | |IOB18M |IO_L22P_T3_33 |UNUSED | |33 | | | | | | | | |
|AJ14 | |IOB18S |IO_L21N_T3_DQS_33 |UNUSED | |33 | | | | | | | | |
|AJ15 | | |VCCO_32 | | |32 | | | | |any******| | | |
|AJ16 | |IOB18S |IO_L3N_T0_DQS_32 |UNUSED | |32 | | | | | | | | |
|AJ17 | |IOB18S |IO_L5N_T0_32 |UNUSED | |32 | | | | | | | | |
|AJ18 | |IOB18M |IO_L9P_T1_DQS_32 |UNUSED | |32 | | | | | | | | |
|AJ19 | |IOB18M |IO_L7P_T1_32 |UNUSED | |32 | | | | | | | | |
|AJ20 | | |GND | | | | | | | | | | | |
|AJ21 | |IOB33S |IO_L23N_T3_12 |UNUSED | |12 | | | | | | | | |
|AJ22 | |IOB33M |IO_L21P_T3_DQS_12 |UNUSED | |12 | | | | | | | | |
|AJ23 | |IOB33S |IO_L21N_T3_DQS_12 |UNUSED | |12 | | | | | | | | |
|AJ24 | |IOB33M |IO_L15P_T2_DQS_12 |UNUSED | |12 | | | | | | | | |
|AJ25 | | |VCCO_13 | | |13 | | | | |3.30 | | | |
|AJ26 | |IOB33M |IO_L24P_T3_13 |UNUSED | |13 | | | | | | | | |
|AJ27 | |IOB33M |IO_L20P_T3_13 |UNUSED | |13 | | | | | | | | |
|AJ28 | |IOB33M |IO_L17P_T2_13 |UNUSED | |13 | | | | | | | | |
|AJ29 | |IOB33S |IO_L17N_T2_13 |UNUSED | |13 | | | | | | | | |
|AJ30 | | |GND | | | | | | | | | | | |
|AK1 |ddr3_dq<22> |IOB18 |IO_L17N_T2_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AK2 | | |VCCO_34 | | |34 | | | | |1.50 | | | |
|AK3 | |IOB18S |IO_L18N_T2_34 |UNUSED | |34 | | | | | | | | |
|AK4 |ddr3_dq<31> |IOB18 |IO_L24N_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AK5 |ddr3_dq<30> |IOB18 |IO_L24P_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AK6 |ddr3_dq<27> |IOB18 |IO_L22N_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AK7 | | |GND | | | | | | | | | | | |
|AK8 |ddr3_dq<29> |IOB18 |IO_L23N_T3_34 |BIDIR |SSTL15_T_DCI |34 | |FAST | |NONE | |LOCATED |NO |SPLIT |
|AK9 |ddr3_odt<0> |IOB18 |IO_L15N_T2_DQS_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|AK10 | |IOB18S |IO_L17N_T2_33 |UNUSED | |33 | | | | | | | | |
|AK11 | |IOB18M |IO_L17P_T2_33 |UNUSED | |33 | | | | | | | | |
|AK12 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|AK13 | |IOB18S |IO_L20N_T3_33 |UNUSED | |33 | | | | | | | | |
|AK14 | |IOB18M |IO_L20P_T3_33 |UNUSED | |33 | | | | | | | | |
|AK15 | |IOB18S |IO_L1N_T0_32 |UNUSED | |32 | | | | | | | | |
|AK16 | |IOB18M |IO_L1P_T0_32 |UNUSED | |32 | | | | | | | | |
|AK17 | | |GND | | | | | | | | | | | |
|AK18 | |IOB18S |IO_L9N_T1_DQS_32 |UNUSED | |32 | | | | | | | | |
|AK19 | |IOB18S |IO_L7N_T1_32 |UNUSED | |32 | | | | | | | | |
|AK20 | |IOB33M |IO_L24P_T3_12 |UNUSED | |12 | | | | | | | | |
|AK21 | |IOB33S |IO_L24N_T3_12 |UNUSED | |12 | | | | | | | | |
|AK22 | | |VCCO_12 | | |12 | | | | |any******| | | |
|AK23 | |IOB33M |IO_L17P_T2_12 |UNUSED | |12 | | | | | | | | |
|AK24 | |IOB33S |IO_L17N_T2_12 |UNUSED | |12 | | | | | | | | |
|AK25 | |IOB33S |IO_L15N_T2_DQS_12 |UNUSED | |12 | | | | | | | | |
|AK26 | |IOB33S |IO_L24N_T3_13 |UNUSED | |13 | | | | | | | | |
|AK27 | | |GND | | | | | | | | | | | |
|AK28 | |IOB33S |IO_L20N_T3_13 |UNUSED | |13 | | | | | | | | |
|AK29 | |IOB33M |IO_L15P_T2_DQS_13 |UNUSED | |13 | | | | | | | | |
|AK30 | |IOB33S |IO_L15N_T2_DQS_13 |UNUSED | |13 | | | | | | | | |
|B1 | |OPAD |MGTXTXN2_118 |UNUSED | | | | | | | | | | |
|B2 | |OPAD |MGTXTXP2_118 |UNUSED | | | | | | | | | | |
|B3 | | |MGTAVTT | | | | | | | | | | | |
|B4 | | |GND | | | | | | | | | | | |
|B5 | |IPAD |MGTXRXN2_118 |UNUSED | | | | | | | | | | |
|B6 | |IPAD |MGTXRXP2_118 |UNUSED | | | | | | | | | | |
|B7 | | |MGTAVCC | | | | | | | | | | | |
|B8 | | |GND | | | | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | |
|B10 | | |CCLK_0 | | | | | | | | | | | |
|B11 | | |GND | | | | | | | | | | | |
|B12 | |IOB33S |IO_L15N_T2_DQS_18 |UNUSED | |18 | | | | | | | | |
|B13 | |IOB33M |IO_L22P_T3_18 |UNUSED | |18 | | | | | | | | |
|B14 | |IOB33M |IO_L24P_T3_18 |UNUSED | |18 | | | | | | | | |
|B15 | |IOB33S |IO_L23N_T3_18 |UNUSED | |18 | | | | | | | | |
|B16 | | |VCCO_17 | | |17 | | | | |any******| | | |
|B17 | |IOB33S |IO_L17N_T2_17 |UNUSED | |17 | | | | | | | | |
|B18 | |IOB33M |IO_L22P_T3_17 |UNUSED | |17 | | | | | | | | |
|B19 | |IOB33S |IO_L24N_T3_17 |UNUSED | |17 | | | | | | | | |
|B20 | |IOB33S |IO_L19N_T3_VREF_17 |UNUSED | |17 | | | | | | | | |
|B21 | | |GND | | | | | | | | | | | |
|B22 | |IOB33M |IO_L23P_T3_17 |UNUSED | |17 | | | | | | | | |
|B23 | |IOB33M |IO_L1P_T0_16 |UNUSED | |16 | | | | | | | | |
|B24 | |IOB33S |IO_L8N_T1_16 |UNUSED | |16 | | | | | | | | |
|B25 | |IOB33S |IO_L12N_T1_MRCC_16 |UNUSED | |16 | | | | | | | | |
|B26 | | |VCCO_16 | | |16 | | | | |any******| | | |
|B27 | |IOB33M |IO_L7P_T1_16 |UNUSED | |16 | | | | | | | | |
|B28 | |IOB33M |IO_L9P_T1_DQS_16 |UNUSED | |16 | | | | | | | | |
|B29 | |IOB33S |IO_L15N_T2_DQS_16 |UNUSED | |16 | | | | | | | | |
|B30 | |IOB33M |IO_L17P_T2_16 |UNUSED | |16 | | | | | | | | |
|C1 | | |GND | | | | | | | | | | | |
|C2 | | |GND | | | | | | | | | | | |
|C3 | |OPAD |MGTXTXN1_118 |UNUSED | | | | | | | | | | |
|C4 | |OPAD |MGTXTXP1_118 |UNUSED | | | | | | | | | | |
|C5 | | |MGTAVTT | | | | | | | | | | | |
|C6 | | |GND | | | | | | | | | | | |
|C7 | |IPAD |MGTREFCLK0N_118 |UNUSED | | | | | | | | | | |
|C8 | |IPAD |MGTREFCLK0P_118 |UNUSED | | | | | | | | | | |
|C9 | | |GND | | | | | | | | | | | |
|C10 | | |VCCBATT_0 | | | | | | | | | | | |
|C11 | |IOB33S |IO_L18N_T2_18 |UNUSED | |18 | | | | | | | | |
|C12 | |IOB33M |IO_L15P_T2_DQS_18 |UNUSED | |18 | | | | | | | | |
|C13 | | |VCCO_18 | | |18 | | | | |any******| | | |
|C14 | |IOB33S |IO_L21N_T3_DQS_18 |UNUSED | |18 | | | | | | | | |
|C15 | |IOB33M |IO_L23P_T3_18 |UNUSED | |18 | | | | | | | | |
|C16 | |IOB33S |IO_L15N_T2_DQS_17 |UNUSED | |17 | | | | | | | | |
|C17 | |IOB33M |IO_L17P_T2_17 |UNUSED | |17 | | | | | | | | |
|C18 | | |GND | | | | | | | | | | | |
|C19 | |IOB33M |IO_L24P_T3_17 |UNUSED | |17 | | | | | | | | |
|C20 | |IOB33M |IO_L19P_T3_17 |UNUSED | |17 | | | | | | | | |
|C21 | |IOB33S |IO_L8N_T1_17 |UNUSED | |17 | | | | | | | | |
|C22 | |IOB33S |IO_L10N_T1_17 |UNUSED | |17 | | | | | | | | |
|C23 | | |VCCO_16 | | |16 | | | | |any******| | | |
|C24 | |IOB33M |IO_L8P_T1_16 |UNUSED | |16 | | | | | | | | |
|C25 | |IOB33M |IO_L12P_T1_MRCC_16 |UNUSED | |16 | | | | | | | | |
|C26 | |IOB33S |IO_L11N_T1_SRCC_16 |UNUSED | |16 | | | | | | | | |
|C27 | |IOB33S |IO_L13N_T2_MRCC_16 |UNUSED | |16 | | | | | | | | |
|C28 | | |GND | | | | | | | | | | | |
|C29 | |IOB33M |IO_L15P_T2_DQS_16 |UNUSED | |16 | | | | | | | | |
|C30 | |IOB33S |IO_L16N_T2_16 |UNUSED | |16 | | | | | | | | |
|D1 | |OPAD |MGTXTXN0_118 |UNUSED | | | | | | | | | | |
|D2 | |OPAD |MGTXTXP0_118 |UNUSED | | | | | | | | | | |
|D3 | | |MGTAVTT | | | | | | | | | | | |
|D4 | | |GND | | | | | | | | | | | |
|D5 | |IPAD |MGTXRXN1_118 |UNUSED | | | | | | | | | | |
|D6 | |IPAD |MGTXRXP1_118 |UNUSED | | | | | | | | | | |
|D7 | | |MGTAVCC | | | | | | | | | | | |
|D8 | | |GND | | | | | | | | | | | |
|D9 | | |GND | | | | | | | | | | | |
|D10 | | |VCCO_18 | | |18 | | | | |any******| | | |
|D11 | |IOB33M |IO_L18P_T2_18 |UNUSED | |18 | | | | | | | | |
|D12 | |IOB33M |IO_L13P_T2_MRCC_18 |UNUSED | |18 | | | | | | | | |
|D13 | |IOB33S |IO_L13N_T2_MRCC_18 |UNUSED | |18 | | | | | | | | |
|D14 | |IOB33M |IO_L21P_T3_DQS_18 |UNUSED | |18 | | | | | | | | |
|D15 | | |GND | | | | | | | | | | | |
|D16 | |IOB33M |IO_L15P_T2_DQS_17 |UNUSED | |17 | | | | | | | | |
|D17 | |IOB33M |IO_L13P_T2_MRCC_17 |UNUSED | |17 | | | | | | | | |
|D18 | |IOB33S |IO_L13N_T2_MRCC_17 |UNUSED | |17 | | | | | | | | |
|D19 | |IOB33S |IO_L14N_T2_SRCC_17 |UNUSED | |17 | | | | | | | | |
|D20 | | |VCCO_17 | | |17 | | | | |any******| | | |
|D21 | |IOB33M |IO_L8P_T1_17 |UNUSED | |17 | | | | | | | | |
|D22 | |IOB33M |IO_L10P_T1_17 |UNUSED | |17 | | | | | | | | |
|D23 | |IOB33S |IO_L2N_T0_16 |UNUSED | |16 | | | | | | | | |
|D24 | |IOB33S |IO_L4N_T0_16 |UNUSED | |16 | | | | | | | | |
|D25 | | |GND | | | | | | | | | | | |
|D26 | |IOB33M |IO_L11P_T1_SRCC_16 |UNUSED | |16 | | | | | | | | |
|D27 | |IOB33M |IO_L13P_T2_MRCC_16 |UNUSED | |16 | | | | | | | | |
|D28 | |IOB33S |IO_L14N_T2_SRCC_16 |UNUSED | |16 | | | | | | | | |
|D29 | |IOB33M |IO_L16P_T2_16 |UNUSED | |16 | | | | | | | | |
|D30 | | |VCCO_16 | | |16 | | | | |any******| | | |
|E1 | | |GND | | | | | | | | | | | |
|E2 | | |GND | | | | | | | | | | | |
|E3 | |IPAD |MGTXRXN0_118 |UNUSED | | | | | | | | | | |
|E4 | |IPAD |MGTXRXP0_118 |UNUSED | | | | | | | | | | |
|E5 | | |MGTAVTT | | | | | | | | | | | |
|E6 | | |GND | | | | | | | | | | | |
|E7 | |IPAD |MGTREFCLK1N_118 |UNUSED | | | | | | | | | | |
|E8 | |IPAD |MGTREFCLK1P_118 |UNUSED | | | | | | | | | | |
|E9 | | |GND | | | | | | | | | | | |
|E10 | | |TCK_0 | | | | | | | | | | | |
|E11 | |IOB33S |IO_L16N_T2_18 |UNUSED | |18 | | | | | | | | |
|E12 | | |GND | | | | | | | | | | | |
|E13 | |IOB33S |IO_L14N_T2_SRCC_18 |UNUSED | |18 | | | | | | | | |
|E14 | |IOB33M |IO_L20P_T3_18 |UNUSED | |18 | | | | | | | | |
|E15 | |IOB33S |IO_L20N_T3_18 |UNUSED | |18 | | | | | | | | |
|E16 | |IOB33S |IO_L19N_T3_VREF_18 |UNUSED | |18 | | | | | | | | |
|E17 | | |VCCO_17 | | |17 | | | | |any******| | | |
|E18 | |IOB33 |IO_25_17 |UNUSED | |17 | | | | | | | | |
|E19 | |IOB33M |IO_L14P_T2_SRCC_17 |UNUSED | |17 | | | | | | | | |
|E20 | |IOB33S |IO_L12N_T1_MRCC_17 |UNUSED | |17 | | | | | | | | |
|E21 | |IOB33S |IO_L11N_T1_SRCC_17 |UNUSED | |17 | | | | | | | | |
|E22 | | |GND | | | | | | | | | | | |
|E23 | |IOB33M |IO_L2P_T0_16 |UNUSED | |16 | | | | | | | | |
|E24 | |IOB33M |IO_L4P_T0_16 |UNUSED | |16 | | | | | | | | |
|E25 | |IOB33S |IO_L3N_T0_DQS_16 |UNUSED | |16 | | | | | | | | |
|E26 | |IOB33S |IO_L5N_T0_16 |UNUSED | |16 | | | | | | | | |
|E27 | | |VCCO_16 | | |16 | | | | |any******| | | |
|E28 | |IOB33M |IO_L14P_T2_SRCC_16 |UNUSED | |16 | | | | | | | | |
|E29 | |IOB33M |IO_L18P_T2_16 |UNUSED | |16 | | | | | | | | |
|E30 | |IOB33S |IO_L18N_T2_16 |UNUSED | |16 | | | | | | | | |
|F1 | |OPAD |MGTXTXN3_117 |UNUSED | | | | | | | | | | |
|F2 | |OPAD |MGTXTXP3_117 |UNUSED | | | | | | | | | | |
|F3 | | |MGTAVTT | | | | | | | | | | | |
|F4 | | |GND | | | | | | | | | | | |
|F5 | |IPAD |MGTXRXN3_117 |UNUSED | | | | | | | | | | |
|F6 | |IPAD |MGTXRXP3_117 |UNUSED | | | | | | | | | | |
|F7 | | |MGTAVCC | | | | | | | | | | | |
|F8 | | |GND | | | | | | | | | | | |
|F9 | | |GND | | | | | | | | | | | |
|F10 | | |TMS_0 | | | | | | | | | | | |
|F11 | |IOB33M |IO_L16P_T2_18 |UNUSED | |18 | | | | | | | | |
|F12 | |IOB33M |IO_L14P_T2_SRCC_18 |UNUSED | |18 | | | | | | | | |
|F13 | |IOB33S |IO_L12N_T1_MRCC_18 |UNUSED | |18 | | | | | | | | |
|F14 | | |VCCO_18 | | |18 | | | | |any******| | | |
|F15 | |IOB33M |IO_L19P_T3_18 |UNUSED | |18 | | | | | | | | |
|F16 | |IOB33 |IO_25_18 |UNUSED | |18 | | | | | | | | |
|F17 | |IOB33S |IO_L18N_T2_17 |UNUSED | |17 | | | | | | | | |
|F18 | |IOB33S |IO_L16N_T2_17 |UNUSED | |17 | | | | | | | | |
|F19 | | |GND | | | | | | | | | | | |
|F20 | |IOB33M |IO_L12P_T1_MRCC_17 |UNUSED | |17 | | | | | | | | |
|F21 | |IOB33M |IO_L11P_T1_SRCC_17 |UNUSED | |17 | | | | | | | | |
|F22 | |IOB33S |IO_L9N_T1_DQS_17 |UNUSED | |17 | | | | | | | | |
|F23 | |IOB33 |IO_0_16 |UNUSED | |16 | | | | | | | | |
|F24 | | |VCCO_16 | | |16 | | | | |any******| | | |
|F25 | |IOB33M |IO_L3P_T0_DQS_16 |UNUSED | |16 | | | | | | | | |
|F26 | |IOB33M |IO_L5P_T0_16 |UNUSED | |16 | | | | | | | | |
|F27 | |IOB33S |IO_L21N_T3_DQS_16 |UNUSED | |16 | | | | | | | | |
|F28 | |IOB33S |IO_L20N_T3_16 |UNUSED | |16 | | | | | | | | |
|F29 | | |GND | | | | | | | | | | | |
|F30 | |IOB33S |IO_L22N_T3_16 |UNUSED | |16 | | | | | | | | |
|G1 | | |GND | | | | | | | | | | | |
|G2 | | |GND | | | | | | | | | | | |
|G3 | |IPAD |MGTXRXN2_117 |UNUSED | | | | | | | | | | |
|G4 | |IPAD |MGTXRXP2_117 |UNUSED | | | | | | | | | | |
|G5 | | |MGTAVTT | | | | | | | | | | | |
|G6 | | |GND | | | | | | | | | | | |
|G7 | |IPAD |MGTREFCLK0N_117 |UNUSED | | | | | | | | | | |
|G8 | |IPAD |MGTREFCLK0P_117 |UNUSED | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |TDO_0 | | | | | | | | | | | |
|G11 | | |VCCO_18 | | |18 | | | | |any******| | | |
|G12 | |IOB33 |IO_0_18 |UNUSED | |18 | | | | | | | | |
|G13 | |IOB33M |IO_L12P_T1_MRCC_18 |UNUSED | |18 | | | | | | | | |
|G14 | |IOB33S |IO_L11N_T1_SRCC_18 |UNUSED | |18 | | | | | | | | |
|G15 | |IOB33S |IO_L7N_T1_18 |UNUSED | |18 | | | | | | | | |
|G16 | | |GND | | | | | | | | | | | |
|G17 | |IOB33M |IO_L18P_T2_17 |UNUSED | |17 | | | | | | | | |
|G18 | |IOB33M |IO_L16P_T2_17 |UNUSED | |17 | | | | | | | | |
|G19 | |IOB33 |IO_0_17 |UNUSED | |17 | | | | | | | | |
|G20 | |IOB33S |IO_L2N_T0_17 |UNUSED | |17 | | | | | | | | |
|G21 | | |VCCO_17 | | |17 | | | | |any******| | | |
|G22 | |IOB33M |IO_L9P_T1_DQS_17 |UNUSED | |17 | | | | | | | | |
|G23 | |IOB33M |IO_L6P_T0_16 |UNUSED | |16 | | | | | | | | |
|G24 | |IOB33S |IO_L6N_T0_VREF_16 |UNUSED | |16 | | | | | | | | |
|G25 | |IOB33 |IO_25_16 |UNUSED | |16 | | | | | | | | |
|G26 | | |GND | | | | | | | | | | | |
|G27 | |IOB33M |IO_L21P_T3_DQS_16 |UNUSED | |16 | | | | | | | | |
|G28 | |IOB33M |IO_L20P_T3_16 |UNUSED | |16 | | | | | | | | |
|G29 | |IOB33M |IO_L22P_T3_16 |UNUSED | |16 | | | | | | | | |
|G30 | |IOB33S |IO_L24N_T3_16 |UNUSED | |16 | | | | | | | | |
|H1 | |OPAD |MGTXTXN2_117 |UNUSED | | | | | | | | | | |
|H2 | |OPAD |MGTXTXP2_117 |UNUSED | | | | | | | | | | |
|H3 | | |MGTAVTT | | | | | | | | | | | |
|H4 | | |GND | | | | | | | | | | | |
|H5 | |IPAD |MGTXRXN1_117 |UNUSED | | | | | | | | | | |
|H6 | |IPAD |MGTXRXP1_117 |UNUSED | | | | | | | | | | |
|H7 | | |MGTAVCC | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |TDI_0 | | | | | | | | | | | |
|H11 | |IOB33M |IO_L10P_T1_18 |UNUSED | |18 | | | | | | | | |
|H12 | |IOB33S |IO_L10N_T1_18 |UNUSED | |18 | | | | | | | | |
|H13 | | |GND | | | | | | | | | | | |
|H14 | |IOB33M |IO_L11P_T1_SRCC_18 |UNUSED | |18 | | | | | | | | |
|H15 | |IOB33M |IO_L7P_T1_18 |UNUSED | |18 | | | | | | | | |
|H16 | |IOB33S |IO_L9N_T1_DQS_18 |UNUSED | |18 | | | | | | | | |
|H17 | |IOB33S |IO_L3N_T0_DQS_17 |UNUSED | |17 | | | | | | | | |
|H18 | | |VCCO_17 | | |17 | | | | |any******| | | |
|H19 | |IOB33S |IO_L4N_T0_17 |UNUSED | |17 | | | | | | | | |
|H20 | |IOB33M |IO_L2P_T0_17 |UNUSED | |17 | | | | | | | | |
|H21 | |IOB33M |IO_L7P_T1_17 |UNUSED | |17 | | | | | | | | |
|H22 | |IOB33S |IO_L7N_T1_17 |UNUSED | |17 | | | | | | | | |
|H23 | | |GND | | | | | | | | | | | |
|H24 | |IOB33M |IO_L19P_T3_16 |UNUSED | |16 | | | | | | | | |
|H25 | |IOB33S |IO_L19N_T3_VREF_16 |UNUSED | |16 | | | | | | | | |
|H26 | |IOB33M |IO_L23P_T3_16 |UNUSED | |16 | | | | | | | | |
|H27 | |IOB33S |IO_L23N_T3_16 |UNUSED | |16 | | | | | | | | |
|H28 | | |VCCO_16 | | |16 | | | | |any******| | | |
|H29 | |IOB33S |IO_L7N_T1_AD10N_15 |UNUSED | |15 | | | | | | | | |
|H30 | |IOB33M |IO_L24P_T3_16 |UNUSED | |16 | | | | | | | | |
|J1 | | |GND | | | | | | | | | | | |
|J2 | | |GND | | | | | | | | | | | |
|J3 | |OPAD |MGTXTXN1_117 |UNUSED | | | | | | | | | | |
|J4 | |OPAD |MGTXTXP1_117 |UNUSED | | | | | | | | | | |
|J5 | | |MGTAVTT | | | | | | | | | | | |
|J6 | | |GND | | | | | | | | | | | |
|J7 | |IPAD |MGTREFCLK1N_117 |UNUSED | | | | | | | | | | |
|J8 | |IPAD |MGTREFCLK1P_117 |UNUSED | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | |
|J11 | |IOB33M |IO_L8P_T1_18 |UNUSED | |18 | | | | | | | | |
|J12 | |IOB33S |IO_L8N_T1_18 |UNUSED | |18 | | | | | | | | |
|J13 | |IOB33S |IO_L4N_T0_18 |UNUSED | |18 | | | | | | | | |
|J14 | |IOB33S |IO_L5N_T0_18 |UNUSED | |18 | | | | | | | | |
|J15 | | |VCCO_18 | | |18 | | | | |any******| | | |
|J16 | |IOB33M |IO_L9P_T1_DQS_18 |UNUSED | |18 | | | | | | | | |
|J17 | |IOB33M |IO_L3P_T0_DQS_17 |UNUSED | |17 | | | | | | | | |
|J18 | |IOB33S |IO_L1N_T0_17 |UNUSED | |17 | | | | | | | | |
|J19 | |IOB33M |IO_L4P_T0_17 |UNUSED | |17 | | | | | | | | |
|J20 | | |GND | | | | | | | | | | | |
|J21 | |IOB33M |IO_L5P_T0_AD2P_15 |UNUSED | |15 | | | | | | | | |
|J22 | |IOB33S |IO_L5N_T0_AD2N_15 |UNUSED | |15 | | | | | | | | |
|J23 | |IOB33M |IO_L1P_T0_AD0P_15 |UNUSED | |15 | | | | | | | | |
|J24 | |IOB33S |IO_L1N_T0_AD0N_15 |UNUSED | |15 | | | | | | | | |
|J25 | | |VCCO_15 | | |15 | | | | |any******| | | |
|J26 | |IOB33S |IO_L10N_T1_AD4N_15 |UNUSED | |15 | | | | | | | | |
|J27 | |IOB33M |IO_L8P_T1_AD3P_15 |UNUSED | |15 | | | | | | | | |
|J28 | |IOB33S |IO_L8N_T1_AD3N_15 |UNUSED | |15 | | | | | | | | |
|J29 | |IOB33M |IO_L7P_T1_AD10P_15 |UNUSED | |15 | | | | | | | | |
|J30 | | |GND | | | | | | | | | | | |
|K1 | |OPAD |MGTXTXN0_117 |UNUSED | | | | | | | | | | |
|K2 | |OPAD |MGTXTXP0_117 |UNUSED | | | | | | | | | | |
|K3 | | |MGTAVTT | | | | | | | | | | | |
|K4 | | |GND | | | | | | | | | | | |
|K5 | |IPAD |MGTXRXN0_117 |UNUSED | | | | | | | | | | |
|K6 | |IPAD |MGTXRXP0_117 |UNUSED | | | | | | | | | | |
|K7 | | |MGTAVCC | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | |
|K10 | | |PROGRAM_B_0 | | | | | | | | | | | |
|K11 | |IOB33S |IO_L6N_T0_VREF_18 |UNUSED | |18 | | | | | | | | |
|K12 | | |VCCO_18 | | |18 | | | | |any******| | | |
|K13 | |IOB33M |IO_L4P_T0_18 |UNUSED | |18 | | | | | | | | |
|K14 | |IOB33M |IO_L5P_T0_18 |UNUSED | |18 | | | | | | | | |
|K15 | |IOB33S |IO_L2N_T0_18 |UNUSED | |18 | | | | | | | | |
|K16 | |IOB33S |IO_L1N_T0_18 |UNUSED | |18 | | | | | | | | |
|K17 | | |GND | | | | | | | | | | | |
|K18 | |IOB33M |IO_L1P_T0_17 |UNUSED | |17 | | | | | | | | |
|K19 | |IOB33M |IO_L6P_T0_17 |UNUSED | |17 | | | | | | | | |
|K20 | |IOB33S |IO_L6N_T0_VREF_17 |UNUSED | |17 | | | | | | | | |
|K21 | |IOB33S |IO_L4N_T0_AD9N_15 |UNUSED | |15 | | | | | | | | |
|K22 | | |VCCO_15 | | |15 | | | | |any******| | | |
|K23 | |IOB33M |IO_L3P_T0_DQS_AD1P_15 |UNUSED | |15 | | | | | | | | |
|K24 | |IOB33S |IO_L3N_T0_DQS_AD1N_15 |UNUSED | |15 | | | | | | | | |
|K25 | |IOB33S |IO_L12N_T1_MRCC_AD5N_15 |UNUSED | |15 | | | | | | | | |
|K26 | |IOB33M |IO_L10P_T1_AD4P_15 |UNUSED | |15 | | | | | | | | |
|K27 | | |GND | | | | | | | | | | | |
|K28 | |IOB33M |IO_L13P_T2_MRCC_15 |UNUSED | |15 | | | | | | | | |
|K29 | |IOB33S |IO_L13N_T2_MRCC_15 |UNUSED | |15 | | | | | | | | |
|K30 | |IOB33S |IO_L9N_T1_DQS_AD11N_15 |UNUSED | |15 | | | | | | | | |
|L1 | | |GND | | | | | | | | | | | |
|L2 | | |GND | | | | | | | | | | | |
|L3 | |OPAD |MGTXTXN3_116 |UNUSED | | | | | | | | | | |
|L4 | |OPAD |MGTXTXP3_116 |UNUSED | | | | | | | | | | |
|L5 | | |MGTAVTT | | | | | | | | | | | |
|L6 | | |GND | | | | | | | | | | | |
|L7 | |IPAD |MGTREFCLK0N_116 |UNUSED | | | | | | | | | | |
|L8 | |IPAD |MGTREFCLK0P_116 |UNUSED | | | | | | | | | | |
|L9 | | |GND | | | | | | | | | | | |
|L10 | | |CFGBVS_0 | | | | | | | | | | | |
|L11 | |IOB33M |IO_L6P_T0_18 |UNUSED | |18 | | | | | | | | |
|L12 | |IOB33M |IO_L3P_T0_DQS_18 |UNUSED | |18 | | | | | | | | |
|L13 | |IOB33S |IO_L3N_T0_DQS_18 |UNUSED | |18 | | | | | | | | |
|L14 | | |GND | | | | | | | | | | | |
|L15 | |IOB33M |IO_L2P_T0_18 |UNUSED | |18 | | | | | | | | |
|L16 | |IOB33M |IO_L1P_T0_18 |UNUSED | |18 | | | | | | | | |
|L17 | |IOB33M |IO_L5P_T0_17 |UNUSED | |17 | | | | | | | | |
|L18 | |IOB33S |IO_L5N_T0_17 |UNUSED | |17 | | | | | | | | |
|L19 | | |VCCO_17 | | |17 | | | | |any******| | | |
|L20 | |IOB33S |IO_L6N_T0_VREF_15 |UNUSED | |15 | | | | | | | | |
|L21 | |IOB33M |IO_L4P_T0_AD9P_15 |UNUSED | |15 | | | | | | | | |
|L22 | |IOB33M |IO_L2P_T0_AD8P_15 |UNUSED | |15 | | | | | | | | |
|L23 | |IOB33S |IO_L2N_T0_AD8N_15 |UNUSED | |15 | | | | | | | | |
|L24 | | |GND | | | | | | | | | | | |
|L25 | |IOB33M |IO_L12P_T1_MRCC_AD5P_15 |UNUSED | |15 | | | | | | | | |
|L26 | |IOB33M |IO_L11P_T1_SRCC_AD12P_15 |UNUSED | |15 | | | | | | | | |
|L27 | |IOB33S |IO_L11N_T1_SRCC_AD12N_15 |UNUSED | |15 | | | | | | | | |
|L28 | |IOB33S |IO_L14N_T2_SRCC_15 |UNUSED | |15 | | | | | | | | |
|L29 | | |VCCO_15 | | |15 | | | | |any******| | | |
|L30 | |IOB33M |IO_L9P_T1_DQS_AD11P_15 |UNUSED | |15 | | | | | | | | |
|M1 | |OPAD |MGTXTXN2_116 |UNUSED | | | | | | | | | | |
|M2 | |OPAD |MGTXTXP2_116 |UNUSED | | | | | | | | | | |
|M3 | | |MGTAVTT | | | | | | | | | | | |
|M4 | | |GND | | | | | | | | | | | |
|M5 | |IPAD |MGTXRXN3_116 |UNUSED | | | | | | | | | | |
|M6 | |IPAD |MGTXRXP3_116 |UNUSED | | | | | | | | | | |
|M7 | | |MGTAVCC | | | | | | | | | | | |
|M8 | | |GND | | | | | | | | | | | |
|M9 | | |GND | | | | | | | | | | | |
|M10 | | |DONE_0 | | | | | | | | | | | |
|M11 | | |VCCINT | | | | | | | |1.0 | | | |
|M12 | | |GND | | | | | | | | | | | |
|M13 | | |VCCINT | | | | | | | |1.0 | | | |
|M14 | | |GND | | | | | | | | | | | |
|M15 | | |VCCINT | | | | | | | |1.0 | | | |
|M16 | | |GND | | | | | | | | | | | |
|M17 | | |VCCINT | | | | | | | |1.0 | | | |
|M18 | | |GND | | | | | | | | | | | |
|M19 | |IOB33 |IO_0_15 |UNUSED | |15 | | | | | | | | |
|M20 | |IOB33M |IO_L6P_T0_15 |UNUSED | |15 | | | | | | | | |
|M21 | | |GND | | | | | | | | | | | |
|M22 | |IOB33M |IO_L24P_T3_RS1_15 |UNUSED | |15 | | | | | | | | |
|M23 | |IOB33S |IO_L24N_T3_RS0_15 |UNUSED | |15 | | | | | | | | |
|M24 | |IOB33M |IO_L23P_T3_FOE_B_15 |UNUSED | |15 | | | | | | | | |
|M25 | |IOB33S |IO_L23N_T3_FWE_B_15 |UNUSED | |15 | | | | | | | | |
|M26 | | |VCCO_15 | | |15 | | | | |any******| | | |
|M27 | |IOB33S |IO_L16N_T2_A27_15 |UNUSED | |15 | | | | | | | | |
|M28 | |IOB33M |IO_L14P_T2_SRCC_15 |UNUSED | |15 | | | | | | | | |
|M29 | |IOB33M |IO_L15P_T2_DQS_15 |UNUSED | |15 | | | | | | | | |
|M30 | |IOB33S |IO_L15N_T2_DQS_ADV_B_15 |UNUSED | |15 | | | | | | | | |
|N1 | | |GND | | | | | | | | | | | |
|N2 | | |GND | | | | | | | | | | | |
|N3 | |OPAD |MGTXTXN1_116 |UNUSED | | | | | | | | | | |
|N4 | |OPAD |MGTXTXP1_116 |UNUSED | | | | | | | | | | |
|N5 | | |MGTAVTT | | | | | | | | | | | |
|N6 | | |GND | | | | | | | | | | | |
|N7 | |IPAD |MGTREFCLK1N_116 |UNUSED | | | | | | | | | | |
|N8 | |IPAD |MGTREFCLK1P_116 |UNUSED | | | | | | | | | | |
|N9 | | |GND | | | | | | | | | | | |
|N10 | | |VCCINT | | | | | | | |1.0 | | | |
|N11 | | |GND | | | | | | | | | | | |
|N12 | | |VCCINT | | | | | | | |1.0 | | | |
|N13 | | |GND | | | | | | | | | | | |
|N14 | | |VCCINT | | | | | | | |1.0 | | | |
|N15 | | |GND | | | | | | | | | | | |
|N16 | | |VCCBRAM | | | | | | | | | | | |
|N17 | | |GND | | | | | | | | | | | |
|N18 | | |VCCINT | | | | | | | |1.0 | | | |
|N19 | |IOB33M |IO_L19P_T3_A22_15 |UNUSED | |15 | | | | | | | | |
|N20 | |IOB33S |IO_L19N_T3_A21_VREF_15 |UNUSED | |15 | | | | | | | | |
|N21 | |IOB33M |IO_L20P_T3_A20_15 |UNUSED | |15 | | | | | | | | |
|N22 | |IOB33S |IO_L20N_T3_A19_15 |UNUSED | |15 | | | | | | | | |
|N23 | | |VCCO_15 | | |15 | | | | |any******| | | |
|N24 | |IOB33S |IO_L21N_T3_DQS_A18_15 |UNUSED | |15 | | | | | | | | |
|N25 | |IOB33M |IO_L18P_T2_A24_15 |UNUSED | |15 | | | | | | | | |
|N26 | |IOB33S |IO_L18N_T2_A23_15 |UNUSED | |15 | | | | | | | | |
|N27 | |IOB33M |IO_L16P_T2_A28_15 |UNUSED | |15 | | | | | | | | |
|N28 | | |GND | | | | | | | | | | | |
|N29 | |IOB33M |IO_L17P_T2_A26_15 |UNUSED | |15 | | | | | | | | |
|N30 | |IOB33S |IO_L17N_T2_A25_15 |UNUSED | |15 | | | | | | | | |
|P1 | |OPAD |MGTXTXN0_116 |UNUSED | | | | | | | | | | |
|P2 | |OPAD |MGTXTXP0_116 |UNUSED | | | | | | | | | | |
|P3 | | |MGTAVTT | | | | | | | | | | | |
|P4 | | |GND | | | | | | | | | | | |
|P5 | |IPAD |MGTXRXN2_116 |UNUSED | | | | | | | | | | |
|P6 | |IPAD |MGTXRXP2_116 |UNUSED | | | | | | | | | | |
|P7 | | |MGTAVCC | | | | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | |
|P9 | | |GND | | | | | | | | | | | |
|P10 | | |GND | | | | | | | | | | | |
|P11 | | |VCCINT | | | | | | | |1.0 | | | |
|P12 | | |GND | | | | | | | | | | | |
|P13 | | |VCCAUX | | | | | | | |1.8 | | | |
|P14 | | |GNDADC_0 | | | | | | | | | | | |
|P15 | | |VCCADC_0 | | | | | | | | | | | |
|P16 | | |GND | | | | | | | | | | | |
|P17 | | |VCCINT | | | | | | | |1.0 | | | |
|P18 | | |GND | | | | | | | | | | | |
|P19 | |IOB33 |IO_25_15 |UNUSED | |15 | | | | | | | | |
|P20 | | |VCCO_15 | | |15 | | | | |any******| | | |
|P21 | |IOB33M |IO_L22P_T3_A17_15 |UNUSED | |15 | | | | | | | | |
|P22 | |IOB33S |IO_L22N_T3_A16_15 |UNUSED | |15 | | | | | | | | |
|P23 | |IOB33M |IO_L21P_T3_DQS_15 |UNUSED | |15 | | | | | | | | |
|P24 | |IOB33M |IO_L1P_T0_D00_MOSI_14 |UNUSED | |14 | | | | | | | | |
|P25 | | |GND | | | | | | | | | | | |
|P26 | |IOB33M |IO_L10P_T1_D14_14 |UNUSED | |14 | | | | | | | | |
|P27 | |IOB33M |IO_L8P_T1_D11_14 |UNUSED | |14 | | | | | | | | |
|P28 | |IOB33S |IO_L8N_T1_D12_14 |UNUSED | |14 | | | | | | | | |
|P29 | |IOB33M |IO_L7P_T1_D09_14 |UNUSED | |14 | | | | | | | | |
|P30 | | |VCCO_14 | | |14 | | | | |any******| | | |
|R1 | | |GND | | | | | | | | | | | |
|R2 | | |GND | | | | | | | | | | | |
|R3 | |IPAD |MGTXRXN1_116 |UNUSED | | | | | | | | | | |
|R4 | |IPAD |MGTXRXP1_116 |UNUSED | | | | | | | | | | |
|R5 | | |MGTAVTT | | | | | | | | | | | |
|R6 | | |GND | | | | | | | | | | | |
|R7 | |IPAD |MGTREFCLK0N_115 |UNUSED | | | | | | | | | | |
|R8 | |IPAD |MGTREFCLK0P_115 |UNUSED | | | | | | | | | | |
|R9 | | |GND | | | | | | | | | | | |
|R10 | | |VCCINT | | | | | | | |1.0 | | | |
|R11 | | |GND | | | | | | | | | | | |
|R12 | | |VCCINT | | | | | | | |1.0 | | | |
|R13 | | |GND | | | | | | | | | | | |
|R14 | | |VREFN_0 | | | | | | | | | | | |
|R15 | |IPAD |VP_0 |UNUSED | |0 | | | | | | | | |
|R16 | | |VCCBRAM | | | | | | | | | | | |
|R17 | | |GND | | | | | | | | | | | |
|R18 | | |VCCINT | | | | | | | |1.0 | | | |
|R19 | |IOB33 |IO_0_14 |UNUSED | |14 | | | | | | | | |
|R20 | |IOB33M |IO_L2P_T0_D02_14 |UNUSED | |14 | | | | | | | | |
|R21 | |IOB33S |IO_L2N_T0_D03_14 |UNUSED | |14 | | | | | | | | |
|R22 | | |GND | | | | | | | | | | | |
|R23 | |IOB33M |IO_L3P_T0_DQS_PUDC_B_14 |UNUSED | |14 | | | | | | | | |
|R24 | |IOB33S |IO_L3N_T0_DQS_EMCCLK_14 |UNUSED | |14 | | | | | | | | |
|R25 | |IOB33S |IO_L1N_T0_D01_DIN_14 |UNUSED | |14 | | | | | | | | |
|R26 | |IOB33S |IO_L10N_T1_D15_14 |UNUSED | |14 | | | | | | | | |
|R27 | | |VCCO_14 | | |14 | | | | |any******| | | |
|R28 | |IOB33M |IO_L11P_T1_SRCC_14 |UNUSED | |14 | | | | | | | | |
|R29 | |IOB33S |IO_L7N_T1_D10_14 |UNUSED | |14 | | | | | | | | |
|R30 | |IOB33M |IO_L9P_T1_DQS_14 |UNUSED | |14 | | | | | | | | |
|T1 | |OPAD |MGTXTXN3_115 |UNUSED | | | | | | | | | | |
|T2 | |OPAD |MGTXTXP3_115 |UNUSED | | | | | | | | | | |
|T3 | | |MGTAVTT | | | | | | | | | | | |
|T4 | | |GND | | | | | | | | | | | |
|T5 | |IPAD |MGTXRXN0_116 |UNUSED | | | | | | | | | | |
|T6 | |IPAD |MGTXRXP0_116 |UNUSED | | | | | | | | | | |
|T7 | | |MGTVCCAUX | | | | | | | | | | | |
|T8 | | |GND | | | | | | | | | | | |
|T9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|T10 | | |GND | | | | | | | | | | | |
|T11 | | |VCCINT | | | | | | | |1.0 | | | |
|T12 | | |GND | | | | | | | | | | | |
|T13 | | |VCCAUX | | | | | | | |1.8 | | | |
|T14 | |IPAD |VN_0 |UNUSED | |0 | | | | | | | | |
|T15 | | |VREFP_0 | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
|T17 | | |VCCINT | | | | | | | |1.0 | | | |
|T18 | | |GND | | | | | | | | | | | |
|T19 | | |GND | | | | | | | | | | | |
|T20 | |IOB33M |IO_L4P_T0_D04_14 |UNUSED | |14 | | | | | | | | |
|T21 | |IOB33S |IO_L4N_T0_D05_14 |UNUSED | |14 | | | | | | | | |
|T22 | |IOB33M |IO_L5P_T0_D06_14 |UNUSED | |14 | | | | | | | | |
|T23 | |IOB33S |IO_L5N_T0_D07_14 |UNUSED | |14 | | | | | | | | |
|T24 | | |VCCO_14 | | |14 | | | | |any******| | | |
|T25 | |IOB33M |IO_L14P_T2_SRCC_14 |UNUSED | |14 | | | | | | | | |
|T26 | |IOB33M |IO_L12P_T1_MRCC_14 |UNUSED | |14 | | | | | | | | |
|T27 | |IOB33S |IO_L12N_T1_MRCC_14 |UNUSED | |14 | | | | | | | | |
|T28 | |IOB33S |IO_L11N_T1_SRCC_14 |UNUSED | |14 | | | | | | | | |
|T29 | | |GND | | | | | | | | | | | |
|T30 | |IOB33S |IO_L9N_T1_DQS_D13_14 |UNUSED | |14 | | | | | | | | |
|U1 | | |GND | | | | | | | | | | | |
|U2 | | |GND | | | | | | | | | | | |
|U3 | |OPAD |MGTXTXN2_115 |UNUSED | | | | | | | | | | |
|U4 | |OPAD |MGTXTXP2_115 |UNUSED | | | | | | | | | | |
|U5 | | |MGTAVTT | | | | | | | | | | | |
|U6 | | |GND | | | | | | | | | | | |
|U7 | |IPAD |MGTREFCLK1N_115 |UNUSED | | | | | | | | | | |
|U8 | |IPAD |MGTREFCLK1P_115 |UNUSED | | | | | | | | | | |
|U9 | | |GND | | | | | | | | | | | |
|U10 | | |VCCINT | | | | | | | |1.0 | | | |
|U11 | | |GND | | | | | | | | | | | |
|U12 | | |VCCINT | | | | | | | |1.0 | | | |
|U13 | | |GND | | | | | | | | | | | |
|U14 | | |DXN_0 | | | | | | | | | | | |
|U15 | | |DXP_0 | | | | | | | | | | | |
|U16 | | |VCCBRAM | | | | | | | | | | | |
|U17 | | |GND | | | | | | | | | | | |
|U18 | | |VCCINT | | | | | | | |1.0 | | | |
|U19 | |IOB33M |IO_L6P_T0_FCS_B_14 |UNUSED | |14 | | | | | | | | |
|U20 | |IOB33S |IO_L6N_T0_D08_VREF_14 |UNUSED | |14 | | | | | | | | |
|U21 | | |VCCO_14 | | |14 | | | | |any******| | | |
|U22 | |IOB33M |IO_L21P_T3_DQS_14 |UNUSED | |14 | | | | | | | | |
|U23 | |IOB33S |IO_L21N_T3_DQS_A06_D22_14 |UNUSED | |14 | | | | | | | | |
|U24 | |IOB33M |IO_L23P_T3_A03_D19_14 |UNUSED | |14 | | | | | | | | |
|U25 | |IOB33S |IO_L14N_T2_SRCC_14 |UNUSED | |14 | | | | | | | | |
|U26 | | |GND | | | | | | | | | | | |
|U27 | |IOB33M |IO_L13P_T2_MRCC_14 |UNUSED | |14 | | | | | | | | |
|U28 | |IOB33S |IO_L13N_T2_MRCC_14 |UNUSED | |14 | | | | | | | | |
|U29 | |IOB33M |IO_L15P_T2_DQS_RDWR_B_14 |UNUSED | |14 | | | | | | | | |
|U30 | |IOB33S |IO_L15N_T2_DQS_DOUT_CSO_B_14|UNUSED | |14 | | | | | | | | |
|V1 | |OPAD |MGTXTXN1_115 |UNUSED | | | | | | | | | | |
|V2 | |OPAD |MGTXTXP1_115 |UNUSED | | | | | | | | | | |
|V3 | | |MGTAVTT | | | | | | | | | | | |
|V4 | | |GND | | | | | | | | | | | |
|V5 | |IPAD |MGTXRXN3_115 |UNUSED | | | | | | | | | | |
|V6 | |IPAD |MGTXRXP3_115 |UNUSED | | | | | | | | | | |
|V7 | | |MGTVCCAUX | | | | | | | | | | | |
|V8 | | |GND | | | | | | | | | | | |
|V9 | | |GND | | | | | | | | | | | |
|V10 | | |GND | | | | | | | | | | | |
|V11 | | |VCCAUX_IO_G0 | | | | | | | |1.8 | | | |
|V12 | | |GND | | | | | | | | | | | |
|V13 | | |VCCAUX | | | | | | | |1.8 | | | |
|V14 | | |GND | | | | | | | | | | | |
|V15 | | |VCCAUX | | | | | | | |1.8 | | | |
|V16 | | |GND | | | | | | | | | | | |
|V17 | | |VCCINT | | | | | | | |1.0 | | | |
|V18 | | |GND | | | | | | | | | | | |
|V19 | |IOB33M |IO_L19P_T3_A10_D26_14 |UNUSED | |14 | | | | | | | | |
|V20 | |IOB33S |IO_L19N_T3_A09_D25_VREF_14 |UNUSED | |14 | | | | | | | | |
|V21 | |IOB33M |IO_L22P_T3_A05_D21_14 |UNUSED | |14 | | | | | | | | |
|V22 | |IOB33S |IO_L22N_T3_A04_D20_14 |UNUSED | |14 | | | | | | | | |
|V23 | | |GND | | | | | | | | | | | |
|V24 | |IOB33S |IO_L23N_T3_A02_D18_14 |UNUSED | |14 | | | | | | | | |
|V25 | |IOB33M |IO_L18P_T2_A12_D28_14 |UNUSED | |14 | | | | | | | | |
|V26 | |IOB33M |IO_L16P_T2_CSI_B_14 |UNUSED | |14 | | | | | | | | |
|V27 | |IOB33S |IO_L16N_T2_A15_D31_14 |UNUSED | |14 | | | | | | | | |
|V28 | | |VCCO_14 | | |14 | | | | |any******| | | |
|V29 | |IOB33M |IO_L17P_T2_A14_D30_14 |UNUSED | |14 | | | | | | | | |
|V30 | |IOB33S |IO_L17N_T2_A13_D29_14 |UNUSED | |14 | | | | | | | | |
|W1 | | |GND | | | | | | | | | | | |
|W2 | | |GND | | | | | | | | | | | |
|W3 | |IPAD |MGTXRXN2_115 |UNUSED | | | | | | | | | | |
|W4 | |IPAD |MGTXRXP2_115 |UNUSED | | | | | | | | | | |
|W5 | | |MGTAVTT | | | | | | | | | | | |
|W6 | | |GND | | | | | | | | | | | |
|W7 | | |MGTAVTTRCAL_115 | | | | | | | | | | | |
|W8 | | |MGTRREF_115 | | | | | | | | | | | |
|W9 | | |GND | | | | | | | | | | | |
|W10 | | |VCCAUX_IO_G0 | | | | | | | |1.8 | | | |
|W11 | | |GND | | | | | | | | | | | |
|W12 | | |VCCAUX_IO_G0 | | | | | | | |1.8 | | | |
|W13 | | |GND | | | | | | | | | | | |
|W14 | | |VCCAUX | | | | | | | |1.8 | | | |
|W15 | | |GND | | | | | | | | | | | |
|W16 | | |VCCBRAM | | | | | | | | | | | |
|W17 | | |GND | | | | | | | | | | | |
|W18 | | |VCCINT | | | | | | | |1.0 | | | |
|W19 | |IOB33 |IO_25_14 |UNUSED | |14 | | | | | | | | |
|W20 | | |GND | | | | | | | | | | | |
|W21 | |IOB33M |IO_L24P_T3_A01_D17_14 |UNUSED | |14 | | | | | | | | |
|W22 | |IOB33S |IO_L24N_T3_A00_D16_14 |UNUSED | |14 | | | | | | | | |
|W23 | |IOB33M |IO_L20P_T3_A08_D24_14 |UNUSED | |14 | | | | | | | | |
|W24 | |IOB33S |IO_L20N_T3_A07_D23_14 |UNUSED | |14 | | | | | | | | |
|W25 | | |VCCO_14 | | |14 | | | | |any******| | | |
|W26 | |IOB33S |IO_L18N_T2_A11_D27_14 |UNUSED | |14 | | | | | | | | |
|W27 | |IOB33M |IO_L2P_T0_13 |UNUSED | |13 | | | | | | | | |
|W28 | |IOB33S |IO_L2N_T0_13 |UNUSED | |13 | | | | | | | | |
|W29 | |IOB33M |IO_L4P_T0_13 |UNUSED | |13 | | | | | | | | |
|W30 | | |GND | | | | | | | | | | | |
|Y1 | |OPAD |MGTXTXN0_115 |UNUSED | | | | | | | | | | |
|Y2 | |OPAD |MGTXTXP0_115 |UNUSED | | | | | | | | | | |
|Y3 | | |GND | | | | | | | | | | | |
|Y4 | | |GND | | | | | | | | | | | |
|Y5 | |IPAD |MGTXRXN1_115 |UNUSED | | | | | | | | | | |
|Y6 | |IPAD |MGTXRXP1_115 |UNUSED | | | | | | | | | | |
|Y7 | | |GND | | | | | | | | | | | |
|Y8 | | |GND | | | | | | | | | | | |
|Y9 | | |GND | | | | | | | | | | | |
|Y10 |ddr3_addr<9> |IOB18 |IO_L4N_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|Y11 |ddr3_addr<10> |IOB18 |IO_L4P_T0_33 |OUTPUT |SSTL15 |33 | |FAST | | | |LOCATED |NO |NONE |
|Y12 | | |VCCO_33 | | |33 | | | | |1.50 | | | |
|Y13 | |IOB18 |IO_0_VRN_33 |UNUSED | |33 | | | | | | | | |
|Y14 | |IOB18 |IO_0_VRN_32 |UNUSED | |32 | | | | | | | | |
|Y15 | |IOB18S |IO_L24N_T3_32 |UNUSED | |32 | | | | | | | | |
|Y16 | |IOB18M |IO_L24P_T3_32 |UNUSED | |32 | | | | | | | | |
|Y17 | | |GND | | | | | | | | | | | |
|Y18 | |IOB18S |IO_L15N_T2_DQS_32 |UNUSED | |32 | | | | | | | | |
|Y19 | |IOB18M |IO_L15P_T2_DQS_32 |UNUSED | |32 | | | | | | | | |
|Y20 | |IOB33 |IO_0_12 |UNUSED | |12 | | | | | | | | |
|Y21 | |IOB33M |IO_L2P_T0_12 |UNUSED | |12 | | | | | | | | |
|Y22 | | |VCCO_12 | | |12 | | | | |any******| | | |
|Y23 | |IOB33M |IO_L1P_T0_12 |UNUSED | |12 | | | | | | | | |
|Y24 | |IOB33S |IO_L1N_T0_12 |UNUSED | |12 | | | | | | | | |
|Y25 | |IOB33 |IO_0_13 |UNUSED | |13 | | | | | | | | |
|Y26 | |IOB33M |IO_L1P_T0_13 |UNUSED | |13 | | | | | | | | |
|Y27 | | |GND | | | | | | | | | | | |
|Y28 | |IOB33M |IO_L3P_T0_DQS_13 |UNUSED | |13 | | | | | | | | |
|Y29 | |IOB33S |IO_L4N_T0_13 |UNUSED | |13 | | | | | | | | |
|Y30 |tg_compare_error |IOB33 |IO_L8P_T1_13 |OUTPUT |LVCMOS33 |13 |12 |SLOW | | | |LOCATED |NO |NONE |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
All RSVD_0 pins must be tied to GROUND.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
top/x300/coregen/ddr3_32bit/example_design/par/example_top_par.xrpt
+6494
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top_summary.xml
+10
View File
@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>
top/x300/coregen/ddr3_32bit/example_design/par/example_top_usage.xml
+5556
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/example_top_xst.xrpt
+320
View File
@@ -0,0 +1,320 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.4">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Tue Jan 22 18:20:29 2013">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/opt/Xilinx/14.4/ISE_DS/ISE/sysgen/lib:/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:/usr/lib:/usr/local/lib"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="2100@10.0.52.74:/usr/local/flexlm"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.4/ISE_DS/../../Vivado_HLS/2012.4/bin:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.4/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.4/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4/bin:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/EDK/gnu/microblaze/lin64/bin:/opt/Xilinx/14.4/ISE_DS/EDK/gnu/powerpc-eabi/lin64/bin:/opt/Xilinx/14.4/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.4/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.4/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/home/ianb/bin:/home/ianb/gnuradio_redirect/bin:/usr/lib/lightdm/lightdm:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/opt/microblaze/bin:/opt/zpu/install/bin"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_VIVADO"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="LMC_HOME"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
</row>
<row stringID="row" value="7">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="8">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.4/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 12.10"/>
</item>
<item stringID="User_EnvHost" value="server2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz"/>
<item stringID="speed" value="1600.000 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="../synth/example_top.prj"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="example_top"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc7k410t-2-ffg900"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="example_top"/>
<item DEFAULT="" label="-lso" stringID="XST_LSO" value="../synth/example_top.lso"/>
</section>
<section stringID="XST_UNISIM_SUMMARY">
<item dataType="int" stringID="XST_NUM_AND2B1L" value="1"/>
<item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
<item dataType="int" stringID="XST_NUM_BUFH" value="1"/>
<item dataType="int" stringID="XST_NUM_BUFIO" value="1"/>
<item dataType="int" stringID="XST_NUM_FDRE" value="641"/>
<item dataType="int" stringID="XST_NUM_FDSE" value="2"/>
<item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="XST_NUM_IDELAYCTRL" value="1"/>
<item dataType="int" stringID="XST_NUM_IDELAYE2" value="16"/>
<item dataType="int" stringID="XST_NUM_ISERDESE2" value="16"/>
<item dataType="int" stringID="XST_NUM_LUT4" value="8"/>
<item dataType="int" stringID="XST_NUM_LUT6" value="290"/>
<item dataType="int" stringID="XST_NUM_MUXCY" value="1"/>
<item dataType="int" stringID="XST_NUM_OBUF" value="1"/>
<item dataType="int" stringID="XST_NUM_OBUFDS" value="1"/>
<item dataType="int" stringID="XST_NUM_OBUFT" value="1"/>
<item dataType="int" stringID="XST_NUM_ODDR" value="5"/>
<item dataType="int" stringID="XST_NUM_OR2L" value="1"/>
<item dataType="int" stringID="XST_NUM_OSERDESE2" value="44"/>
<item dataType="int" stringID="XST_NUM_RAM32M" value="96"/>
<item dataType="int" stringID="XST_NUM_SRLC32E" value="43"/>
<item dataType="int" stringID="XST_NUM_XADC" value="1"/>
<item dataType="int" stringID="XST_NUM_XORCY" value="1"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="5"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="542">
<item dataType="int" stringID="XST_10BIT_ADDER" value="4"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
<item dataType="int" stringID="XST_2BIT_SUBTRACTOR" value="32"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="25"/>
<item dataType="int" stringID="XST_3BIT_SUBTRACTOR" value="11"/>
<item dataType="int" stringID="XST_32BIT_ADDER" value="7"/>
<item dataType="int" stringID="XST_4BIT_ADDER" value="19"/>
<item dataType="int" stringID="XST_4BIT_SUBTRACTOR" value="12"/>
<item dataType="int" stringID="XST_5BIT_SUBTRACTOR" value="8"/>
<item dataType="int" stringID="XST_6BIT_SUBTRACTOR" value="27"/>
<item dataType="int" stringID="XST_7BIT_ADDER" value="38"/>
<item dataType="int" stringID="XST_7BIT_SUBTRACTOR" value="11"/>
<item dataType="int" stringID="XST_8BIT_ADDER" value="38"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="2510">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1887"/>
<item dataType="int" stringID="XST_10BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_11BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="7"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="69"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="84"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="19"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="91"/>
<item dataType="int" stringID="XST_5BIT_REGISTER" value="50"/>
<item dataType="int" stringID="XST_6BIT_REGISTER" value="61"/>
<item dataType="int" stringID="XST_7BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="76"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="7"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="495">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="210"/>
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="8"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="6"/>
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_EQUAL" value="14"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="8"/>
<item dataType="int" stringID="XST_7BIT_COMPARATOR_LESSEQUAL" value="16"/>
<item dataType="int" stringID="XST_8BIT_COMPARATOR_GREATER" value="4"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="3049">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="1922"/>
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="18"/>
<item dataType="int" stringID="XST_10BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="100"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="140"/>
<item dataType="int" stringID="XST_3BIT_4TO1_MULTIPLEXER" value="6"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="59"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="78"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="67"/>
<item dataType="int" stringID="XST_6BIT_2TO1_MULTIPLEXER" value="234"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="22"/>
<item dataType="int" stringID="XST_8BIT_8TO1_MULTIPLEXER" value="2"/>
</item>
<item dataType="int" stringID="XST_FSMS" value="14"/>
<item dataType="int" stringID="XST_XORS" value="31">
<item dataType="int" stringID="XST_1BIT_XOR2" value="30"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="5"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="326">
<item dataType="int" stringID="XST_10BIT_ADDER" value="1"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
<item dataType="int" stringID="XST_2BIT_SUBTRACTOR" value="26"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="10"/>
<item dataType="int" stringID="XST_3BIT_SUBTRACTOR" value="6"/>
<item dataType="int" stringID="XST_32BIT_ADDER" value="5"/>
<item dataType="int" stringID="XST_4BIT_ADDER" value="6"/>
<item dataType="int" stringID="XST_4BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_5BIT_SUBTRACTOR" value="6"/>
<item dataType="int" stringID="XST_6BIT_SUBTRACTOR" value="20"/>
<item dataType="int" stringID="XST_7BIT_ADDER" value="8"/>
<item dataType="int" stringID="XST_7BIT_SUBTRACTOR" value="16"/>
<item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
</item>
<item dataType="int" stringID="XST_COUNTERS" value="121">
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="3"/>
<item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="3"/>
<item dataType="int" stringID="XST_2BIT_DOWN_COUNTER" value="6"/>
<item dataType="int" stringID="XST_2BIT_UP_COUNTER" value="12"/>
<item dataType="int" stringID="XST_3BIT_DOWN_COUNTER" value="5"/>
<item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="15"/>
<item dataType="int" stringID="XST_4BIT_DOWN_COUNTER" value="8"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="14"/>
<item dataType="int" stringID="XST_5BIT_DOWN_COUNTER" value="2"/>
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_ACCUMULATORS" value="1"></item>
<item dataType="int" stringID="XST_REGISTERS" value="14499">
<item dataType="int" stringID="XST_FLIPFLOPS" value="14499"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="556"></item>
<item dataType="int" stringID="XST_COMPARATORS" value="495">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="210"/>
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="8"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="6"/>
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_EQUAL" value="14"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="8"/>
<item dataType="int" stringID="XST_7BIT_COMPARATOR_LESSEQUAL" value="16"/>
<item dataType="int" stringID="XST_8BIT_COMPARATOR_GREATER" value="4"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="3653">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="2646"/>
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="27"/>
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="94"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="119"/>
<item dataType="int" stringID="XST_3BIT_4TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="51"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="63"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="58"/>
<item dataType="int" stringID="XST_6BIT_2TO1_MULTIPLEXER" value="180"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="20"/>
<item dataType="int" stringID="XST_8BIT_8TO1_MULTIPLEXER" value="2"/>
</item>
<item dataType="int" stringID="XST_FSMS" value="14"/>
<item dataType="int" stringID="XST_XORS" value="31">
<item dataType="int" stringID="XST_1BIT_XOR2" value="30"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="11836">
<item dataType="int" stringID="XST_FLIPFLOPS" value="11836"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="26">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="12"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="3"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_DESIGN_SUMMARY">
<section stringID="XST_">
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="example_top.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="10936">
<item dataType="int" stringID="XST_GND" value="12"/>
<item dataType="int" stringID="XST_INV" value="288"/>
<item dataType="int" stringID="XST_LUT1" value="175"/>
<item dataType="int" stringID="XST_LUT2" value="683"/>
<item dataType="int" stringID="XST_LUT3" value="1514"/>
<item dataType="int" stringID="XST_LUT4" value="1268"/>
<item dataType="int" stringID="XST_LUT5" value="2132"/>
<item dataType="int" stringID="XST_LUT6" value="3594"/>
<item dataType="int" stringID="XST_MUXCY" value="544"/>
<item dataType="int" stringID="XST_MUXF5" value="2"/>
<item dataType="int" stringID="XST_MUXF6" value="1"/>
<item dataType="int" stringID="XST_MUXF7" value="46"/>
<item dataType="int" stringID="XST_MUXF8" value="2"/>
<item dataType="int" stringID="XST_VCC" value="12"/>
<item dataType="int" stringID="XST_XORCY" value="470"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="12843">
<item dataType="int" stringID="XST_FD" value="3123"/>
<item dataType="int" stringID="XST_FDC" value="120"/>
<item dataType="int" stringID="XST_FDCE" value="21"/>
<item dataType="int" stringID="XST_FDE" value="5190"/>
<item dataType="int" stringID="XST_FDP" value="544"/>
<item dataType="int" stringID="XST_FDR" value="750"/>
<item dataType="int" stringID="XST_FDRE" value="2425"/>
<item dataType="int" stringID="XST_FDS" value="186"/>
<item dataType="int" stringID="XST_FDSE" value="474"/>
<item dataType="int" stringID="XST_ODDR" value="9"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="146">
<item dataType="int" stringID="XST_RAMB18E1" value="1"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="979">
<item dataType="int" stringID="XST_SRL16" value="192"/>
<item dataType="int" stringID="XST_SRL16E" value="1"/>
<item dataType="int" stringID="XST_SRLC16E" value="318"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="3">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="3"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="70">
<item dataType="int" stringID="XST_IBUF" value="1"/>
<item dataType="int" stringID="XST_IBUFG" value="1"/>
<item dataType="int" stringID="XST_OBUF" value="27"/>
<item dataType="int" stringID="XST_OBUFT" value="4"/>
</item>
<item dataType="int" stringID="XST_OTHERS" value="178">
<item dataType="int" stringID="XST_BUFHCE" value="1"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="7k410tffg900-2"/>
<item AVAILABLE="508400" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="12843"/>
<item AVAILABLE="254200" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="11219"/>
<item AVAILABLE="254200" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="9680"/>
<item AVAILABLE="90600" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="1539"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="979"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="16784"/>
<item AVAILABLE="16784" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="3941"/>
<item AVAILABLE="16784" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="5565"/>
<item AVAILABLE="16784" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="7278"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="496"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
<item AVAILABLE="500" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="75"/>
<item AVAILABLE="795" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="6"/>
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="6"/>
<item AVAILABLE="32" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="3"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="2995"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="770"/>
</section>
</application>
</document>
top/x300/coregen/ddr3_32bit/example_design/par/ise_flow.sh
Executable
+116
View File
@@ -0,0 +1,116 @@
#!/bin/csh -f
##*****************************************************************************
## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 1.8
## \ \ Application : MIG
## / / Filename : ise_flow.sh
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:14 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Script file to run Synthesis and PAR through ISE in batch mode
## Reference :
## Revision History :
##****************************************************************************
./rem_files.sh
echo Synthesis Tool: XST
mkdir "../synth/__projnav" > ise_flow_results.txt
mkdir "../synth/xst" >> ise_flow_results.txt
mkdir "../synth/xst/work" >> ise_flow_results.txt
xst -ifn xst_options.txt -ofn example_top.syr -intstyle ise >> ise_flow_results.txt
if( ! -e example_top.ngc ) then
echo Failed in SYNTHESIS
exit
endif
echo Implementation Tool: ISE
echo Running TRANSLATE
ngdbuild -intstyle ise -dd ../synth/_ngo -nt timestamp -uc example_top.ucf -p xc7k410t-ffg900-2 example_top.ngc example_top.ngd >> ise_flow_results.txt
if( ! -e example_top.ngd ) then
echo Failed in TRANSLATE
exit
endif
echo Running MAP
map -intstyle ise -p xc7k410t-ffg900-2 -w -ol high -xe n -register_duplication off -ir off -pr off -lc off -power off -o example_top_map.ncd example_top.ngd example_top.pcf >> ise_flow_results.txt
if( ! -e example_top_map.ncd ) then
echo Failed in MAP
exit
endif
echo Running PAR
par -w -intstyle ise -ol high -xe n example_top_map.ncd example_top.ncd example_top.pcf >> ise_flow_results.txt
if( ! -e example_top.ncd ) then
echo Failed in PAR
exit
endif
echo Running TRACE
trce -intstyle ise -v 3 -fastpaths -xml example_top example_top.ncd -o example_top.twr example_top.pcf >> ise_flow_results.txt
echo Running BITGEN
bitgen -intstyle ise example_top.ncd >> ise_flow_results.txt
if( ! -e example_top.bit ) then
echo Failed in BITGEN
exit
endif
echo IMPLEMENTATION SUCCESSFUL
top/x300/coregen/ddr3_32bit/example_design/par/ise_flow_results.txt
+17336
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/par/makeproj.sh
Executable
+68
View File
@@ -0,0 +1,68 @@
#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 1.8
# \ \ Application : MIG
# / / Filename : makeproj
# /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:13 $
# \ \ / \ Date Created : Tue Sept 21 2010
# \___\/\___\
#
# Device : 7 Series
# Design Name : DDR3 SDRAM
# Purpose : Batch file to run Synthesis and PAR through ISE in batch mode
# Reference :
# Revision History :
# ****************************************************************************
NEWPROJECT .
SETPROJECT .
top/x300/coregen/ddr3_32bit/example_design/par/par_usage_statistics.html
+31
View File
@@ -0,0 +1,31 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>20541</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>67953</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>67953</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>64457</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>44.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>47.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>67.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>81.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>105.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>107.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>107.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>107.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>115.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>17.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>8.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>56.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.7611</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
top/x300/coregen/ddr3_32bit/example_design/par/readme.txt
+92
View File
@@ -0,0 +1,92 @@
This folder has the script files to synthesize using the XST and implement
the design through command mode or GUI mode.
Steps to run the design using the ise_flow (batch mode):
Windows OS:
1. Double clicking the "ise_flow.bat" file synthesizes the design using
XST and does the implementation of design.
Linux OS:
1. Run the "ise_flow.sh" command at the prompt as shown below:
> ./ise_flow.sh
Windows/Linux OS:
2. On running "ise_flow.sh/ise_flow.bat" file, removes the XST report files
first (if exist any on previous runs) and then does implementation of
the design.
3. Running the "ise_flow.sh/ise_flow.bat" file creates the ise_flow_results
text file. It has the report file data for all the XST tool processes.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.sh/create_ise.bat" file creates "test.xise"
project file and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the
"test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing
the command 'ise test.xise' from the terminal.
Other files in PAR folder :
* "example_top.ucf" file is the constraint file for the design. This is used
by ISE tool during translate phase. It has clock constraints, location
constraints, IO standards and MAXDELAY/SLICE constraints if any.
* "rem_files.sh/rem_files.bat" is called within the ise_flow.sh/ise_flow.bat
script. This deletes all the previous reports and design files (if any)
generated by ISE.
* "set_ise_prop.tcl" file has all the properties that needs to be set
in GUI mode. This file will appear only for XST cases.
* "xst_options.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon4_cg.xco", "ddr_ila_basic_cg.xco", "ddr_ila_rdpath_cg.xco",
"ddr_ila_wrpath_cg.xco" and "ddr_vio_sync_async_out72_cg.xco" files are
used to generate ChipScope icon, ila and vio EDIF/NGC files. When you want
to view the design signals on ChipScope, you should port the design signals
to ChipScope modules i.e. ila, vio and icon and set DEBUG_PORT parameter
to "ON" in example_top rtl file. In order to generate the EDIF/NGC files,
you must execute the following commands before starting synthesis and PAR.
coregen -b icon4_cg.xco
coregen -b ddr_ila_basic_cg.xco
coregen -b ddr_ila_rdpath_cg.xco
coregen -b ddr_ila_wrpath_cg.xco
coregen -b ddr_vio_sync_async_out72_cg.xco
Note : When you generate the design with DEBUG_PORT = "ON" option, then
appropriate ChipScope modules must be instantiated in the design top rtl
file. This folder must contain the necessary ChipScope .ngc files before
Synthesis and PAR of the design starts.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "example_top.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "example_top.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
Synth folder:
* "example_top.prj" file has commands to add all rtl files to the XST project
for synthesis.
* "example_top.lso" file is a custom library search order file for XST synthesis.
compatible_ucf folder:
* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI
(Pin Compatible FPGAs page in GUI). It generates the UCF files for all
the Compatible FPGAs selected in GUI. If you want to switch to any of the
Compatible FPGAs follow the steps mentioned below.
top/x300/coregen/ddr3_32bit/example_design/par/rem_files.sh
Executable
+232
View File
@@ -0,0 +1,232 @@
##!/bin/csh -f
##****************************************************************************
## (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 1.8
## \ \ Application : MIG
## / / Filename : rem_files.bat
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:13 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Batch file to remove files generated from ISE
## Reference :
## Revision History :
##****************************************************************************
rm -rf "../synth/__projnav"
rm -rf "../synth/xst"
rm -rf "../synth/_ngo"
rm -rf tmp
rm -rf _xmsgs
rm -rf xst
rm -rf xlnx_auto_0_xdb
rm -rf coregen.cgp
rm -rf coregen.cgc
rm -rf coregen.log
rm -rf ise_flow_results.txt
rm -rf xlnx_auto_0.ise
rm -rf example_top_vhdl.prj
rm -rf example_top.syr
rm -rf example_top.ngc
rm -rf example_top.ngr
rm -rf example_top_xst.xrpt
rm -rf example_top.bld
rm -rf example_top.ngd
rm -rf example_top_ngdbuild.xrpt
rm -rf example_top_map.map
rm -rf example_top_map.mrp
rm -rf example_top_map.ngm
rm -rf example_top.pcf
rm -rf example_top_map.ncd
rm -rf example_top_map.xrpt
rm -rf example_top_summary.xml
rm -rf example_top_usage.xml
rm -rf example_top.ncd
rm -rf example_top.par
rm -rf example_top.xpi
rm -rf smartpreview.twr
rm -rf example_top.ptwx
rm -rf example_top.pad
rm -rf example_top.unroutes
rm -rf example_top_pad.csv
rm -rf example_top_pad.txt
rm -rf example_top_par.xrpt
rm -rf example_top.twx
rm -rf example_top.bgn
rm -rf example_top.twr
rm -rf example_top.drc
rm -rf example_top_bitgen.xwbt
rm -rf example_top.bit
# Files and folders generated Coregen ChipScope Modules
rm -rf ddr_icon.asy
rm -rf ddr_icon.ngc
rm -rf ddr_icon.xco
rm -rf ddr_icon_xmdf.tcl
rm -rf ddr_icon.gise
rm -rf ddr_icon.ise
rm -rf ddr_icon.xise
rm -rf ddr_icon_flist.txt
rm -rf ddr_icon_readme.txt
rm -rf ddr_icon.cdc
rm -rf ddr_icon_xdb
rm -rf ddr_ila_basic.asy
rm -rf ddr_ila_basic.ngc
rm -rf ddr_ila_basic.constraints
rm -rf ddr_ila_basic.ncf
rm -rf ddr_ila_basic.ucf
rm -rf ddr_ila_basic.xdc
rm -rf ddr_ila_basic.xco
rm -rf ddr_ila_basic_xmdf.tcl
rm -rf ddr_ila_basic.gise
rm -rf ddr_ila_basic.ise
rm -rf ddr_ila_basic.xise
rm -rf ddr_ila_basic_flist.txt
rm -rf ddr_ila_basic_readme.txt
rm -rf ddr_ila_basic.cdc
rm -rf ddr_ila_basic_xdb
rm -rf ddr_ila_wrpath.asy
rm -rf ddr_ila_wrpath.ngc
rm -rf ddr_ila_wrpath.constraints
rm -rf ddr_ila_wrpath.ncf
rm -rf ddr_ila_wrpath.ucf
rm -rf ddr_ila_wrpath.xdc
rm -rf ddr_ila_wrpath.xco
rm -rf ddr_ila_wrpath_xmdf.tcl
rm -rf ddr_ila_wrpath.gise
rm -rf ddr_ila_wrpath.ise
rm -rf ddr_ila_wrpath.xise
rm -rf ddr_ila_wrpath_flist.txt
rm -rf ddr_ila_wrpath_readme.txt
rm -rf ddr_ila_wrpath.cdc
rm -rf ddr_ila_wrpath_xdb
rm -rf ddr_ila_rdpath.asy
rm -rf ddr_ila_rdpath.ngc
rm -rf ddr_ila_rdpath.constraints
rm -rf ddr_ila_rdpath.ncf
rm -rf ddr_ila_rdpath.ucf
rm -rf ddr_ila_rdpath.xdc
rm -rf ddr_ila_rdpath.xco
rm -rf ddr_ila_rdpath_xmdf.tcl
rm -rf ddr_ila_rdpath.gise
rm -rf ddr_ila_rdpath.ise
rm -rf ddr_ila_rdpath.xise
rm -rf ddr_ila_rdpath_flist.txt
rm -rf ddr_ila_rdpath_readme.txt
rm -rf ddr_ila_rdpath.cdc
rm -rf ddr_ila_rdpath_xdb
rm -rf ddr_vio_sync_async_out72.asy
rm -rf ddr_vio_sync_async_out72.ngc
rm -rf ddr_vio_sync_async_out72.constraints
rm -rf ddr_vio_sync_async_out72.ncf
rm -rf ddr_vio_sync_async_out72.ucf
rm -rf ddr_vio_sync_async_out72.xdc
rm -rf ddr_vio_sync_async_out72.xco
rm -rf ddr_vio_sync_async_out72_xmdf.tcl
rm -rf ddr_vio_sync_async_out72.gise
rm -rf ddr_vio_sync_async_out72.ise
rm -rf ddr_vio_sync_async_out72.xise
rm -rf ddr_vio_sync_async_out72_flist.txt
rm -rf ddr_vio_sync_async_out72_readme.txt
rm -rf ddr_vio_sync_async_out72.cdc
rm -rf ddr_vio_sync_async_out72_xdb
rm -rf ddr_vio_async_in_sync_out.asy
rm -rf ddr_vio_async_in_sync_out.ngc
rm -rf ddr_vio_async_in_sync_out.constraints
rm -rf ddr_vio_async_in_sync_out.ncf
rm -rf ddr_vio_async_in_sync_out.ucf
rm -rf ddr_vio_async_in_sync_out.xdc
rm -rf ddr_vio_async_in_sync_out.xco
rm -rf ddr_vio_async_in_sync_out_xmdf.tcl
rm -rf ddr_vio_async_in_sync_out.gise
rm -rf ddr_vio_async_in_sync_out.ise
rm -rf ddr_vio_async_in_sync_out.xise
rm -rf ddr_vio_async_in_sync_out_flist.txt
rm -rf ddr_vio_async_in_sync_out_readme.txt
rm -rf ddr_vio_async_in_sync_out.cdc
rm -rf ddr_vio_async_in_sync_out_xdb
# Files and folders generated by create ise
rm -rf test_xdb
rm -rf _xmsgs
rm -rf test.gise
rm -rf test.xise
rm -rf test.xise
# Files and folders generated by ISE through GUI mode
rm -rf _ngo
rm -rf xst
rm -rf example_top.cmd_log
rm -rf example_top.lso
rm -rf example_top.prj
rm -rf example_top.stx
rm -rf example_top.ut
rm -rf example_top.xst
rm -rf example_top_guide.ncd
rm -rf example_top_prev_built.ngd
rm -rf example_top_summary.html
rm -rf par_usage_statistics.html
rm -rf usage_statistics_webtalk.html
rm -rf webtalk.log
rm -rf device_usage_statistics.html
rm -rf test.ntrc_log
top/x300/coregen/ddr3_32bit/example_design/par/rem_files.tcl
+201
View File
@@ -0,0 +1,201 @@
##!/bin/csh -f
##****************************************************************************
## (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 1.8
## \ \ Application : MIG
## / / Filename : rem_files.tcl
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:13 $
## \ \ / \ Date Created : Fri Jan 27 2012
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Tcl file to remove files generated from PlanAhead
## Reference :
## Revision History :
##****************************************************************************
file delete -force coregen.cgp
file delete -force coregen.cgc
file delete -force coregen.log
# Files and folders generated Coregen ChipScope Modules
file delete -force ddr_icon.asy
file delete -force ddr_icon.ngc
file delete -force ddr_icon.xco
file delete -force ddr_icon_xmdf.tcl
file delete -force ddr_icon.gise
file delete -force ddr_icon.ise
file delete -force ddr_icon.xise
file delete -force ddr_icon_flist.txt
file delete -force ddr_icon_readme.txt
file delete -force ddr_icon.cdc
file delete -force ddr_icon_xdb
file delete -force ddr_ila_basic.asy
file delete -force ddr_ila_basic.ngc
file delete -force ddr_ila_basic.xco
file delete -force ddr_ila_basic_xmdf.tcl
file delete -force ddr_ila_basic.gise
file delete -force ddr_ila_basic.ise
file delete -force ddr_ila_basic.xise
file delete -force ddr_ila_basic_flist.txt
file delete -force ddr_ila_basic_readme.txt
file delete -force ddr_ila_basic.cdc
file delete -force ddr_ila_basic_xdb
file delete -force ddr_ila_wrpath.asy
file delete -force ddr_ila_wrpath.ngc
file delete -force ddr_ila_wrpath.xco
file delete -force ddr_ila_wrpath_xmdf.tcl
file delete -force ddr_ila_wrpath.gise
file delete -force ddr_ila_wrpath.ise
file delete -force ddr_ila_wrpath.xise
file delete -force ddr_ila_wrpath_flist.txt
file delete -force ddr_ila_wrpath_readme.txt
file delete -force ddr_ila_wrpath.cdc
file delete -force ddr_ila_wrpath_xdb
file delete -force ddr_ila_rdpath.asy
file delete -force ddr_ila_rdpath.ngc
file delete -force ddr_ila_rdpath.xco
file delete -force ddr_ila_rdpath_xmdf.tcl
file delete -force ddr_ila_rdpath.gise
file delete -force ddr_ila_rdpath.ise
file delete -force ddr_ila_rdpath.xise
file delete -force ddr_ila_rdpath_flist.txt
file delete -force ddr_ila_rdpath_readme.txt
file delete -force ddr_ila_rdpath.cdc
file delete -force ddr_ila_rdpath_xdb
file delete -force ddr_vio_sync_async_out72.asy
file delete -force ddr_vio_sync_async_out72.ngc
file delete -force ddr_vio_sync_async_out72.xco
file delete -force ddr_vio_sync_async_out72_xmdf.tcl
file delete -force ddr_vio_sync_async_out72.gise
file delete -force ddr_vio_sync_async_out72.ise
file delete -force ddr_vio_sync_async_out72.xise
file delete -force ddr_vio_sync_async_out72_flist.txt
file delete -force ddr_vio_sync_async_out72_readme.txt
file delete -force ddr_vio_sync_async_out72.cdc
file delete -force ddr_vio_sync_async_out72_xdb
file delete -force ddr_vio_async_in_sync_out.asy
file delete -force ddr_vio_async_in_sync_out.ngc
file delete -force ddr_vio_async_in_sync_out.xco
file delete -force ddr_vio_async_in_sync_out_xmdf.tcl
file delete -force ddr_vio_async_in_sync_out.gise
file delete -force ddr_vio_async_in_sync_out.ise
file delete -force ddr_vio_async_in_sync_out.xise
file delete -force ddr_vio_async_in_sync_out_flist.txt
file delete -force ddr_vio_async_in_sync_out_readme.txt
file delete -force ddr_vio_async_in_sync_out.cdc
file delete -force ddr_vio_async_in_sync_out_xdb
# Files and folders generated by planAhead & ISE
file delete -force example_top.bgn
file delete -force example_top.bit
file delete -force example_top.drc
file delete -force example_top.edf
file delete -force example_top.ncd
file delete -force example_top.pcf
file delete -force example_top.planahead.xdc
file delete -force example_top.routed.v
file delete -force example_top.sta
file delete -force example_top.v
file delete -force example_top_drc.txt
file delete -force proj1.ppr
file delete -force xilinx_device_details.xml
file delete -force .Xil
file delete -force proj1.data
file delete -force proj1.srcs
file delete -force ise_flow_results.txt
file delete -force xlnx_auto_0.ise
file delete -force example_top_vhdl.prj
file delete -force example_top.syr
file delete -force example_top.ngc
file delete -force example_top.ngr
file delete -force example_top_xst.xrpt
file delete -force example_top.bld
file delete -force example_top.ngd
file delete -force example_top_ngdbuild.xrpt
file delete -force example_top_map.map
file delete -force example_top_map.mrp
file delete -force example_top_map.ngm
file delete -force example_top.pcf
file delete -force example_top_map.ncd
file delete -force example_top_map.xrpt
file delete -force example_top_summary.xml
file delete -force example_top_usage.xml
file delete -force example_top.ncd
file delete -force example_top.par
file delete -force example_top.xpi
file delete -force smartpreview.twr
file delete -force example_top.ptwx
file delete -force example_top.pad
file delete -force example_top.unroutes
file delete -force example_top_pad.csv
file delete -force example_top_pad.txt
file delete -force example_top_par.xrpt
file delete -force example_top.twx
file delete -force example_top.twr
file delete -force example_top.drc
file delete -force example_top_bitgen.xwbt
file delete -force synthesis.log
file delete -force optimization.log
file delete -force place.log
file delete -force route.log
file delete -force bitgen.log
file delete -force post_synth.dcp
file delete -force post_optimize.dcp
file delete -force post_place.dcp
file delete -force post_route.dcp
top/x300/coregen/ddr3_32bit/example_design/par/set_ise_prop.tcl
+109
View File
@@ -0,0 +1,109 @@
project new test.xise
project set "Device Family" "kintex7"
project set "Device" "xc7k410t"
project set "Package" "ffg900"
project set "Speed Grade" "-2"
project set "Synthesis Tool" "XST (VHDL/Verilog)"
project set "Simulator" "ISim (VHDL/Verilog)"
xfile add "../rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v"
xfile add "../rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v"
xfile add "../rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v"
xfile add "../rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v"
xfile add "../rtl/traffic_gen/mig_7series_v1_8_tg.v"
xfile add "../rtl/example_top.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v"
xfile add "../../user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v"
xfile add "../../user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v"
xfile add "../../user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v"
xfile add "../../user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v"
xfile add "../../user_design/rtl/clocking/mig_7series_v1_8_tempmon.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_arb_mux.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_arb_select.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_common.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_compare.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_mach.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_queue.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_bank_state.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_col_mach.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_mc.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_rank_common.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_rank_mach.v"
xfile add "../../user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v"
xfile add "../../user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v"
xfile add "../../user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v"
xfile add "../../user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v"
xfile add "../../user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v"
xfile add "../../user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v"
xfile add "../../user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v"
xfile add "../../user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v"
xfile add "../../user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v"
xfile add "../../user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v"
xfile add "../../user_design/rtl/ui/mig_7series_v1_8_ui_top.v"
xfile add "../../user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v"
xfile add "../../user_design/rtl/ddr3_32bit.v"
xfile add "example_top.ucf"
project set "Library Search Order" "../synth/example_top.lso" -process "Synthesize - XST"
project close
top/x300/coregen/ddr3_32bit/example_design/par/vivado.tcl
+80
View File
@@ -0,0 +1,80 @@
#
# This is a common pa.tcl used by all designs used for hardware validation
#
# To remove all report and implementation files (if exist any on previous runs)
source rem_files.tcl
# Setup default values
set DEBUG_FILES 1
# Might not need in the future#
create_project proj1 . -force;
set_property design_mode RTL [get_property srcset [current_run]] ;# Set project type to RTL (as apposed to Netlist)
# Define some helpful variables, dirs, etc.
# All defines related to the design should be located in the app directory
set design example_top
set device xc7k410t-2-ffg900
#set constraints_file example_top.ucf
# Setup design sources and constraints
set readfile [open ../synth/example_top.prj r]
while {[gets $readfile line] >=0} {
set file_list [split $line " "]
if {[lindex $file_list 0] == "verilog"} {
read_verilog [lindex $file_list 2]
} else {
read_vhdl [lindex $file_list 2]
}
}
# Read the xdc constraints for the top-level file
set_property top ${design} [get_property srcset [current_run]]
import_files -fileset [get_filesets constrs_1] -force -norecurse {./example_top.xdc}
# Synthesize the design and create a post synthesis data check point
# Also create a port synthesis verilog netlist module
synth_design -part ${device} -top example_top >> synthesis.log;
write_checkpoint post_synth.dcp;
write_verilog ./${design}.v;
# Optimize the design and create a post optimization data check point
opt_design >> optimization.log;
write_checkpoint post_optimize.dcp;
# Place the design and create a post placement data check point
place_design >> place.log;
write_checkpoint post_place.dcp;
# Route the design and create a post routing data check point
route_design >> route.log;
write_checkpoint post_route.dcp;
# Create a static timing analysis report
report_timing -delay_type min_max -sort_by group -max_paths 3 -input_pins -file ${design}.sta;
# Mandatory outputs
report_drc;
if {[report_drc -file example_top_drc.txt -rules {ADEF}]} {
puts "ERROR -- report_drc bad return status -- should only find warnings"
exit 1
}
write_bitstream -file ${design}.bit >> bitgen.log;
# Optional 'debug' outputs
if {$DEBUG_FILES} {
write_edf ./${design}.edf;
write_verilog ./${design}.routed.v;
write_xdc ./${design}.planahead.xdc;
write_ncd -file ${design}.ncd
write_pcf -file ${design}.pcf
}
close_project -delete;
top/x300/coregen/ddr3_32bit/example_design/par/vivado_gui.tcl
+5
View File
@@ -0,0 +1,5 @@
add_files ../rtl
set_property target_constrs_file example_top.xdc [current_fileset -constrset]
top/x300/coregen/ddr3_32bit/example_design/par/xlnx_auto_0_xdb/cst.xbcd
BIN
View File
Binary file not shown.
top/x300/coregen/ddr3_32bit/example_design/par/xst_options.txt
+9
View File
@@ -0,0 +1,9 @@
set -tmpdir ../synth/__projnav
set -xsthdpdir ..\synth\xst
run
-ifn ../synth/example_top.prj
-ofn example_top
-p xc7k410t-2-ffg900
-top example_top
-lso ../synth/example_top.lso
quit
top/x300/coregen/ddr3_32bit/example_design/rtl/example_top.v
+1091
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v
Executable
+405
View File
@@ -0,0 +1,405 @@
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: axi4_wrapper.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module is wrapper for converting the reads and writes to transactions
// that follow the AXI protocol.
//
//Reference:
//Revision History:
//*****************************************************************************
module mig_7series_v1_8_axi4_tg #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_EN_WRAP_TRANS = 0, // Set 1 to enable wrap transactions
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter DBG_WR_STS_WIDTH = 32,
parameter DBG_RD_STS_WIDTH = 32,
parameter ENFORCE_RD_WR = 0,
parameter ENFORCE_RD_WR_CMD = 8'h11,
parameter EN_UPSIZER = 0,
parameter ENFORCE_RD_WR_PATTERN = 3'b000
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// Input control signals
input init_cmptd, // Initialization completed
input init_test, // Initialize the test
input wdog_mask, // Mask the watchdog timeouts
input wrap_en, // Enable wrap transactions
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output axi_rd_rready, // Read Response ready
// Error status signals
output cmd_err, // Error during command phase
output data_msmatch_err, // Data mismatch
output write_err, // Write error occured
output read_err, // Read error occured
output test_cmptd, // Data pattern test completed
output write_cmptd, // Write test completed
output read_cmptd, // Read test completed
output reg cmptd_one_wr_rd, // Completed atleast one write
// and read
// Debug status signals
output dbg_wr_sts_vld, // Write debug status valid,
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
output dbg_rd_sts_vld, // Read debug status valid
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
);
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
localparam CTL_SIG_WIDTH = 3; // Control signal width
localparam RD_STS_WIDTH = 16; // Read port status signal width
localparam WDG_TIMER_WIDTH = 11;
localparam WR_STS_WIDTH = 16; // Write port status signal width
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
wire cmd_en;
wire [2:0] cmd;
wire [7:0] blen;
wire [31:0] addr;
wire [CTL_SIG_WIDTH-1:0] ctl;
wire cmd_ack;
// User interface write ports
wire wrdata_vld;
wire [C_AXI_DATA_WIDTH-1:0] wrdata;
wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
wire wrdata_cmptd;
wire wrdata_rdy;
wire wrdata_sts_vld;
wire [WR_STS_WIDTH-1:0] wrdata_sts;
// User interface read ports
wire rddata_rdy;
wire rddata_vld;
wire [C_AXI_DATA_WIDTH-1:0] rddata;
wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
wire rddata_cmptd;
wire [RD_STS_WIDTH-1:0] rddata_sts;
reg cmptd_one_wr;
reg cmptd_one_rd;
//*****************************************************************************
// AXI4 wrapper instance
//*****************************************************************************
mig_7series_v1_8_axi4_wrapper #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
.C_END_ADDRESS (C_END_ADDRESS),
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
.WR_STS_WIDTH (WR_STS_WIDTH),
.RD_STS_WIDTH (RD_STS_WIDTH),
.EN_UPSIZER (EN_UPSIZER),
.WDG_TIMER_WIDTH (WDG_TIMER_WIDTH)
) axi4_wrapper_inst
(
.aclk (aclk),
.aresetn (aresetn),
// User interface command port
.cmd_en (cmd_en),
.cmd (cmd),
.blen (blen),
.addr (addr),
.ctl (ctl),
.wdog_mask (wdog_mask),
.cmd_ack (cmd_ack),
// User interface write ports
.wrdata_vld (wrdata_vld),
.wrdata (wrdata),
.wrdata_bvld (wrdata_bvld),
.wrdata_cmptd (wrdata_cmptd),
.wrdata_rdy (wrdata_rdy),
.wrdata_sts_vld (wrdata_sts_vld),
.wrdata_sts (wrdata_sts),
// User interface read ports
.rddata_rdy (rddata_rdy),
.rddata_vld (rddata_vld),
.rddata (rddata),
.rddata_bvld (rddata_bvld),
.rddata_cmptd (rddata_cmptd),
.rddata_sts (rddata_sts),
// AXI write address channel signals
.axi_wready (axi_wready),
.axi_wid (axi_wid),
.axi_waddr (axi_waddr),
.axi_wlen (axi_wlen),
.axi_wsize (axi_wsize),
.axi_wburst (axi_wburst),
.axi_wlock (axi_wlock),
.axi_wcache (axi_wcache),
.axi_wprot (axi_wprot),
.axi_wvalid (axi_wvalid),
// AXI write data channel signals
.axi_wd_wready (axi_wd_wready),
.axi_wd_wid (axi_wd_wid),
.axi_wd_data (axi_wd_data),
.axi_wd_strb (axi_wd_strb),
.axi_wd_last (axi_wd_last),
.axi_wd_valid (axi_wd_valid),
// AXI write response channel signals
.axi_wd_bid (axi_wd_bid),
.axi_wd_bresp (axi_wd_bresp),
.axi_wd_bvalid (axi_wd_bvalid),
.axi_wd_bready (axi_wd_bready),
// AXI read address channel signals
.axi_rready (axi_rready),
.axi_rid (axi_rid),
.axi_raddr (axi_raddr),
.axi_rlen (axi_rlen),
.axi_rsize (axi_rsize),
.axi_rburst (axi_rburst),
.axi_rlock (axi_rlock),
.axi_rcache (axi_rcache),
.axi_rprot (axi_rprot),
.axi_rvalid (axi_rvalid),
// AXI read data channel signals
.axi_rd_bid (axi_rd_bid),
.axi_rd_rresp (axi_rd_rresp),
.axi_rd_rvalid (axi_rd_rvalid),
.axi_rd_data (axi_rd_data),
.axi_rd_last (axi_rd_last),
.axi_rd_rready (axi_rd_rready)
);
//*****************************************************************************
// Traffic Generator instance
//*****************************************************************************
mig_7series_v1_8_tg #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
.C_END_ADDRESS (C_END_ADDRESS),
.C_EN_WRAP_TRANS (C_EN_WRAP_TRANS),
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
.WR_STS_WIDTH (WR_STS_WIDTH),
.RD_STS_WIDTH (RD_STS_WIDTH),
.DBG_WR_STS_WIDTH (DBG_WR_STS_WIDTH),
.DBG_RD_STS_WIDTH (DBG_RD_STS_WIDTH),
.ENFORCE_RD_WR (ENFORCE_RD_WR),
.ENFORCE_RD_WR_CMD (ENFORCE_RD_WR_CMD),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.ENFORCE_RD_WR_PATTERN (ENFORCE_RD_WR_PATTERN)
) traffic_gen_inst
(
.clk (aclk),
.resetn (aresetn),
// Input start signals
.init_cmptd (init_cmptd),
.init_test (init_test),
.wrap_en (wrap_en),
// Control ports
.cmd_ack (cmd_ack),
.cmd_en (cmd_en),
.cmd (cmd),
.blen (blen),
.addr (addr),
.ctl (ctl),
// Write port
.wdata_rdy (wrdata_rdy),
.wdata_vld (wrdata_vld),
.wdata_cmptd (wrdata_cmptd),
.wdata (wrdata),
.wdata_bvld (wrdata_bvld),
.wdata_sts_vld (wrdata_sts_vld),
.wdata_sts (wrdata_sts),
// Read Port
.rdata_vld (rddata_vld),
.rdata (rddata),
.rdata_bvld (rddata_bvld),
.rdata_cmptd (rddata_cmptd),
.rdata_sts (rddata_sts),
.rdata_rdy (rddata_rdy),
// Error status signals
.cmd_err (cmd_err),
.data_msmatch_err (data_msmatch_err),
.write_err (write_err),
.read_err (read_err),
.test_cmptd (test_cmptd),
.write_cmptd (write_cmptd),
.read_cmptd (read_cmptd),
// Debug status signals
.dbg_wr_sts_vld (dbg_wr_sts_vld),
.dbg_wr_sts (dbg_wr_sts),
.dbg_rd_sts_vld (dbg_rd_sts_vld),
.dbg_rd_sts (dbg_rd_sts)
);
always @(posedge aclk)
if (!aresetn)
cmptd_one_wr <= 1'b0;
else if (write_cmptd)
cmptd_one_wr <= 1'b1;
always @(posedge aclk)
if (!aresetn)
cmptd_one_rd <= 1'b0;
else if (read_cmptd)
cmptd_one_rd <= 1'b1;
always @(posedge aclk)
if (!aresetn)
cmptd_one_wr_rd <= 1'b0;
else if (cmptd_one_wr & cmptd_one_rd)
cmptd_one_wr_rd <= 1'b1;
endmodule
top/x300/coregen/ddr3_32bit/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v
Executable
+868
View File
@@ -0,0 +1,868 @@
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: axi4_wrapper.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module is wrapper for converting the reads and writes to transactions
// that follow the AXI4 protocol.
//
//Reference:
//Revision History:
//*****************************************************************************
module mig_7series_v1_8_axi4_wrapper #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter CTL_SIG_WIDTH = 2, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter EN_UPSIZER = 0, // There is no upsizer code
parameter WDG_TIMER_WIDTH = 9
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// User interface command port
input cmd_en, // Asserted to indicate a valid command
// and address
input [2:0] cmd, // Write or read command
// 000 - READ with INCR bursts
// 001 - READ with WRAP bursts
// 01x - Reserved
// 100 - WRITE with INCR bursts
// 101 - WRITE with WRAP bursts
input [7:0] blen, // Burst length calculated as blen+1
input [31:0] addr, // Address for the read or the write
// transaction
input [CTL_SIG_WIDTH-1:0] ctl, // control command for read or write
// transaction
input wdog_mask, // Mask the watchdog timeouts
output cmd_ack,// Indicates the command has been accepted
// User interface write ports
input wrdata_vld, // Asserted to indicate a valid write
// data
input [C_AXI_DATA_WIDTH-1:0] wrdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld, // Byte valids for the write data
input wrdata_cmptd,// Last data to be transferred
output reg wrdata_rdy, // Indicates that the write data is
// ready to be accepted
output reg wrdata_sts_vld, // Indicates a write status after
// completion of a write transfer
output [WR_STS_WIDTH-1:0] wrdata_sts, // Status of the write transaction
// User interface read ports
input rddata_rdy, // Data ready to be accepted
output reg rddata_vld, // Indicates a valid read data available
output reg [C_AXI_DATA_WIDTH-1:0] rddata, // Read data
output [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld, // Byte valids for read data
output reg rddata_cmptd, // Indicates last data present and
// valid status
output [RD_STS_WIDTH-1:0] rddata_sts, // Status of the read transaction
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
// write address
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output reg axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output reg [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output reg axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output reg axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output reg axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output reg axi_rd_rready // Read Response ready
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] AXI_WRIDLE = 9'd0,
AXI_WRCTL = 9'd1,
AXI_WRRDY = 9'd2,
AXI_WRDAT = 9'd3,
AXI_WRDAT_WT = 9'd4,
AXI_WRDAT_LST = 9'd5,
AXI_WRDAT_DMY = 9'd6,
AXI_WRRESP_WT = 9'd7,
AXI_WRTO = 9'd8;
parameter [5:0] AXI_RDIDLE = 6'd0,
AXI_RDCTL = 6'd1,
AXI_RDDAT = 6'd2,
AXI_RDDAT_LST = 6'd3,
AXI_RDDAT_WT = 6'd4,
AXI_RDTO = 6'd5;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg wrap_w;
reg [7:0] blen_w;
reg [7:0] blen_w_minus_1;
reg [C_AXI_ADDR_WIDTH-1:0] addr_w;
reg [CTL_SIG_WIDTH-1:0] ctl_w;
reg wrap_r;
reg [7:0] blen_r;
reg [C_AXI_ADDR_WIDTH-1:0] addr_r;
reg [CTL_SIG_WIDTH-1:0] ctl_r;
reg [8:0] wstate;
reg [8:0] next_wstate;
reg wr_cmd_start;
reg [WDG_TIMER_WIDTH-1:0] wr_wdog_cntr;
reg wrdata_vld_r;
reg wrdata_cmptd_r;
reg [7:0] wr_len_cntr;
reg [7:0] rd_len_cntr;
reg [7:0] blen_cntr;
reg [3:0] wr_cntr;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r1;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r2;
reg wrdata_mux_ctrl;
reg [2:0] wrdata_fsm_sts;
reg [3:0] brespid_r;
reg [1:0] bresp_r;
reg [5:0] rstate;
reg [5:0] next_rstate;
reg [WDG_TIMER_WIDTH-1:0] rd_wdog_cntr;
reg rd_cmd_start;
reg rlast;
reg [3:0] rd_cntr;
reg rddata_ppld;
reg [C_AXI_DATA_WIDTH-1:0] rddata_p1;
reg err_resp;
reg [1:0] rddata_fsm_sts;
reg rrid_err;
reg pending_one_trans;
reg axi_wready_l;
wire wr_cmd_timeout;
wire wr_done;
wire wr_last;
wire rd_cmd_timeout;
//*****************************************************************************
// Address and control register logic
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn) begin
wrap_w <= 1'b0;
blen_w <= 8'h0;
blen_w_minus_1 <= 8'h0;
addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_w <= {CTL_SIG_WIDTH{1'b0}};
end
else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] &
cmd_en & cmd[2]) begin
wrap_w <= cmd[0];
blen_w <= blen;
blen_w_minus_1 <= blen - 8'h01;
addr_w <= addr;
ctl_w <= ctl;
end
end
always @(posedge aclk) begin
if (!aresetn) begin
wrap_r <= 1'b0;
blen_r <= 8'h0;
addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_r <= {CTL_SIG_WIDTH{1'b0}};
end
else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] &
cmd_en & !cmd[2]) begin
wrap_r <= cmd[0];
blen_r <= blen;
addr_r <= addr;
ctl_r <= ctl;
end
end
assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
(rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
//*****************************************************************************
// Write data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cmd_start <= 1'b0;
else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
wr_cmd_start <= 1'b1;
else if (wstate[AXI_WRCTL])
wr_cmd_start <= 1'b0;
always @(posedge aclk)
if (wstate[AXI_WRIDLE] |
(axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
(axi_wd_bvalid & wstate[AXI_WRRESP_WT]))
wr_wdog_cntr <= 'h0;
else if (!wstate[AXI_WRTO] & !wdog_mask)
wr_wdog_cntr <= wr_wdog_cntr + 'h1;
always @(posedge aclk)
wrdata_vld_r <= wrdata_vld;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_cmptd_r <= 1'b0;
else if (wrdata_cmptd & wrdata_vld)
wrdata_cmptd_r <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
blen_cntr <= 8'h0;
else if (wrdata_vld & wrdata_rdy)
blen_cntr <= blen_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
pending_one_trans <= 1'b0;
else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
pending_one_trans <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
pending_one_trans <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wr_len_cntr <= 8'h0;
else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) &
axi_wd_valid & axi_wd_wready)
wr_len_cntr <= wr_len_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wready_l <= 1'b0;
else if (axi_wready)
axi_wready_l <= 1'b1;
assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
assign wr_last = (wr_len_cntr >= blen_w_minus_1);
assign wr_done = (blen_cntr >= blen_w);
//*****************************************************************************
// Write data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
wstate <= 9'h1;
else
wstate <= next_wstate;
end
always @(*) begin
next_wstate = 9'h0;
case (1'b1)
wstate[AXI_WRIDLE]: begin // 9'h001
if (wr_cmd_start)
next_wstate[AXI_WRCTL] = 1'b1;
else
next_wstate[AXI_WRIDLE] = 1'b1;
end
wstate[AXI_WRCTL]: begin // 9'h002
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wvalid)
next_wstate[AXI_WRRDY] = 1'b1;
else
next_wstate[AXI_WRCTL] = 1'b1;
end
wstate[AXI_WRRDY]: begin // 9'h004
if (wrdata_cmptd_r & wrdata_rdy)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (wrdata_vld_r & wrdata_rdy)
next_wstate[AXI_WRDAT] = 1'b1;
else
next_wstate[AXI_WRRDY] = 1'b1;
end
wstate[AXI_WRDAT]: begin // 9'h008
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else if (!axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
wstate[AXI_WRDAT_WT]: begin // 9'h010
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready) begin
if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!pending_one_trans & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
else
next_wstate[AXI_WRDAT_WT] = 1'b1;
end
wstate[AXI_WRDAT_LST]: begin // 9'h020
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_valid & axi_wd_wready)
next_wstate[AXI_WRRESP_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_LST] = 1'b1;
end
wstate[AXI_WRDAT_DMY]: begin // 9'h040
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (wrdata_cmptd_r & wr_last)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!wr_last & !axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_DMY] = 1'b1;
end
wstate[AXI_WRRESP_WT]: begin // 9'h080
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_bvalid &
(EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
next_wstate[AXI_WRIDLE] = 1'b1;
else
next_wstate[AXI_WRRESP_WT] = 1'b1;
end
wstate[AXI_WRTO]: begin // 9'h100
next_wstate[AXI_WRIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Write channel control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cntr <= 4'h0;
else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
wr_cntr <= wr_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_wvalid <= 1'b0;
else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
(axi_wready & !wstate[AXI_WRCTL]))
axi_wvalid <= 1'b0;
else if (wstate[AXI_WRCTL])
axi_wvalid <= 1'b1;
assign awid = wr_cntr;
assign axi_waddr = addr_w;
assign axi_wid = wr_cntr;
assign axi_wlen = blen_w;
assign axi_wburst = {1'b0, wrap_w} + 2'b01;
assign axi_wsize = ctl_w[2:0];
// Not supported and hence assigned zeros
assign axi_wlock = 2'b0;
assign axi_wcache = 4'b0;
assign axi_wprot = 3'b0;
//*****************************************************************************
// Write channel data signals
//*****************************************************************************
always @(posedge aclk) begin
if (wstate[AXI_WRIDLE]) begin
wrdata_r1 <= 'h0;
wrdata_r2 <= 'h0;
end
else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] |
wstate[AXI_WRDAT_LST])) begin
wrdata_r1 <= wrdata;
wrdata_r2 <= wrdata_r1;
end
end
always @(posedge aclk)
if (!aresetn)
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT] |
(wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT]))
wrdata_rdy <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_sts_vld <= 1'b0;
else if (wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b0;
else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_mux_ctrl <= 1'b0;
else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
wstate[AXI_WRIDLE])
wrdata_mux_ctrl <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
wrdata_mux_ctrl <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_wd_last <= 1'b0;
else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
axi_wd_last <= 1'b0;
else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT_LST])
axi_wd_last <= 1'b1;
generate
begin: data_axi_wr
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_data <= 'h0;
else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl)
axi_wd_data <= wrdata_r2;
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
axi_wd_data <= wrdata_r1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT]))) |
(next_wstate[AXI_WRDAT_LST] & !axi_wd_wready &
(wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) |
((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) |
(wstate[AXI_WRDAT_WT]))
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
else
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
end
end
endgenerate
assign axi_wd_wid = wr_cntr;
assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
//*****************************************************************************
// Write response and status signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
axi_wd_bready <= 1'b0;
else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b0;
else if (wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_fsm_sts <= 3'b000;
else begin
if (next_wstate[AXI_WRTO]) begin
if (wstate[AXI_WRDAT])
wrdata_fsm_sts <= 3'b001;
else if (wstate[AXI_WRDAT_WT])
wrdata_fsm_sts <= 3'b010;
else if (wstate[AXI_WRDAT_DMY])
wrdata_fsm_sts <= 3'b011;
else if (wstate[AXI_WRRESP_WT])
wrdata_fsm_sts <= 3'b100;
end
end
always @(posedge aclk)
if (wstate[AXI_WRIDLE]) begin
brespid_r <= 4'h0;
bresp_r <= 2'b00;
end
else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
brespid_r <= axi_wd_bid;
bresp_r <= axi_wd_bresp;
end
assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r};
//*****************************************************************************
// Read data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid)
rd_wdog_cntr <= 'h0;
else if (!rstate[AXI_RDTO])
rd_wdog_cntr <= rd_wdog_cntr + 'h1;
always @(posedge aclk)
if (!aresetn)
rd_cmd_start <= 1'b0;
else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
rd_cmd_start <= 1'b1;
else if (rstate[AXI_RDCTL])
rd_cmd_start <= 1'b0;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rlast <= 1'b0;
else if (axi_rd_last & axi_rd_rvalid)
rlast <= 1'b1;
assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
//*****************************************************************************
// Read data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
rstate <= 6'h1;
else
rstate <= next_rstate;
end
always @(*) begin
next_rstate = 6'h0;
case (1'b1)
rstate[AXI_RDIDLE]: begin // 6'h01
if (rd_cmd_start)
next_rstate[AXI_RDCTL] = 1'b1;
else
next_rstate[AXI_RDIDLE] = 1'b1;
end
rstate[AXI_RDCTL]: begin // 6'h02
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (axi_rready & axi_rvalid) begin
if (rddata_rdy)
next_rstate[AXI_RDDAT] = 1'b1;
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
else
next_rstate[AXI_RDCTL] = 1'b1;
end
rstate[AXI_RDDAT]: begin // 6'h04
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDDAT_LST]: begin // 6'h08
if (rddata_cmptd & rddata_vld & rddata_rdy)
next_rstate[AXI_RDIDLE] = 1'b1;
else
next_rstate[AXI_RDDAT_LST] = 1'b1;
end
rstate[AXI_RDDAT_WT]: begin // 6'h10
if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDTO]: begin // 6'h20
next_rstate[AXI_RDIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Read Address control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rd_cntr <= 4'h0;
else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
rd_cntr <= rd_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL])
axi_rvalid <= 1'b1;
assign axi_rid = rd_cntr;
generate
begin: addr_axi_rd
if (C_AXI_DATA_WIDTH == 256)
assign axi_raddr = {addr_r[31:5], 5'b0};
else if (C_AXI_DATA_WIDTH == 128)
assign axi_raddr = {addr_r[31:4], 4'b0};
else if (C_AXI_DATA_WIDTH == 64)
assign axi_raddr = {addr_r[31:3], 3'b0};
else
assign axi_raddr = {addr_r[31:2], 2'b0};
end
endgenerate
assign axi_rlen = blen_r;
assign axi_rburst = {1'b0, wrap_r} + 2'b01;
assign axi_rsize = ctl_r[2:0];
// Not supported and hence assigned zeros
assign axi_rlock = 2'b0;
assign axi_rcache = 4'b0;
assign axi_rprot = 3'b0;
//*****************************************************************************
// Read channel data signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rddata_vld <= 1'b0;
else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
(rddata_rdy & rstate[AXI_RDDAT_LST]) |
(rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) |
(rddata_rdy & axi_rd_rvalid & axi_rd_last) |
rstate[AXI_RDIDLE])
rddata_vld <= 1'b0;
else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
rddata_ppld <= 1'b0;
else if (rddata_vld & rddata_rdy)
rddata_ppld <= 1'b0;
else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
rddata_ppld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_rd_rready <= 1'b0;
else if (rstate[AXI_RDIDLE] |
(rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
(rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
(next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
axi_rd_rready <= 1'b0;
else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
(next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
(rstate[AXI_RDDAT_WT] & !rddata_ppld) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
axi_rd_rready <= 1'b1;
always @(posedge aclk)
if (axi_rd_rvalid)
rddata_p1 <= axi_rd_data;
generate
begin: data_axi_rd
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (axi_rd_rvalid & !rddata_ppld)
rddata <= axi_rd_data;
else if (rddata_rdy & rddata_vld & rddata_ppld)
rddata <= rddata_p1;
assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
always @(posedge aclk)
if (!aresetn)
rddata_cmptd <= 1'b0;
else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
rstate[AXI_RDIDLE])
rddata_cmptd <= 1'b0;
else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_cmptd <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
err_resp <= 1'b0;
else if (axi_rd_rvalid & axi_rd_rresp[1])
err_resp <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rddata_fsm_sts <= 2'b00;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b01;
else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b10;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rrid_err <= 1'b0;
else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
rrid_err <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rd_len_cntr <= 8'h0;
else if (axi_rd_rvalid & axi_rd_rready)
rd_len_cntr <= rd_len_cntr + 8'h01;
assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp};
// synthesis translate_off
always @(posedge aclk) begin
if (rd_cmd_timeout)
$display ("ERR: Read timeout occured at time %t", $time);
if (wr_cmd_timeout)
$display ("ERR: Write timeout occured at time %t", $time);
end
// synthesis translate_on
endmodule
top/x300/coregen/ddr3_32bit/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v
Executable
+250
View File
@@ -0,0 +1,250 @@
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_8_cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
assign prbs_o = prbs;
endmodule
top/x300/coregen/ddr3_32bit/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v
Executable
+188
View File
@@ -0,0 +1,188 @@
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_gen_chk.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex6/Spartan6/7series
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison. This always
// generates 32-bit data only. This also checks the received
// data
//Reference:
//Revision History:
//*****************************************************************************
module mig_7series_v1_8_data_gen_chk # (
parameter C_AXI_DATA_WIDTH = 32 // Width of the AXI write and read data
)
(
input clk,
input data_en,
input [2:0] data_pattern,
input pattern_init, // when high the patterns are initialized
input [31:0] prbs_seed_i,
input [C_AXI_DATA_WIDTH-1:0] rdata,
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld,
input rdata_vld,
input wrd_cntr_rst,
output msmatch_err, // Indicates there is a mismatch error
output reg [7:0] wrd_cntr, // Word count output
output reg [31:0] data_o // generated data
);
reg [31:0] prbs;
reg [32:1] lfsr_q;
reg [31:0] walk0;
wire [31:0] walk1;
reg [C_AXI_DATA_WIDTH/32-1:0] msmatch_err_sig;
//*****************************************************************************
// Data generate segment
//*****************************************************************************
always @ (posedge clk) begin
if (pattern_init) begin
lfsr_q <= {prbs_seed_i + 32'h55555555};
end
else if (data_en) begin
lfsr_q[32:9] <= lfsr_q[31:8];
lfsr_q[8] <= lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= lfsr_q[5:3];
lfsr_q[3] <= lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= lfsr_q[1] ;
lfsr_q[1] <= lfsr_q[32];
end
end
always @(posedge clk)
if (pattern_init)
walk0 <= 32'hFFFF_FFFE;
else if (data_en)
walk0 <= walk0 << 1;
assign walk1 = ~walk0;
always @(*) begin
prbs = lfsr_q[32:1];
end
always @(*) begin
case (data_pattern)
3'b001: data_o = prbs; // PRBS pattern
3'b010: data_o = walk0; // Walking zeros
3'b011: data_o = walk1; // Walking ones
3'b100: data_o = 32'hFFFF_FFFF; // All ones
3'b101: data_o = 32'h0000_0000; // All zeros
default: data_o = 32'h5A5A_A5A5;
endcase
end
//*****************************************************************************
// Data check segment
//*****************************************************************************
always @(posedge clk)
if (wrd_cntr_rst)
wrd_cntr <= 8'h00;
else if (rdata_vld & !msmatch_err)
wrd_cntr <= wrd_cntr + 8'h01;
genvar i;
generate
begin: data_check
for (i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1) begin: gen_data_check
always @(posedge clk)
if (wrd_cntr_rst)
msmatch_err_sig[i] <= 1'b0;
else if (rdata_vld &
((rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) |
(rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) |
(rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) |
(rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3])))
msmatch_err_sig[i] <= 1'b1;
else
msmatch_err_sig[i] <= 1'b0;
end
end
endgenerate
assign msmatch_err = |msmatch_err_sig;
// synthesis translate_off
//*****************************************************************************
// Simulation debug signals and messages
//*****************************************************************************
always @(posedge clk) begin
if (rdata_vld & ({{C_AXI_DATA_WIDTH/32}{data_o}} !== rdata)) begin
$display ("[ERROR] : Written data and read data does not match");
$display ("Data written : %h", {{C_AXI_DATA_WIDTH/32}{data_o}});
$display ("Data read : %h", rdata);
$display ("Word number : %h", wrd_cntr);
$display ("Simulation time : %t", $time);
end
end
// synthesis translate_on
endmodule
top/x300/coregen/ddr3_32bit/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v
Executable
+735
View File
@@ -0,0 +1,735 @@
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: tg.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module generates and checks the AXI traffic
//
//Reference:
//Revision History:
//*****************************************************************************
module mig_7series_v1_8_tg #(
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 32'h0, // Start address of the address map
parameter C_END_ADDRESS = 32'h0000_00FF, // End address of the address map
parameter C_EN_WRAP_TRANS = 0, // Should be set to 1 for wrap transactions
parameter CTL_SIG_WIDTH = 3, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter DBG_WR_STS_WIDTH = 32,
parameter DBG_RD_STS_WIDTH = 32,
parameter ENFORCE_RD_WR = 0,
parameter ENFORCE_RD_WR_CMD = 8'h11,
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter ENFORCE_RD_WR_PATTERN = 3'b000
)
(
input clk, // input clock
input resetn, // Active low reset signal
// Input start signals
input init_cmptd, // Initialization completed
input init_test, // Initialize the test
input wrap_en, // Enable wrap transactions
// Control ports
input cmd_ack, // Command has been accepted
output reg cmd_en, // Command enable
output [2:0] cmd, // Command
output reg [7:0] blen, // Length of the burst
output reg [31:0] addr, // output address
output [CTL_SIG_WIDTH-1:0] ctl, // Control signal
// Write port
input wdata_rdy, // Write data ready to be accepted
output wdata_vld, // Write data valid
output reg wdata_cmptd, // Write data completed
output [C_AXI_DATA_WIDTH-1:0] wdata, // Write data
output [C_AXI_DATA_WIDTH/8-1:0] wdata_bvld, // Byte valids
input wdata_sts_vld, // Status valid
input [WR_STS_WIDTH-1:0] wdata_sts, // Write status
// Read Port
input rdata_vld, // Read data valid
input [C_AXI_DATA_WIDTH-1:0] rdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld, // Byte valids
input rdata_cmptd, // Read data completed
input [RD_STS_WIDTH-1:0] rdata_sts, // Read status
output rdata_rdy, // Read data ready
// Error status signals
output reg cmd_err, // Error during command phase
output reg data_msmatch_err, // Data mismatch
output reg write_err, // Write error occured
output reg read_err, // Read error occured
output test_cmptd, // Completed testing with all patterns
output write_cmptd, // Completed write operation
output read_cmptd, // Completed write operation
// Debug status signals
output reg dbg_wr_sts_vld, // Write debug status valid,
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
output reg dbg_rd_sts_vld, // Read debug status valid
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] TG_IDLE = 8'd0,
TG_GEN_PRBS = 8'd1,
TG_WR_CMD = 8'd2,
TG_WR_DATA = 8'd3,
TG_WR_DONE = 8'd4,
TG_RD_CMD = 8'd5,
TG_RD_DATA = 8'd6,
TG_UPDT_CNTR = 8'd7;
//*****************************************************************************
// Internal wire and reg declarations
//*****************************************************************************
wire [2:0] data_pattern;
wire dgen_en;
wire dgen_init;
wire [31:0] prbs_seed;
wire msmatch_err;
wire [31:0] prbs_data;
wire [31:0] prbs_blen;
wire [7:0] prbs_blen_mdfy;
wire [31:0] prbs_addr;
wire [31:0] prbs_addr_mdfy;
wire cmd_gen_csr_sig;
wire rdata_sig_vld;
wire [7:0] wrd_cntr;
wire wrd_cntr_rst;
wire w_burst_4;
wire w_burst_8;
wire w_burst_16;
reg [7:0] tg_state;
reg [7:0] next_tg_state;
reg [2:0] shft_cntr;
reg [2:0] seed_cntr;
reg cmd_vld;
reg [7:0] blen_cntr;
reg wr_proc;
reg curr_wr_ptr;
reg curr_rd_ptr;
reg [31:0] curr_addr1;
reg [31:0] curr_addr2;
reg [7:0] curr_blen1;
reg [7:0] curr_blen2;
reg cmd_wr_en;
reg cmd_wr_en_r;
reg cmd_rd_en;
reg [7:0] cmd_gen_csr;
reg cmd_err_dbg;
reg data_msmatch_err_dbg;
reg write_err_dbg;
reg read_err_dbg;
reg [WR_STS_WIDTH-1:0] wdata_sts_r; // Write status registered
reg [RD_STS_WIDTH-1:0] rdata_sts_r; // Read status registered
//*****************************************************************************
// FSM Control Block
//*****************************************************************************
always @(posedge clk) begin
if (!resetn | init_test)
tg_state <= 8'h1;
else
tg_state <= next_tg_state;
end
always @(*) begin
next_tg_state = 8'h0;
case (1'b1)
tg_state[TG_IDLE]: begin // 8'h01
if (init_cmptd)
next_tg_state[TG_GEN_PRBS] = 1'b1;
else
next_tg_state[TG_IDLE] = 1'b1;
end
tg_state[TG_GEN_PRBS]: begin // 8'h02
if (cmd_vld) begin
if (cmd_gen_csr_sig)
next_tg_state[TG_WR_CMD] = 1'b1;
else
next_tg_state[TG_RD_CMD] = 1'b1;
end else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
tg_state[TG_WR_CMD]: begin // 8'h04
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (wdata_rdy)
next_tg_state[TG_WR_DATA] = 1'b1;
else
next_tg_state[TG_WR_CMD] = 1'b1;
end
tg_state[TG_WR_DATA]: begin // 8'h08
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (blen_cntr == 8'h0 & wdata_rdy)
next_tg_state[TG_WR_DONE] = 1'b1;
else
next_tg_state[TG_WR_DATA] = 1'b1;
end
tg_state[TG_WR_DONE]: begin // 8'h10
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else
next_tg_state[TG_WR_DONE] = 1'b1;
end
tg_state[TG_RD_CMD]: begin // 8'h20
if (rdata_cmptd) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (cmd_ack)
next_tg_state[TG_RD_DATA] = 1'b1;
else
next_tg_state[TG_RD_CMD] = 1'b1;
end
tg_state[TG_RD_DATA]: begin // 8'h040
if (rdata_cmptd & rdata_vld & rdata_rdy) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else
next_tg_state[TG_RD_DATA] = 1'b1;
end
tg_state[TG_UPDT_CNTR]: begin // 8'h80
if (&seed_cntr)
next_tg_state[TG_IDLE] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
endcase
end
//*****************************************************************************
// Control Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
cmd_wr_en <= 1'b0;
else if (next_tg_state[TG_WR_CMD] & tg_state[TG_GEN_PRBS])
cmd_wr_en <= 1'b1;
else
cmd_wr_en <= 1'b0;
end
always @(posedge clk) begin
if (!resetn)
cmd_rd_en <= 1'b0;
else if (next_tg_state[TG_RD_CMD] & tg_state[TG_GEN_PRBS])
cmd_rd_en <= 1'b1;
else
cmd_rd_en <= 1'b0;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
curr_wr_ptr <= 1'b0;
else if (cmd_wr_en)
curr_wr_ptr <= ~curr_wr_ptr;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
curr_rd_ptr <= 1'b0;
else if (cmd_rd_en)
curr_rd_ptr <= ~curr_rd_ptr;
end
always @(posedge clk) begin
if (!resetn)
cmd_vld <= 1'b0;
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
cmd_vld <= 1'b0;
else if (tg_state[TG_GEN_PRBS])
cmd_vld <= 1'b1;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE])
wr_proc <= 1'b0;
else if (cmd_wr_en)
wr_proc <= 1'b1;
else if (cmd_rd_en)
wr_proc <= 1'b0;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
shft_cntr <= 3'b000;
else if (tg_state[TG_GEN_PRBS] & (next_tg_state[TG_WR_CMD] |
next_tg_state[TG_RD_CMD]))
shft_cntr <= shft_cntr + 3'b001;
end
always @(posedge clk)
cmd_wr_en_r <= cmd_wr_en;
assign prbs_seed = {{10{seed_cntr}}, 2'b10};
assign dgen_init = next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS];
assign agen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
assign cgen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
assign data_pattern = (ENFORCE_RD_WR == 1) ? ENFORCE_RD_WR_PATTERN :
seed_cntr;
assign dgen_en = wr_proc ? (tg_state[TG_WR_DATA] & wdata_rdy) :
(tg_state[TG_RD_DATA] & rdata_vld) ;
assign wrd_cntr_rst = tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE];
//*****************************************************************************
// Data Generation, FIFO, Checker and Data Sizer block
//*****************************************************************************
mig_7series_v1_8_data_gen_chk #
(
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH)
) data_gen_chk_inst
(
.clk (clk),
.data_en (dgen_en),
.data_pattern (data_pattern),
.pattern_init (dgen_init),
.prbs_seed_i (prbs_seed),
.rdata (rdata),
.rdata_bvld (rdata_bvld),
.rdata_vld (rdata_sig_vld),
.msmatch_err (msmatch_err),
.wrd_cntr_rst (wrd_cntr_rst),
.wrd_cntr (wrd_cntr),
.data_o (prbs_data)
);
assign rdata_rdy = tg_state[TG_RD_DATA];
assign rdata_sig_vld = wr_proc ? 1'b0 : (rdata_vld & tg_state[TG_RD_DATA]);
//*****************************************************************************
// Command generation
//*****************************************************************************
always @(posedge clk) begin
if (tg_state[TG_IDLE])
seed_cntr <= 3'b000;
else if (next_tg_state[TG_UPDT_CNTR] &
(tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE] |
tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD] |
tg_state[TG_RD_DATA] ))
seed_cntr <= seed_cntr + 3'b001;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]) begin
if (ENFORCE_RD_WR == 1)
cmd_gen_csr <= ENFORCE_RD_WR_CMD;
else
cmd_gen_csr <= {seed_cntr, 1'b1, seed_cntr, 1'b1};
end
else if (next_tg_state[TG_GEN_PRBS] &
(tg_state[TG_WR_CMD] | tg_state[TG_WR_DATA] |
tg_state[TG_RD_DATA] | tg_state[TG_RD_CMD] |
tg_state[TG_WR_DONE]))
cmd_gen_csr <= cmd_gen_csr >> 1;
end
assign cmd_gen_csr_sig = cmd_gen_csr[0];
//*****************************************************************************
// Burst Length generation PRBS
//*****************************************************************************
mig_7series_v1_8_cmd_prbs_gen_axi #
(
.PRBS_CMD ("BLEN"),
.PRBS_WIDTH (32), // 64,15,20
.SEED_WIDTH (32), // 32,15,4
.ADDR_WIDTH (C_AXI_ADDR_WIDTH)
) blen_gen_inst
(
.clk_i (clk),
.prbs_seed_init (cgen_init),
.clk_en (cmd_wr_en_r),
.prbs_seed_i (prbs_seed),
.prbs_o (prbs_blen)
);
assign w_burst_4 = (|prbs_blen[7:2]);
assign w_burst_8 = (|prbs_blen[7:3]);
assign w_burst_16 = (|prbs_blen[7:4]);
assign prbs_blen_mdfy = (C_EN_WRAP_TRANS == 1 && wrap_en) ? {4'h0, w_burst_16, w_burst_8,
w_burst_4, 1'b1} : prbs_blen[7:0];
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
curr_blen1 <= 8'h0;
curr_blen2 <= 8'h0;
end
else if (cmd_wr_en) begin
if (curr_wr_ptr)
curr_blen2 <= prbs_blen_mdfy;
else
curr_blen1 <= prbs_blen_mdfy;
end
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | (next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS]))
blen_cntr <= 8'h00;
else if (tg_state[TG_GEN_PRBS] & next_tg_state[TG_GEN_PRBS])
blen_cntr <= prbs_blen_mdfy;
else if (tg_state[TG_WR_DATA] & wdata_rdy & (blen_cntr != 8'h00))
blen_cntr <= blen_cntr - 8'h01;
end
//*****************************************************************************
// Address generation PRBS
//*****************************************************************************
mig_7series_v1_8_cmd_prbs_gen_axi #
(
.FAMILY ("VIRTEX7"),
.ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.PRBS_CMD ("ADDRESS"), // "INSTR", "BLEN","ADDRESS"
.PRBS_WIDTH (32), // 64,15,20
.SEED_WIDTH (32), // 32,15,4
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.PRBS_EADDR (C_END_ADDRESS),
.PRBS_SADDR (C_BEGIN_ADDRESS)
) addr_gen_inst
(
.clk_i (clk),
.prbs_seed_init (agen_init),
.clk_en (cmd_wr_en_r),
.prbs_seed_i (prbs_seed),
.prbs_o (prbs_addr)
);
generate
begin: addr_axi_wr
if (C_AXI_DATA_WIDTH == 256)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_ffe0;
else if (C_AXI_DATA_WIDTH == 128)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff0;
else if (C_AXI_DATA_WIDTH == 64)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff8;
else
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fffc;
end
endgenerate
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
curr_addr1 <= 32'h0;
curr_addr2 <= 32'h0;
end
else if (cmd_wr_en) begin
if (curr_wr_ptr)
curr_addr2 <= prbs_addr_mdfy;
else
curr_addr1 <= prbs_addr_mdfy;
end
end
//*****************************************************************************
// Control Output Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
cmd_en <= 1'b0;
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
cmd_en <= 1'b1;
else if (tg_state[TG_WR_DATA] | tg_state[TG_RD_DATA])
cmd_en <= 1'b0;
end
assign cmd = {cmd_gen_csr_sig, 1'b0, wrap_en};
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
blen <= 8'h0;
addr <= 32'h0;
end
else if (cmd_gen_csr_sig & tg_state[TG_GEN_PRBS]) begin
blen <= prbs_blen_mdfy;
addr <= prbs_addr_mdfy;
end
else if (tg_state[TG_GEN_PRBS]) begin
case ({curr_wr_ptr, curr_rd_ptr})
2'b01: begin
blen <= curr_blen2;
addr <= curr_addr2;
end
default : begin
blen <= curr_blen1;
addr <= curr_addr1;
end
endcase
end
end
generate
begin: cntrl_sig
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
if (C_AXI_DATA_WIDTH == 1024)
assign ctl[2:0] = 3'b111;
else if (C_AXI_DATA_WIDTH == 512)
assign ctl[2:0] = 3'b110;
else if (C_AXI_DATA_WIDTH == 256)
assign ctl[2:0] = 3'b101;
else if (C_AXI_DATA_WIDTH == 128)
assign ctl[2:0] = 3'b100;
else if (C_AXI_DATA_WIDTH == 64)
assign ctl[2:0] = 3'b011;
else
assign ctl[2:0] = 3'b010;
end
end
endgenerate
//*****************************************************************************
// Write Output Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
wdata_cmptd <= 1'b0;
else if (tg_state[TG_WR_DONE])
wdata_cmptd <= 1'b0;
else if ((tg_state[TG_WR_DATA] & wdata_rdy & blen_cntr == 8'h01) |
(next_tg_state[TG_WR_DATA] & tg_state[TG_WR_CMD] & blen_cntr == 8'h00))
wdata_cmptd <= 1'b1;
end
assign wdata_vld = tg_state[TG_WR_DATA];
assign wdata = {{C_AXI_DATA_WIDTH/32}{prbs_data}};
generate
begin: data_sig
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
assign wdata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
//*****************************************************************************
// Status and Debug Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn) begin
cmd_err_dbg <= 1'b0;
data_msmatch_err_dbg <= 1'b0;
write_err_dbg <= 1'b0;
read_err_dbg <= 1'b0;
end
else if (tg_state[TG_IDLE] & next_tg_state[TG_GEN_PRBS]) begin
cmd_err_dbg <= 1'b0;
data_msmatch_err_dbg <= 1'b0;
write_err_dbg <= 1'b0;
read_err_dbg <= 1'b0;
end
else begin
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
(tg_state[TG_RD_CMD] | tg_state[TG_WR_CMD]))
cmd_err_dbg <= 1'b0;
if (msmatch_err & tg_state[TG_RD_DATA])
data_msmatch_err_dbg <= 1'b1;
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
tg_state[TG_WR_DATA])
write_err_dbg <= 1'b1;
if (rdata_cmptd & rdata_vld & rdata_rdy)
read_err_dbg <= (rdata_sts[3:2] == 2'b01);
end
end
always @(posedge clk) begin
if (!resetn) begin
cmd_err <= 1'b0;
data_msmatch_err <= 1'b0;
write_err <= 1'b0;
read_err <= 1'b0;
end
else begin
if (cmd_err_dbg)
cmd_err <= 1'b1;
if (data_msmatch_err_dbg)
data_msmatch_err <= 1'b1;
if (write_err_dbg)
write_err <= 1'b1;
if (read_err_dbg)
read_err <= 1'b1;
end
end
always @(posedge clk) begin
if (!resetn) begin
dbg_wr_sts_vld <= 1'b0;
dbg_rd_sts_vld <= 1'b0;
end
else if (tg_state[TG_GEN_PRBS]) begin
dbg_wr_sts_vld <= 1'b0;
dbg_rd_sts_vld <= 1'b0;
end
else begin
if (wdata_sts_vld)
dbg_wr_sts_vld <= 1'b1;
if (rdata_cmptd & rdata_vld & rdata_rdy)
dbg_rd_sts_vld <= 1'b1;
end
end
always @(posedge clk) begin
if (tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE]) begin
wdata_sts_r <= {WR_STS_WIDTH{1'b0}};
rdata_sts_r <= {RD_STS_WIDTH{1'b0}};
end
else begin
if (wdata_sts_vld)
wdata_sts_r <= wdata_sts;
if (rdata_cmptd & rdata_vld & rdata_rdy)
rdata_sts_r <= rdata_sts;
end
end
assign dbg_wr_sts = {11'h0, write_err_dbg, cmd_err_dbg, data_pattern, wdata_sts_r};
assign dbg_rd_sts = {2'b00, data_msmatch_err_dbg, read_err_dbg, cmd_err_dbg, data_pattern, wrd_cntr, rdata_sts_r};
assign test_cmptd = tg_state[TG_UPDT_CNTR] & next_tg_state[TG_IDLE];
assign write_cmptd = (tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE]) &
(next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
assign read_cmptd = tg_state[TG_RD_DATA] & (next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
// synthesis translate_off
//*****************************************************************************
// Simulation debug signals and messages
//*****************************************************************************
always @(*) begin
if (test_cmptd) begin
$display ("[INFO] : All tests have been completed");
if (cmd_err)
$display ("[ERROR] Command error has occured");
if (data_msmatch_err)
$display ("[ERROR] Data mismatch error occured");
if (write_err)
$display ("[ERROR] Timeout occured during write transaction");
if (read_err)
$display ("[ERROR] Timeout occured during read transaction");
if (!cmd_err & !data_msmatch_err & !write_err & !read_err)
$display ("[INFO] : Tests PASSED");
$finish;
end
end
// synthesis translate_on
endmodule
top/x300/coregen/ddr3_32bit/example_design/sim/ddr3_model.v
+2677
View File
File diff suppressed because it is too large Load Diff
top/x300/coregen/ddr3_32bit/example_design/sim/ddr3_model_parameters.vh
+2895
View File
File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More