Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
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+The following files were generated for 'chipscope_ila' in directory
+/home/ashish/git/fpgadev/pcie_support/usrp3/top/b250/coregen/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * chipscope_ila.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * chipscope_ila.cdc
+   * chipscope_ila.constraints/chipscope_ila.ucf
+   * chipscope_ila.constraints/chipscope_ila.xdc
+   * chipscope_ila.ncf
+   * chipscope_ila.ngc
+   * chipscope_ila.ucf
+   * chipscope_ila.v
+   * chipscope_ila.veo
+   * chipscope_ila.xdc
+   * chipscope_ila_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * chipscope_ila.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * chipscope_ila.gise
+   * chipscope_ila.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * chipscope_ila_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * chipscope_ila_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+