Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,64 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2013 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3       *
+*                                                                              *
+*     The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port     *
+*     Block Memory and Single Port Block Memory LogiCOREs, but is not a        *
+*     direct drop-in replacement.  It should be used in all new Xilinx         *
+*     designs. The core supports RAM and ROM functions over a wide range of    *
+*     widths and depths. Use this core to generate block memories with         *
+*     symmetric or asymmetric read and write port widths, as well as cores     *
+*     which can perform simultaneous write operations to separate              *
+*     locations, and simultaneous read operations from the same location.      *
+*     For more information on differences in interface and feature support     *
+*     between this core and the Dual Port Block Memory and Single Port         *
+*     Block Memory LogiCOREs, please consult the data sheet.                   *
+*******************************************************************************/
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+bootram your_instance_name (
+  .clka(clka), // input clka
+  .ena(ena), // input ena
+  .wea(wea), // input [3 : 0] wea
+  .addra(addra), // input [12 : 0] addra
+  .dina(dina), // input [31 : 0] dina
+  .douta(douta) // output [31 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file bootram.v when simulating
+// the core, bootram. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+