Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+--   Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+  GENERIC ( C_MAX_DEPTH : INTEGER :=  1024 ;
+            RST_VALUE  : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+            RST_INC  : INTEGER := 0);
+  PORT (
+        CLK         : IN STD_LOGIC;
+        RST         : IN STD_LOGIC;
+        EN          : IN STD_LOGIC;
+        LOAD        :IN STD_LOGIC;
+        LOAD_VALUE  : IN STD_LOGIC_VECTOR (31 DOWNTO 0)  := (OTHERS => '0');
+        ADDR_OUT    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+   SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+   ADDR_OUT <= ADDR_TEMP;
+   PROCESS(CLK)
+   BEGIN
+      IF(RISING_EDGE(CLK)) THEN
+         IF(RST='1') THEN
+    	    ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); 
+         ELSE
+            IF(EN='1') THEN
+               IF(LOAD='1') THEN
+	              ADDR_TEMP <=LOAD_VALUE;
+	           ELSE
+	              IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+         	         ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+	              ELSE
+	                 ADDR_TEMP <= ADDR_TEMP + '1';
+	              END IF;
+	           END IF;
+	        END IF;
+         END IF;
+      END IF;
+   END PROCESS;
+END ARCHITECTURE;
@@ -0,0 +1,248 @@
+    
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+--  Stimulus Generation For SRAM
+--  100 Writes and 100 Reads will be performed in a repeatitive loop till the 
+--  simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC_SRAM IS
+  PORT(
+       Q   : OUT STD_LOGIC;
+       CLK : IN STD_LOGIC;
+       RST : IN STD_LOGIC;
+       D   : IN STD_LOGIC
+  );
+END REGISTER_LOGIC_SRAM;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
+   SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+  Q <= Q_O;
+  FF_BEH: PROCESS(CLK)
+  BEGIN
+    IF(RISING_EDGE(CLK)) THEN
+      IF(RST ='1') THEN
+    	Q_O <= '0';
+      ELSE
+        Q_O <= D;
+      END IF;
+    END IF;
+  END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+  PORT (
+        CLK       : IN   STD_LOGIC;
+        RST       : IN   STD_LOGIC;
+        ADDRA     : OUT  STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); 
+        DINA      : OUT  STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  
+        ENA       : OUT  STD_LOGIC :='0';
+        WEA       : OUT  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+        CHECK_DATA: OUT  STD_LOGIC:='0'
+  );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+   CONSTANT ZERO           : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
+   SIGNAL   WRITE_ADDR     : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   SIGNAL   WRITE_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0)   := (OTHERS => '0');
+   SIGNAL   READ_ADDR_INT  : STD_LOGIC_VECTOR(12 DOWNTO 0)   := (OTHERS => '0');
+   SIGNAL   READ_ADDR      : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   SIGNAL   DINA_INT       : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+   SIGNAL   DO_WRITE       : STD_LOGIC                                    := '0';
+   SIGNAL   DO_READ        : STD_LOGIC                                    := '0';
+   SIGNAL   COUNT_NO       : INTEGER                                      :=0;
+   SIGNAL   DO_READ_REG    : STD_LOGIC_VECTOR(4 DOWNTO 0)                 :=(OTHERS => '0');
+   SIGNAL   WEA_VCC        : STD_LOGIC_VECTOR(3 DOWNTO 0)     :=(OTHERS => '1');
+   SIGNAL   WEA_GND        : STD_LOGIC_VECTOR(3 DOWNTO 0)     :=(OTHERS => '0');
+BEGIN
+   WRITE_ADDR_INT(12 DOWNTO 0) <= WRITE_ADDR(12 DOWNTO 0);
+   READ_ADDR_INT(12 DOWNTO 0)  <= READ_ADDR(12 DOWNTO 0);
+   ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
+    DINA  <= DINA_INT ;
+
+   CHECK_DATA <= DO_READ;
+
+RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+  GENERIC MAP( 
+    C_MAX_DEPTH => 8192 
+  )
+  PORT MAP(
+    CLK        => CLK,
+    RST        => RST,
+    EN         => DO_READ,
+    LOAD       => '0',
+    LOAD_VALUE => ZERO,
+    ADDR_OUT   => READ_ADDR
+  );
+
+WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+  GENERIC MAP(
+    C_MAX_DEPTH => 8192  )
+  PORT MAP(
+     CLK        => CLK,
+  	 RST        => RST,
+	 EN         => DO_WRITE,
+     LOAD       => '0',
+ 	 LOAD_VALUE => ZERO,
+ 	 ADDR_OUT   => WRITE_ADDR
+  );
+
+WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+   GENERIC MAP (
+     DATA_GEN_WIDTH => 32,
+     DOUT_WIDTH     => 32,
+     DATA_PART_CNT  => DATA_PART_CNT_A,
+     SEED           => 2
+   )
+   PORT MAP (
+     CLK      => CLK,
+ 	 RST      => RST,
+     EN       => DO_WRITE,
+     DATA_OUT => DINA_INT          
+   );
+
+WR_RD_PROCESS: PROCESS (CLK)
+BEGIN
+  IF(RISING_EDGE(CLK)) THEN
+     IF(RST='1') THEN
+ 	    DO_WRITE <= '0';
+        DO_READ  <= '0';
+        COUNT_NO <=  0 ;
+     ELSIF(COUNT_NO < 4) THEN
+ 	    DO_WRITE <= '1';
+        DO_READ  <= '0';
+        COUNT_NO <= COUNT_NO + 1;
+     ELSIF(COUNT_NO< 8) THEN
+	    DO_WRITE <= '0';
+        DO_READ  <= '1';
+        COUNT_NO <= COUNT_NO + 1;
+     ELSIF(COUNT_NO=8) THEN
+        DO_WRITE <= '0';
+        DO_READ  <= '0';
+        COUNT_NO <=  0 ;
+     END IF;
+  END IF;
+END PROCESS;
+
+BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
+BEGIN
+  DFF_RIGHT: IF I=0 GENERATE
+  BEGIN
+    SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
+      PORT MAP(
+        Q   => DO_READ_REG(0),
+        CLK => CLK,
+        RST => RST,
+        D   => DO_READ
+      );
+  END GENERATE DFF_RIGHT;
+  DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
+  BEGIN
+     SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
+       PORT MAP(
+          Q   => DO_READ_REG(I),
+          CLK => CLK,
+          RST => RST,
+          D   => DO_READ_REG(I-1)
+       );
+  END GENERATE DFF_OTHERS;
+END GENERATE BEGIN_SHIFT_REG;
+
+   ENA <= DO_READ OR DO_WRITE ;
+   WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
+
+END ARCHITECTURE;
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Testbench Package 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+--   BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+  RETURN STD_LOGIC_VECTOR;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STRING;
+   FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STD_LOGIC;
+   FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : INTEGER;
+   FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------ 
+ FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+ RETURN INTEGER; 
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE DIV                   : INTEGER;
+  BEGIN
+    DIV   := DATA_VALUE/DIVISOR;
+    IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+      DIV := DIV+1;
+    END IF;
+    RETURN DIV;
+  END DIVROUNDUP;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+    RETURN STD_LOGIC_VECTOR IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC;
+    FALSE_CASE : STD_LOGIC)
+    RETURN STD_LOGIC IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : INTEGER;
+    FALSE_CASE : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE RETVAL : INTEGER := 0;
+  BEGIN
+    IF CONDITION=FALSE THEN
+      RETVAL:=FALSE_CASE;
+    ELSE
+      RETVAL:=TRUE_CASE;
+    END IF;
+    RETURN RETVAL;
+  END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STRING;
+    FALSE_CASE : STRING)
+  RETURN STRING IS
+    BEGIN
+     IF NOT CONDITION THEN
+        RETURN FALSE_CASE;
+     ELSE
+        RETURN TRUE_CASE;
+     END IF;
+ END IF_THEN_ELSE;
+  ------------------------------- 
+  FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+    RETURN INTEGER IS
+      VARIABLE WIDTH       : INTEGER := 0;
+      VARIABLE CNT         : INTEGER := 1;
+    BEGIN
+      IF (DATA_VALUE <= 1) THEN
+        WIDTH   := 1;
+      ELSE
+        WHILE (CNT < DATA_VALUE) LOOP
+          WIDTH := WIDTH + 1;
+          CNT   := CNT *2;
+        END LOOP;
+      END IF;
+      RETURN WIDTH;
+    END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
@@ -0,0 +1,296 @@
+ 
+ 
+ 
+
+ 
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bootram_synth.vhd
+--
+-- Description:
+--  Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY bootram_synth IS
+PORT(
+	CLK_IN     : IN  STD_LOGIC;
+    RESET_IN   : IN  STD_LOGIC;
+    STATUS     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0')   --ERROR STATUS OUT OF FPGA
+    );
+END ENTITY;
+
+ARCHITECTURE bootram_synth_ARCH OF bootram_synth IS
+
+
+COMPONENT bootram_exdes 
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+    WEA            : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINA           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    CLKA       : IN STD_LOGIC
+
+
+  );
+
+END COMPONENT;
+
+
+  SIGNAL CLKA: STD_LOGIC := '0';
+  SIGNAL RSTA: STD_LOGIC := '0';
+  SIGNAL ENA: STD_LOGIC := '0';
+  SIGNAL ENA_R: STD_LOGIC := '0';
+  SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL CHECKER_EN : STD_LOGIC:='0';
+  SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+  SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+  SIGNAL clk_in_i: STD_LOGIC;
+ 
+  SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+  SIGNAL ITER_R0 : STD_LOGIC := '0';
+  SIGNAL ITER_R1 : STD_LOGIC := '0';
+  SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+  SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+  BEGIN
+
+--  clk_buf: bufg
+--    PORT map(
+--      i => CLK_IN,
+--      o => clk_in_i
+--    );
+   clk_in_i <= CLK_IN;
+   CLKA <= clk_in_i;
+
+   RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+   PROCESS(clk_in_i)
+   BEGIN
+      IF(RISING_EDGE(clk_in_i)) THEN
+		 RESET_SYNC_R1 <= RESET_IN;
+		 RESET_SYNC_R2 <= RESET_SYNC_R1;
+		 RESET_SYNC_R3 <= RESET_SYNC_R2;
+	  END IF;
+   END PROCESS;
+
+
+PROCESS(CLKA)
+BEGIN
+  IF(RISING_EDGE(CLKA)) THEN
+    IF(RESET_SYNC_R3='1') THEN
+        ISSUE_FLAG_STATUS<= (OTHERS => '0'); 
+	  ELSE
+        ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+   END IF;
+  END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+   BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+      GENERIC MAP ( 
+         WRITE_WIDTH => 32,
+		 READ_WIDTH  => 32      )
+      PORT MAP (
+         CLK     => CLKA,
+         RST     => RSTA, 
+         EN      => CHECKER_EN_R,
+         DATA_IN => DOUTA,
+         STATUS  => ISSUE_FLAG(0)
+	   );
+
+   PROCESS(CLKA)
+   BEGIN
+      IF(RISING_EDGE(CLKA)) THEN
+         IF(RSTA='1') THEN
+		    CHECKER_EN_R <= '0';
+	     ELSE
+		    CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+    BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+     PORT MAP(
+                CLK => clk_in_i,
+             	RST => RSTA,
+                ADDRA  => ADDRA,
+                DINA => DINA,
+ 
+                ENA => ENA,
+                WEA => WEA,
+	            CHECK_DATA => CHECKER_EN
+             );
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+			STATUS(8) <= '0';
+			iter_r2 <= '0';
+			iter_r1 <= '0';
+			iter_r0 <= '0';
+		  ELSE
+			STATUS(8) <= iter_r2;
+			iter_r2 <= iter_r1;
+			iter_r1 <= iter_r0;
+			iter_r0 <= STIMULUS_FLOW(8);
+	      END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+		      STIMULUS_FLOW <= (OTHERS => '0'); 
+           ELSIF(WEA(0)='1') THEN
+		      STIMULUS_FLOW <= STIMULUS_FLOW+1;
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+            ENA_R <= '0' AFTER 50 ns;
+            WEA_R  <= (OTHERS=>'0') AFTER 50 ns;
+            DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+          
+
+           ELSE
+          ENA_R <= ENA AFTER 50 ns;
+            WEA_R  <= WEA AFTER 50 ns;
+            DINA_R <= DINA AFTER 50 ns;
+
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+            ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+          ELSE
+            ADDRA_R <= ADDRA AFTER 50 ns;
+          END IF;
+	    END IF;
+      END PROCESS;
+
+
+    BMG_PORT: bootram_exdes PORT MAP ( 
+      --Port A
+      ENA        => ENA_R,
+      WEA        => WEA_R,
+      ADDRA      => ADDRA_R,
+      DINA       => DINA_R,
+      DOUTA      => DOUTA,
+      CLKA       => CLKA
+
+    );
+END ARCHITECTURE;
@@ -0,0 +1,134 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: bootram_tb.vhd
+-- Description:
+--  Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY bootram_tb IS
+END ENTITY;
+
+
+ARCHITECTURE bootram_tb_ARCH OF bootram_tb IS
+ SIGNAL  STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL  CLK :  STD_LOGIC := '1';
+ SIGNAL  RESET : STD_LOGIC;
+ 
+ BEGIN
+
+  
+ CLK_GEN: PROCESS BEGIN
+     CLK <= NOT CLK;
+     WAIT FOR 100 NS;
+     CLK <= NOT CLK; 
+     WAIT FOR 100 NS;
+  END PROCESS;
+  
+  RST_GEN: PROCESS BEGIN
+    RESET <= '1';
+    WAIT FOR 1000 NS;
+    RESET <= '0';
+    WAIT;
+  END PROCESS;
+
+  
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+--   ASSERT FALSE
+--     REPORT "END SIMULATION TIME REACHED"
+--     SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+  WAIT UNTIL STATUS(8)='1';
+  IF( STATUS(7 downto 0)/="0") THEN
+    ASSERT false
+     REPORT "Test Completed Successfully"
+	 SEVERITY NOTE;
+     REPORT "Simulation Failed"
+	 SEVERITY FAILURE;
+  ELSE
+   ASSERT false
+     REPORT "TEST PASS"
+     SEVERITY NOTE;
+     REPORT "Test Completed Successfully"
+	 SEVERITY FAILURE;
+  END IF;
+  
+END PROCESS;	 
+  
+  bootram_synth_inst:ENTITY work.bootram_synth
+  PORT MAP(
+           CLK_IN   => CLK,
+     	   RESET_IN => RESET,
+           STATUS   => STATUS
+	  );
+
+END ARCHITECTURE;
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+--   Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+  GENERIC ( WRITE_WIDTH : INTEGER :=32;
+            READ_WIDTH  : INTEGER :=32
+  );
+        
+  PORT (
+        CLK      : IN STD_LOGIC;
+        RST      : IN STD_LOGIC;
+        EN       : IN STD_LOGIC; 
+        DATA_IN  : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0);   --OUTPUT VECTOR          
+        STATUS   : OUT STD_LOGIC:= '0'
+  );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+  SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+  SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+  SIGNAL EN_R : STD_LOGIC := '0';
+  SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+  CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+  CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+  SIGNAL ERR_HOLD : STD_LOGIC :='0';
+  SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+   PROCESS(CLK)
+   BEGIN
+     IF(RISING_EDGE(CLK)) THEN
+       IF(RST= '1') THEN
+     	  EN_R <= '0';
+     	  EN_2R <= '0';
+          DATA_IN_R <= (OTHERS=>'0');
+       ELSE
+	      EN_R <= EN;
+	      EN_2R <= EN_R;
+          DATA_IN_R <= DATA_IN;
+       END IF;        
+     END IF;
+   END PROCESS;
+
+   EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN 
+      GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+                    DOUT_WIDTH     => READ_WIDTH,
+         		    DATA_PART_CNT  => DATA_PART_CNT,
+	                SEED           => 2
+      )
+      PORT MAP (
+            CLK      => CLK,
+			RST      => RST,
+            EN       => EN_2R,
+            DATA_OUT => EXPECTED_DATA
+	  );
+
+   PROCESS(CLK)
+   BEGIN
+      IF(RISING_EDGE(CLK)) THEN
+         IF(EN_2R='1') THEN
+        	 IF(EXPECTED_DATA = DATA_IN_R) THEN
+	            ERR_DET<='0';
+        	 ELSE
+	            ERR_DET<= '1';
+        	 END IF;
+         END IF;
+     END IF;
+   END PROCESS;
+
+   PROCESS(CLK,RST)
+   BEGIN
+	  IF(RST='1') THEN
+		 ERR_HOLD <= '0';
+      ELSIF(RISING_EDGE(CLK)) THEN
+         ERR_HOLD <= ERR_HOLD  OR ERR_DET ;
+      END IF;
+   END PROCESS;
+
+   STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+--   Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+  GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+            DOUT_WIDTH     : INTEGER := 32;
+            DATA_PART_CNT  : INTEGER := 1;
+            SEED           : INTEGER := 2
+  );
+        
+  PORT (
+        CLK      : IN STD_LOGIC;
+        RST      : IN STD_LOGIC;
+        EN       : IN STD_LOGIC; 
+        DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+  CONSTANT LOOP_COUNT     : INTEGER   := DIVROUNDUP(DATA_GEN_WIDTH,8);
+  SIGNAL   RAND_DATA      : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+  SIGNAL   LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+  SIGNAL   LOCAL_CNT      : INTEGER   :=1;
+  SIGNAL   DATA_GEN_I     : STD_LOGIC :='0';
+BEGIN
+
+  LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+  DATA_OUT       <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+  DATA_GEN_I     <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+  PROCESS(CLK)
+  BEGIN
+     IF(RISING_EDGE (CLK)) THEN
+        IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+           LOCAL_CNT <=1;
+        ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+           IF(LOCAL_CNT = 1) THEN
+              LOCAL_CNT <= LOCAL_CNT+1;
+           ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+              LOCAL_CNT <= LOCAL_CNT+1;
+           ELSE
+              LOCAL_CNT <= 1;
+           END IF;
+        ELSE
+          LOCAL_CNT <= 1;
+        END IF;
+     END IF;
+  END PROCESS;
+
+  RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+    RAND_GEN_INST:ENTITY work.RANDOM
+       GENERIC MAP(
+           WIDTH => 8,
+           SEED => (SEED+N) 
+       )
+       PORT MAP(
+          CLK => CLK,
+	      RST => RST,
+          EN  => DATA_GEN_I,
+          RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+       );
+  END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
@@ -0,0 +1,64 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+ 
+
+
+
+wcfg new
+isim set radix hex
+wave add /bootram_tb/status
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/CLKA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ADDRA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DINA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/WEA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ENA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DOUTA
+run all
+quit
@@ -0,0 +1,71 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+cp ../../../bootram.mif .
+
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../../bootram.v 
+vhpcomp -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ../bmg_tb_pkg.vhd
+vhpcomp -work work    ../random.vhd
+vhpcomp -work work    ../data_gen.vhd
+vhpcomp -work work    ../addr_gen.vhd
+vhpcomp -work work    ../checker.vhd
+vhpcomp -work work    ../bmg_stim_gen.vhd
+vhpcomp -work work    ../bootram_synth.vhd 
+vhpcomp -work work    ../bootram_tb.vhd
+
+
+vlogcomp -work work $XILINX/verilog/src/glbl.v
+fuse work.bootram_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o bootram_tb.exe
+
+./bootram_tb.exe -gui -tclbatch simcmds.tcl
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
@@ -0,0 +1,77 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+ vlib work 
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../../bootram.v 
+vcom -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../random.vhd
+vcom -work work    ../data_gen.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../checker.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../bootram_synth.vhd 
+vcom -work work    ../bootram_tb.vhd
+
+
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vsim  -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.bootram_tb
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
@@ -0,0 +1,72 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+
+
+mkdir work
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../../bootram.v 
+ncvhdl -v93 -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../random.vhd
+ncvhdl -v93 -work work    ../data_gen.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../checker.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../bootram_synth.vhd 
+ncvhdl -v93 -work work    ../bootram_tb.vhd
+
+echo "Elaborating Design"
+ncvlog -work work $XILINX/verilog/src/glbl.v
+ncelab -access +rwc glbl work.bootram_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.bootram_tb
@@ -0,0 +1,71 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../bootram.mif .
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../../bootram.v
+vhdlan  ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../random.vhd
+vhdlan    ../data_gen.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../checker.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../bootram_synth.vhd 
+vhdlan    ../bootram_tb.vhd
+
+echo "Elaborating Design"
+vlogan +v2k $XILINX/verilog/src/glbl.v
+vcs +vcs+lic+wait -debug bootram_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add bootram_tb
+run 
+quit
@@ -0,0 +1,84 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#--  BMG core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create bootram_Group
+gui_list_add_group -id Wave.1 {bootram_Group}
+
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/status
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
@@ -0,0 +1,37 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+      add wave -noupdate /bootram_tb/status
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
@@ -0,0 +1,22 @@
+
+
+ 
+ 
+ 
+
+ 
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+      waveform add -signals /bootram_tb/status
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+console submit -using simulator -wait no "run"
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+--   Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+  GENERIC ( WIDTH : INTEGER :=  32;
+ 	        SEED  : INTEGER :=2 
+  );
+        
+  PORT (
+     CLK        : IN STD_LOGIC;
+     RST        : IN STD_LOGIC;
+     EN         : IN STD_LOGIC;
+     RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+  PROCESS(CLK)
+    VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+    VARIABLE TEMP      : STD_LOGIC := '0';
+  BEGIN
+    IF(RISING_EDGE(CLK)) THEN
+       IF(RST='1') THEN
+          RAND_TEMP  := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+	   ELSE
+          IF(EN = '1') THEN
+             TEMP                        := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+             RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+             RAND_TEMP(0)                := TEMP;
+          END IF;
+       END IF;
+    END IF;
+    RANDOM_NUM <= RAND_TEMP;
+  END PROCESS;
+END ARCHITECTURE;
@@ -0,0 +1,64 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+ 
+
+
+
+wcfg new
+isim set radix hex
+wave add /bootram_tb/status
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/CLKA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ADDRA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DINA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/WEA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ENA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DOUTA
+run all
+quit
@@ -0,0 +1,67 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+cp ../../../bootram.mif .
+
+
+vlogcomp -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ../bmg_tb_pkg.vhd
+vhpcomp -work work    ../random.vhd
+vhpcomp -work work    ../data_gen.vhd
+vhpcomp -work work    ../addr_gen.vhd
+vhpcomp -work work    ../checker.vhd
+vhpcomp -work work    ../bmg_stim_gen.vhd
+vhpcomp -work work    ../bootram_synth.vhd 
+vhpcomp -work work    ../bootram_tb.vhd
+
+    fuse -L simprims_ver work.bootram_tb work.glbl -o bootram_tb.exe
+
+./bootram_tb.exe -sdftyp /bootram_tb/bootram_synth_inst/bmg_port=../../implement/results/routed.sdf -gui -tclbatch simcmds.tcl
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
@@ -0,0 +1,76 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+
+vlib work
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../random.vhd
+vcom -work work    ../data_gen.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../checker.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../bootram_synth.vhd 
+vcom -work work    ../bootram_tb.vhd
+
+    vsim -novopt -t ps  -L simprims_ver +transport_int_delays -sdftyp /bootram_tb/bootram_synth_inst/bmg_port=../../implement/results/routed.sdf $work.bootram_tb $work.glbl -novopt
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
@@ -0,0 +1,79 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+mkdir work
+
+
+ncvlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../random.vhd
+ncvhdl -v93 -work work    ../data_gen.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../checker.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../bootram_synth.vhd 
+ncvhdl -v93 -work work    ../bootram_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :bootram_synth_inst:BMG_PORT,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+
+echo "Elaborating Design"
+ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.bootram_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.bootram_tb
@@ -0,0 +1,71 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../bootram.mif .
+
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../random.vhd
+vhdlan    ../data_gen.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../checker.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../bootram_synth.vhd 
+vhdlan    ../bootram_tb.vhd
+
+
+echo "Elaborating Design"
+vcs +neg_tchk +vcs+lic+wait -debug bootram_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add bootram_tb
+run 
+quit
@@ -0,0 +1,84 @@
+ 
+ 
+ 
+
+ 
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG Generator v8.4 Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create bootram_Group
+gui_list_add_group -id Wave.1 {bootram_Group}
+
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/status
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
@@ -0,0 +1,37 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+
+      add wave -noupdate /bootram_tb/status
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
@@ -0,0 +1,21 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+
+      waveform add -signals /bootram_tb/status
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+console submit -using simulator -wait no "run"