Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
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+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy bootram_exdes.ngc .\results\
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+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\bootram.ngc results\
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+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\bootram_exdes.ucf results\
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+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
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+echo 'Running map'
+map bootram_exdes -o mapped.ncd  -pr i
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+echo 'Running par'
+par mapped.ncd routed.ncd
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+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed -g UnconstrainedPins:Allow
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+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v