Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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+
+ 
+ 
+ 
+
+ 
+
+
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy bootram_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\bootram.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\bootram_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
+
+echo 'Running map'
+map bootram_exdes -o mapped.ncd  -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
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+
+ 
+ 
+ 
+
+ 
+
+
+
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp bootram_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../bootram.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/bootram_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
+
+echo 'Running map'
+map bootram_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\bootram.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../bootram.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc7k410tffg900-2
+set projName bootram
+set design bootram
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module bootram_exdes
+add_files -norecurse {../../example_design/bootram_exdes.vhd}
+add_files -norecurse {./bootram.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/bootram_exdes.xdc}
+set_property top bootram_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module bootram_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module bootram_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
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+work ../example_design/bootram_exdes.vhd
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+run
+-ifmt VHDL
+-ent bootram_exdes
+-p xc7k410t-ffg900-2
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn bootram_exdes 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain