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top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt
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CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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<TITLE>axi_vfifo_ctrl_v1_1_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm">www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
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################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "ACLK" TNM_NET = "ACLK";
TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ;
################################################################################
top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd
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--------------------------------------------------------------------------------
--
-- AXI Virtual FIFO Controller Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi_vfifo_64_exdes.vhd
--
-- Description:
-- This is the VFIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity axi_vfifo_64_exdes is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end axi_vfifo_64_exdes;
architecture xilinx of axi_vfifo_64_exdes is
signal s_aclk_i : std_logic;
component axi_vfifo_64 is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => ACLK,
o => s_aclk_i
);
exdes_inst : axi_vfifo_64
PORT MAP (
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TKEEP => S_AXIS_TKEEP,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TID => S_AXIS_TID,
S_AXIS_TDEST => S_AXIS_TDEST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TSTRB => M_AXIS_TSTRB,
M_AXIS_TKEEP => M_AXIS_TKEEP,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TID => M_AXIS_TID,
M_AXIS_TDEST => M_AXIS_TDEST,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWREGION => M_AXI_AWREGION,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WUSER => M_AXI_WUSER,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BUSER => M_AXI_BUSER,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARREGION => M_AXI_ARREGION,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RUSER => M_AXI_RUSER,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL,
VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY,
VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL,
-- Status Signal
VFIFO_IDLE => VFIFO_IDLE,
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR,
VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR,
VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR,
ACLK => s_aclk_i,
ARESETN => ARESETN
);
end xilinx;
top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc
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################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ]
################################################################################
top/x300/coregen/axi_vfifo_64/implement/implement.bat
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rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy axi_vfifo_64_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement.sh
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#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp axi_vfifo_64_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement_synplify.bat
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rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement_synplify.sh
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#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.bat
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rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\axi_vfifo_64.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.sh
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#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../axi_vfifo_64.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.tcl
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# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc7k410tffg900-2
set projName axi_vfifo_64
set design axi_vfifo_64
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module axi_vfifo_64_exdes
add_files -norecurse {../../example_design/axi_vfifo_64_exdes.vhd}
add_files -norecurse {./axi_vfifo_64.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_exdes.xdc}
set_property top axi_vfifo_64_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module axi_vfifo_64_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
top/x300/coregen/axi_vfifo_64/implement/xst.prj
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work ../example_design/axi_vfifo_64_exdes.vhd
top/x300/coregen/axi_vfifo_64/implement/xst.scr
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run
-ifmt VHDL
-ent axi_vfifo_64_exdes
-p xc7k410t-ffg900-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn axi_vfifo_64_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain