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Pushing the bulk of UHD-3.7.0 code.

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top/x300/coregen/axi4_bram_1kx64/blk_mem_gen_v7_3_readme.txt
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Core name: Xilinx LogiCORE Block Memory Generator
Version: 7.3 Rev 1
Release: ISE 14.4 / Vivado 2012.4
Release Date: October 16, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
................................................................................
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v7.3:
4.1 ISE
4.2 Vivado
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v7.3 of this core at time of release:
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
5.2 Vivado
The following are known issues for v7.3 of this core at time of release:
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
Core name: Xilinx LogiCORE Block Memory Generator
Version: 7.3 Rev 1
Release: ISE 14.4 / Vivado 2012.4
Release Date: October 16, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
................................................................................
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v7.3:
4.1 ISE
4.2 Vivado
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v7.3 of this core at time of release:
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
5.2 Vivado
The following are known issues for v7.3 of this core at time of release:
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
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################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "S_ACLK" TNM_NET = "S_ACLK";
TIMESPEC "TS_S_ACLK" = PERIOD "S_ACLK" 25 MHZ;
################################################################################
top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.vhd
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi4_bram_1kx64_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY axi4_bram_1kx64_exdes IS
PORT (
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_ARESETN : IN STD_LOGIC
);
END axi4_bram_1kx64_exdes;
ARCHITECTURE xilinx OF axi4_bram_1kx64_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT axi4_bram_1kx64 IS
PORT (
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_ARESETN : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => S_ACLK,
O => S_ACLK_buf
);
bmg0 : axi4_bram_1kx64
PORT MAP (
-- AXI BMG Input and Output Port Declarations
--Global Signals
S_AClk => S_ACLK_buf,
--AXI Full/Lite Slav=>
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWADDR =>S_AXI_AWADDR,
S_AXI_AWLEN =>S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID =>S_AXI_AWVALID,
S_AXI_AWREADY =>S_AXI_AWREADY,
S_AXI_WDATA =>S_AXI_WDATA,
S_AXI_WSTRB =>S_AXI_WSTRB,
S_AXI_WLAST =>S_AXI_WLAST,
S_AXI_WVALID =>S_AXI_WVALID,
S_AXI_WREADY =>S_AXI_WREADY,
S_AXI_BID =>S_AXI_BID,
S_AXI_BRESP =>S_AXI_BRESP,
S_AXI_BVALID =>S_AXI_BVALID,
S_AXI_BREADY =>S_AXI_BREADY,
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID =>S_AXI_ARID,
S_AXI_ARADDR =>S_AXI_ARADDR,
S_AXI_ARLEN =>S_AXI_ARLEN,
S_AXI_ARSIZE =>S_AXI_ARSIZE,
S_AXI_ARBURST =>S_AXI_ARBURST,
S_AXI_ARVALID =>S_AXI_ARVALID,
S_AXI_ARREADY =>S_AXI_ARREADY,
S_AXI_RID =>S_AXI_RID,
S_AXI_RDATA =>S_AXI_RDATA,
S_AXI_RRESP =>S_AXI_RRESP,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY =>S_AXI_RREADY,
-- AXI Full/Lite Sid=>
S_ARESETN => S_ARESETN
);
END xilinx;
top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.xdc
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################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_S_CLKA" -period 20.0 [ get_ports S_ACLK ]
################################################################################
top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_prod.vhd
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: axi4_bram_1kx64_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 1
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 1
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : ASYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 8
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 64
-- C_READ_WIDTH_A : 64
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 1
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 8
-- C_WRITE_MODE_B : READ_FIRST
-- C_WRITE_WIDTH_B : 64
-- C_READ_WIDTH_B : 64
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY axi4_bram_1kx64_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END axi4_bram_1kx64_prod;
ARCHITECTURE xilinx OF axi4_bram_1kx64_prod IS
COMPONENT axi4_bram_1kx64_exdes IS
PORT (
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_ARESETN : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : axi4_bram_1kx64_exdes
PORT MAP (
-- AXI BMG Input and Output Port Declarations
--Global Signals
S_AClk => S_AClk,
--AXI Full/Lite Slav=>
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWADDR =>S_AXI_AWADDR,
S_AXI_AWLEN =>S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID =>S_AXI_AWVALID,
S_AXI_AWREADY =>S_AXI_AWREADY,
S_AXI_WDATA =>S_AXI_WDATA,
S_AXI_WSTRB =>S_AXI_WSTRB,
S_AXI_WLAST =>S_AXI_WLAST,
S_AXI_WVALID =>S_AXI_WVALID,
S_AXI_WREADY =>S_AXI_WREADY,
S_AXI_BID =>S_AXI_BID,
S_AXI_BRESP =>S_AXI_BRESP,
S_AXI_BVALID =>S_AXI_BVALID,
S_AXI_BREADY =>S_AXI_BREADY,
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID =>S_AXI_ARID,
S_AXI_ARADDR =>S_AXI_ARADDR,
S_AXI_ARLEN =>S_AXI_ARLEN,
S_AXI_ARSIZE =>S_AXI_ARSIZE,
S_AXI_ARBURST =>S_AXI_ARBURST,
S_AXI_ARVALID =>S_AXI_ARVALID,
S_AXI_ARREADY =>S_AXI_ARREADY,
S_AXI_RID =>S_AXI_RID,
S_AXI_RDATA =>S_AXI_RDATA,
S_AXI_RRESP =>S_AXI_RRESP,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY =>S_AXI_RREADY,
-- AXI Full/Lite Sid=>
S_ARESETN => S_ARESETN
);
END xilinx;
top/x300/coregen/axi4_bram_1kx64/implement/implement.bat
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rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy axi4_bram_1kx64_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi4_bram_1kx64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi4_bram_1kx64_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 axi4_bram_1kx64_exdes
echo 'Running map'
map axi4_bram_1kx64_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi4_bram_1kx64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi4_bram_1kx64/implement/implement.sh
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#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp axi4_bram_1kx64_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi4_bram_1kx64.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi4_bram_1kx64_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 axi4_bram_1kx64_exdes
echo 'Running map'
map axi4_bram_1kx64_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi4_bram_1kx64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi4_bram_1kx64/implement/planAhead_ise.bat
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#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\axi4_bram_1kx64.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
top/x300/coregen/axi4_bram_1kx64/implement/planAhead_ise.sh
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#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../axi4_bram_1kx64.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
top/x300/coregen/axi4_bram_1kx64/implement/planAhead_ise.tcl
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# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc7k410tffg900-2
set projName axi4_bram_1kx64
set design axi4_bram_1kx64
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module axi4_bram_1kx64_exdes
add_files -norecurse {../../example_design/axi4_bram_1kx64_exdes.vhd}
add_files -norecurse {./axi4_bram_1kx64.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi4_bram_1kx64_exdes.xdc}
set_property top axi4_bram_1kx64_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module axi4_bram_1kx64_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi4_bram_1kx64_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
top/x300/coregen/axi4_bram_1kx64/implement/xst.prj
Executable
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@@ -0,0 +1 @@
work ../example_design/axi4_bram_1kx64_exdes.vhd
top/x300/coregen/axi4_bram_1kx64/implement/xst.scr
Executable
+13
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run
-ifmt VHDL
-ent axi4_bram_1kx64_exdes
-p xc7k410t-ffg900-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn axi4_bram_1kx64_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
top/x300/coregen/axi4_bram_1kx64/simulation/addr_gen.vhd
Executable
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/axi4_bram_1kx64_synth.vhd
Executable
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi4_bram_1kx64_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY axi4_bram_1kx64_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE axi4_bram_1kx64_synth_ARCH OF axi4_bram_1kx64_synth IS
COMPONENT axi4_bram_1kx64_exdes
PORT (
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_ARESETN : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL S_ACLK: STD_LOGIC := '0';
SIGNAL S_ARESETN: STD_LOGIC := '0';
SIGNAL S_AXI_AWID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWADDR: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWLEN: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWSIZE: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWBURST: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWVALID: STD_LOGIC := '0';
SIGNAL S_AXI_AWREADY: STD_LOGIC;
SIGNAL S_AXI_WDATA: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_WSTRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_WLAST: STD_LOGIC := '0';
SIGNAL S_AXI_WVALID: STD_LOGIC := '0';
SIGNAL S_AXI_WREADY: STD_LOGIC;
SIGNAL S_AXI_BID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_ARID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_RID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_BRESP: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S_AXI_BVALID: STD_LOGIC;
SIGNAL S_AXI_BREADY: STD_LOGIC := '0';
SIGNAL S_AXI_ARLEN: STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_ARSIZE: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_ARBURST: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_RLAST: STD_LOGIC;
SIGNAL S_AXI_ARADDR: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_ARVALID: STD_LOGIC := '0';
SIGNAL S_AXI_ARREADY: STD_LOGIC;
SIGNAL S_AXI_RDATA: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL S_AXI_RRESP: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S_AXI_RVALID: STD_LOGIC;
SIGNAL S_AXI_RREADY: STD_LOGIC := '0';
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
S_AClk <= clk_in_i;
S_ARESETN<=NOT RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.AXI_CHECKER
PORT MAP (
CLK => S_AClk,
RST => RSTA,
EN => CHECKER_EN,
DATA_IN => S_AXI_RDATA,
STATUS => ISSUE_FLAG(0)
);
BMG_STIM_GEN_INST: ENTITY work.BMG_STIM_GEN
PORT MAP (
S_AClk => S_AClk,
S_ARESETN => S_ARESETN,
S_AXI_AWADDR =>S_AXI_AWADDR,
S_AXI_AWVALID =>S_AXI_AWVALID,
S_AXI_AWREADY =>S_AXI_AWREADY,
s_axi_awid => S_AXI_AWID,
S_AXI_BID => S_AXI_BID,
s_axi_arid => S_AXI_ARID,
S_AXI_RID =>S_AXI_RID,
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_WDATA =>S_AXI_WDATA,
S_AXI_WSTRB =>S_AXI_WSTRB,
S_AXI_WLAST => S_AXI_WLAST,
S_AXI_WVALID =>S_AXI_WVALID,
S_AXI_WREADY =>S_AXI_WREADY,
S_AXI_BRESP =>S_AXI_BRESP,
S_AXI_BVALID =>S_AXI_BVALID,
S_AXI_BREADY =>S_AXI_BREADY,
S_AXI_ARADDR =>S_AXI_ARADDR,
S_AXI_ARVALID =>S_AXI_ARVALID,
S_AXI_ARREADY =>S_AXI_ARREADY,
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_RDATA =>S_AXI_RDATA,
S_AXI_RRESP =>S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY =>S_AXI_RREADY,
S_AXI_RLAST => S_AXI_RLAST,
CHECK_RDATA => CHECKER_EN,
ERROR_FLAG => ISSUE_FLAG(7 DOWNTO 1)
);
PROCESS(S_AClk)
BEGIN
IF(RISING_EDGE(S_AClk)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(S_AClk)
BEGIN
IF(RISING_EDGE(S_AClk)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(S_AXI_AWVALID='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: axi4_bram_1kx64_exdes PORT MAP (
-- AXI BMG Input and Output Port Declarations
--Global Signals
S_ACLK => S_ACLK,
--AXI Full/Lite Slave
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWADDR =>S_AXI_AWADDR,
S_AXI_AWLEN =>S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID =>S_AXI_AWVALID,
S_AXI_AWREADY =>S_AXI_AWREADY,
S_AXI_WDATA =>S_AXI_WDATA,
S_AXI_WSTRB =>S_AXI_WSTRB,
S_AXI_WLAST =>S_AXI_WLAST,
S_AXI_WVALID =>S_AXI_WVALID,
S_AXI_WREADY =>S_AXI_WREADY,
S_AXI_BID =>S_AXI_BID,
S_AXI_BRESP =>S_AXI_BRESP,
S_AXI_BVALID =>S_AXI_BVALID,
S_AXI_BREADY =>S_AXI_BREADY,
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID =>S_AXI_ARID,
S_AXI_ARADDR =>S_AXI_ARADDR,
S_AXI_ARLEN =>S_AXI_ARLEN,
S_AXI_ARSIZE =>S_AXI_ARSIZE,
S_AXI_ARBURST =>S_AXI_ARBURST,
S_AXI_ARVALID =>S_AXI_ARVALID,
S_AXI_ARREADY =>S_AXI_ARREADY,
S_AXI_RID =>S_AXI_RID,
S_AXI_RDATA =>S_AXI_RDATA,
S_AXI_RRESP =>S_AXI_RRESP,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY =>S_AXI_RREADY,
-- AXI Full/Lite Sid=>
S_ARESETN => S_ARESETN
);
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/axi4_bram_1kx64_tb.vhd
Executable
+134
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@@ -0,0 +1,134 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: axi4_bram_1kx64_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY axi4_bram_1kx64_tb IS
END ENTITY;
ARCHITECTURE axi4_bram_1kx64_tb_ARCH OF axi4_bram_1kx64_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
axi4_bram_1kx64_synth_inst:ENTITY work.axi4_bram_1kx64_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/axi_checker.vhd
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator for AXI FULL
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_axi_full_stim_gen.vhd
--
-- Description:
-- Stimulus Generator For AXI FULL Configuration
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY AXI_CHECKER IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (63 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END AXI_CHECKER;
ARCHITECTURE CHECKER_ARCH OF AXI_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL DATA_IN_I: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DATA_IN_I<=(OTHERS=>'0');
ELSE
DATA_IN_I<=DATA_IN;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
ELSE
EN_R <= EN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH => 64 ,
DATA_PART_CNT => 1,
SEED => 2
)
PORT MAP (
CLK =>CLK,
RST => RST,
EN => EN,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_R='1') THEN
IF(EXPECTED_DATA = DATA_IN_I) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/bmg_axi_protocol_chkr.vhd
Executable
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Protocol Checker for AXI
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_axi_protocol_chkr.vhd
--
-- Description:
-- Protocol Checker For AXI Configuration
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_AXI_FULL_PROTOCOL_CHKR IS
PORT (
S_ACLK : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : IN STD_LOGIC;
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : IN STD_LOGIC;
S_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : IN STD_LOGIC;
S_AXI_RRESP : IN STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
ERROR_FLAG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0') --Some Signals are kept open intentionally to add logic if the user needs more checks on the AXI Protocol
);
END BMG_AXI_FULL_PROTOCOL_CHKR;
ARCHITECTURE BEHAVIORAL OF BMG_AXI_FULL_PROTOCOL_CHKR IS
SIGNAL axi_wready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
SIGNAL wready_timeout : STD_LOGIC :='0';
SIGNAL axi_awready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
SIGNAL awready_timeout : STD_LOGIC :='0';
SIGNAL axi_arready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
SIGNAL arready_timeout : STD_LOGIC :='0';
type memory_type is array (3 downto 0) of std_logic_vector(0 downto 0);
SIGNAL awid_mem : memory_type :=(others=>(others=>'0'));
SIGNAL awid_wr_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
SIGNAL awid_rd_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
SIGNAL arid_mem : memory_type :=(others=>(others=>'0'));
SIGNAL arid_wr_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
SIGNAL arid_rd_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
BEGIN
--------------------------------------------------------------------------
------- AWREADY TIMEOUT CHECKER --------------
--------------------------------------------------------------------------
awready_timeout <= AND_REDUCE(axi_awready_cnt);
AWREADY_ERROR_FLAG:PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
ERROR_FLAG(0) <='0';
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(awready_timeout='1') THEN
ERROR_FLAG(0)<='1';
ELSIF(S_AXI_AWREADY='1') THEN
ERROR_FLAG(0)<='0';
END IF;
END IF;
END PROCESS;
AWREADY_CNT_PROCESS: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
axi_awready_cnt <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='0') THEN
axi_awready_cnt <= axi_awready_cnt+1;
ELSIF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='1') THEN
axi_awready_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------
------- WREADY TIMEOUT CHECKER --------------
--------------------------------------------------------------------------
wready_timeout <= AND_REDUCE(axi_wready_cnt);
PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
ERROR_FLAG(1) <='0';
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(wready_timeout='1') THEN
ERROR_FLAG(1)<='1';
ELSIF(S_AXI_WREADY='1') THEN
ERROR_FLAG(1)<='0';
END IF;
END IF;
END PROCESS;
PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
axi_wready_cnt <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_WVALID='1' AND S_AXI_WREADY='0') THEN
axi_wready_cnt <= axi_wready_cnt+1;
ELSIF(S_AXI_WVALID='1' AND S_AXI_WREADY='1') THEN
axi_wready_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------
------- AWID/BID CHECKER --------------
--------------------------------------------------------------------------
AWID_WR_TO_MEM: PROCESS(S_AClk,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
awid_wr_ptr <=(OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='1') THEN
awid_mem(conv_integer(awid_wr_ptr)) <= S_AXI_AWID(0 downto 0);
awid_wr_ptr <= awid_wr_ptr+'1';
END IF;
END IF;
END PROCESS;
AWID_WID_CHECK: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
ERROR_FLAG(2) <='0';
awid_rd_ptr <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_BVALID='1') THEN
IF(S_AXI_BID = awid_mem(conv_integer(awid_rd_ptr))) THEN
awid_rd_ptr <= awid_rd_ptr+'1';
ELSE
ERROR_FLAG(2) <='1';
END IF;
END IF;
END IF;
END PROCESS;
ARID_WR_TO_MEM: PROCESS(S_AClk,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
arid_wr_ptr <=(OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='1') THEN
arid_mem(conv_integer(arid_wr_ptr)) <= S_AXI_ARID(0 downto 0);
arid_wr_ptr <= arid_wr_ptr+'1';
END IF;
END IF;
END PROCESS;
ARID_RID_CHECK: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
ERROR_FLAG(3) <='0';
arid_rd_ptr <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_RVALID='1' AND S_AXI_RREADY='1') THEN
IF(S_AXI_RID = arid_mem(conv_integer(arid_rd_ptr))) THEN
IF(S_AXI_RLAST='1') THEN
arid_rd_ptr <= arid_rd_ptr+'1';
END IF;
ELSE
ERROR_FLAG(3) <='1';
END IF;
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------
------- ARREADY TIMEOUT CHECKER --------------
--------------------------------------------------------------------------
arready_timeout <= AND_REDUCE(axi_arready_cnt);
ARREADY_ERROR_FLAG:PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
ERROR_FLAG(4) <='0';
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(arready_timeout='1') THEN
ERROR_FLAG(4)<='1';
ELSIF(S_AXI_ARREADY='1') THEN
ERROR_FLAG(4)<='0';
END IF;
END IF;
END PROCESS;
ARREADY_CNT_PROCESS: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
axi_arready_cnt <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='0') THEN
axi_arready_cnt <= axi_arready_cnt+1;
ELSIF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='1') THEN
axi_arready_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/bmg_stim_gen.vhd
Executable
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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator for AXI FULL
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generator For AXI FULL Configuration
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
S_ACLK : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
S_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : OUT STD_LOGIC := '0';
S_AXI_AWREADY : IN STD_LOGIC;
S_AXI_WDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : OUT STD_LOGIC := '0';
S_AXI_WVALID : OUT STD_LOGIC := '0';
S_AXI_WREADY : IN STD_LOGIC;
S_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : IN STD_LOGIC;
S_AXI_BREADY : OUT STD_LOGIC := '0';
S_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : OUT STD_LOGIC := '0';
S_AXI_ARREADY : IN STD_LOGIC;
S_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : IN STD_LOGIC;
S_AXI_RVALID : IN STD_LOGIC;
S_AXI_RREADY : OUT STD_LOGIC := '0';
CHECK_RDATA : OUT STD_LOGIC := '0';
ERROR_FLAG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT WR_RD_DEEP_COUNT : INTEGER:=2;
CONSTANT WAIT_ENABLE : STD_LOGIC_VECTOR (1 DOWNTO 0) := "01";
CONSTANT SEND_ADDR_CMD : STD_LOGIC_VECTOR (1 DOWNTO 0) := "10";
CONSTANT WAIT_BVALID : STD_LOGIC_VECTOR (1 DOWNTO 0) := "11";
CONSTANT RD_WAIT_ENABLE : STD_LOGIC_VECTOR (1 DOWNTO 0) := "01";
CONSTANT RD_SEND_ADDR_CMD : STD_LOGIC_VECTOR (1 DOWNTO 0) := "10";
CONSTANT RD_WAIT_RVALID : STD_LOGIC_VECTOR (1 DOWNTO 0) := "11";
CONSTANT CNT_ZERO : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_RREADY_OSC_I : STD_LOGIC:= '0';
SIGNAL RD_COUNT : INTEGER:= WR_RD_DEEP_COUNT;
SIGNAL WR_COUNT : INTEGER:= WR_RD_DEEP_COUNT;
SIGNAL AXI_WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_AWADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_AXI_ARADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL AXI_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL AXI_ARID_INT : STD_LOGIC_VECTOR(0 DOWNTO 0):=(OTHERS => '0');
SIGNAL AXI_AWID_INT : STD_LOGIC_VECTOR(0 DOWNTO 0):=(OTHERS => '0');
SIGNAL WDATA_CNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL LEN_COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL RD_LEN_COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL S_AXI_AWLEN_I : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL S_AXI_ARLEN_I : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL AXI_WRITE_GEN : STD_LOGIC := '0';
SIGNAL AXI_READ_GEN : STD_LOGIC := '0';
SIGNAL AXI_WDATA_GEN : STD_LOGIC := '0';
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL RD_CURRENT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := RD_WAIT_ENABLE;
SIGNAL RD_NEXT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := RD_WAIT_ENABLE;
SIGNAL CURRENT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := WAIT_ENABLE;
SIGNAL NEXT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := WAIT_ENABLE;
SIGNAL AXI_WDATA : STD_LOGIC_VECTOR(63 DOWNTO 0):= (OTHERS => '0');
SIGNAL S_AWVALID_I : STD_LOGIC := '0';
SIGNAL S_ARVALID_I : STD_LOGIC := '0';
SIGNAL S_WVALID_I : STD_LOGIC := '0';
SIGNAL RST_INT : STD_LOGIC :='0';
SIGNAL S_AXI_AWVALID_I : STD_LOGIC:='0';
SIGNAL S_AXI_WVALID_I : STD_LOGIC:='0';
SIGNAL S_AXI_RREADY_I : STD_LOGIC:= '0';
SIGNAL RREADY_COUNT : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL RD_COMPLETE : STD_LOGIC:='0';
SIGNAL WR_COMPLETE : STD_LOGIC:='0';
SIGNAL S_AXI_WLAST_I : STD_LOGIC:='0';
SIGNAL AXI_NEXT_PKT_ADDR : STD_LOGIC :='0';
SIGNAL AXI_NEXT_RD_ADDR : STD_LOGIC :='0';
SIGNAL S_AXI_BREADY_I : STD_LOGIC:='0';
CONSTANT NUM_OF_BYTES : INTEGER := 8 ;
CONSTANT C_RANGE : INTEGER := 3;
CONSTANT AXI_DEPTH: INTEGER:= 8192;
BEGIN
S_AXI_AWID <= AXI_AWID_INT;
S_AXI_ARID <= AXI_ARID_INT;
RST_INT <= NOT S_ARESETN;
REGISTER_FSM:
PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
CURRENT_STATE <= WAIT_ENABLE;
RD_CURRENT_STATE <= RD_WAIT_ENABLE;
ELSIF(RISING_EDGE(S_ACLK)) THEN
CURRENT_STATE <= NEXT_STATE;
RD_CURRENT_STATE <= RD_NEXT_STATE;
END IF;
END PROCESS;
PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
AXI_AWID_INT <= (OTHERS => '0');
AXI_ARID_INT <= (OTHERS => '0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(AXI_WRITE_GEN='1') THEN
AXI_AWID_INT <= AXI_AWID_INT + '1';
END IF;
IF(AXI_READ_GEN='1') THEN
AXI_ARID_INT <= AXI_ARID_INT + '1';
END IF;
END IF;
END PROCESS;
WR_COMPLETE <= '1' WHEN (WR_COUNT=WR_RD_DEEP_COUNT AND S_AXI_WLAST_I='1') ELSE '0';
WR_COUNT_PACKET: PROCESS(S_ACLK, S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
WR_COUNT <= 0;
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_AWREADY='1' AND S_AXI_AWVALID_I='1') THEN
WR_COUNT <= WR_COUNT+1;
END IF;
IF(WR_COUNT=WR_RD_DEEP_COUNT AND S_AXI_WLAST_I='1') THEN
WR_COUNT<=0;
END IF;
END IF;
END PROCESS;
RD_COMPLETE <= '1' WHEN (RD_COUNT=WR_RD_DEEP_COUNT AND (S_AXI_RLAST='1' AND S_AXI_RVALID='1' AND S_AXI_RREADY_I='1')) ELSE '0';
RD_COUNT_PACKET: PROCESS(S_ACLK, S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
RD_COUNT <=0;
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AXI_ARREADY='1' AND S_ARVALID_I='1') THEN
RD_COUNT <= RD_COUNT+1;
END IF;
IF(RD_COUNT=WR_RD_DEEP_COUNT AND (S_AXI_RLAST='1' AND S_AXI_RVALID='1' AND S_AXI_RREADY_I='1')) THEN
RD_COUNT<=0;
END IF;
END IF;
END PROCESS;
RD_FSM_EN: PROCESS(S_ACLK)
BEGIN
IF(S_ARESETN='0') THEN
DO_READ <='0';
ELSIF(RISING_EDGE(S_ACLK)) THEN
DO_READ <= (WR_COMPLETE);
END IF;
END PROCESS;
WR_FSM_EN: PROCESS(S_ACLK)
BEGIN
IF(S_ARESETN='0') THEN
DO_WRITE <='1';
ELSIF(RISING_EDGE(S_ACLK)) THEN
DO_WRITE <= (RD_COMPLETE);
END IF;
END PROCESS;
--AXI_NEXT_PKT_ADDR <='1' WHEN (AXI_WRITE_GEN='1' AND ((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096)) ELSE '0';
AXI_NEXT_PKT_ADDR <='1' WHEN (AXI_WRITE_GEN='1' AND (((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096) OR ((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=AXI_DEPTH))) ELSE '0';
AXI_WR_ADDR_GEN: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN='0') THEN
AXI_WRITE_ADDR <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF((AXI_WRITE_ADDR>=AXI_DEPTH ) ) THEN
AXI_WRITE_ADDR <= (OTHERS=>'0');
ELSIF(S_AXI_WREADY='1' AND S_AXI_WVALID_I='1') THEN
AXI_WRITE_ADDR <= AXI_WRITE_ADDR + NUM_OF_BYTES;
END IF;
END IF;
END PROCESS;
PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
S_AXI_AWLEN_I <= (OTHERS=> '0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(AXI_WRITE_GEN='1') THEN
IF(AXI_NEXT_PKT_ADDR='0') THEN
S_AXI_AWLEN_I(3 DOWNTO 0) <= AXI_WRITE_ADDR(7 DOWNTO 4);
ELSE
S_AXI_AWLEN_I(3 DOWNTO 0) <= (OTHERS=> '0');
END IF;
END IF;
END IF;
END PROCESS;
-- AXI_NEXT_RD_ADDR <='1' WHEN (AXI_READ_GEN='1' AND ((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096)) ELSE '0';
AXI_NEXT_RD_ADDR <='1' WHEN (AXI_READ_GEN='1' AND (((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096) OR ((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=AXI_DEPTH))) ELSE '0';
PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
S_AXI_ARLEN_I <= (OTHERS=> '0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(AXI_READ_GEN='1') THEN
IF(AXI_NEXT_RD_ADDR='0') THEN
S_AXI_ARLEN_I(3 DOWNTO 0) <= AXI_READ_ADDR(7 DOWNTO 4);
ELSE
S_AXI_ARLEN_I(3 DOWNTO 0) <= (OTHERS=> '0');
END IF;
END IF;
END IF;
END PROCESS;
LEN_COUNT(3 DOWNTO 0) <= AXI_WRITE_ADDR(7 DOWNTO 4);
AXI_WDATA_GEN <= S_AWVALID_I OR (S_AXI_WREADY AND S_AXI_WVALID_I AND (NOT (S_AXI_WLAST_I))) ;
S_AXI_AWLEN <= (OTHERS => '0') AFTER 50 ns WHEN (S_AWVALID_I ='0') ELSE S_AXI_AWLEN_I AFTER 50 ns;
RD_LEN_COUNT(3 DOWNTO 0) <= AXI_READ_ADDR(7 DOWNTO 4);
S_AXI_ARLEN <= (OTHERS => '0') AFTER 50 ns WHEN (S_ARVALID_I ='0') ELSE S_AXI_ARLEN_I AFTER 50 ns;
S_AXI_AWSIZE <= CONV_STD_LOGIC_VECTOR(C_RANGE,3);
S_AXI_ARSIZE <= CONV_STD_LOGIC_VECTOR(C_RANGE,3);
S_AXI_AWBURST <= "01";
S_AXI_ARBURST <= "01";
WDATA_COUNT: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN='0') THEN
WDATA_CNT<=(OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF(S_AWVALID_I='1') THEN
WDATA_CNT<=S_AXI_AWLEN_I;
ELSIF((S_AXI_WREADY='1' AND S_AXI_WVALID_I='1')) THEN
WDATA_CNT<=WDATA_CNT-1;
END IF;
END IF;
END PROCESS;
S_AXI_WLAST_I<= '1' WHEN (WDATA_CNT =CNT_ZERO) ELSE '0';
S_AXI_WLAST <= S_AXI_WLAST_I AFTER 50 ns;
AXI_WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 64,
DOUT_WIDTH => 64 ,
DATA_PART_CNT => 1,
SEED => 2
)
PORT MAP (
CLK =>S_ACLK,
RST => RST_INT,
EN => AXI_WDATA_GEN,
DATA_OUT => AXI_WDATA
);
AWVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN ='0') THEN
S_AWVALID_I <= '0';
ELSIF( RISING_EDGE(S_ACLK)) THEN
IF(AXI_WRITE_GEN='1') THEN
S_AWVALID_I <= '1';
ELSIF(S_AXI_AWVALID_I='1' AND S_AXI_AWREADY='1') THEN
S_AWVALID_I <='0';
END IF;
END IF;
END PROCESS;
WVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN ='0') THEN
S_WVALID_I <= '0';
ELSIF( RISING_EDGE(S_ACLK)) THEN
IF(AXI_WDATA_GEN='1') THEN
S_WVALID_I <= '1';
ELSIF(S_AXI_WVALID_I='1' AND S_AXI_WREADY='1') THEN
S_WVALID_I <='0';
END IF;
END IF;
END PROCESS;
S_AXI_AWADDR_INT <= (OTHERS=>'0') WHEN ( S_AWVALID_I = '0') ELSE AXI_WRITE_ADDR;
S_AXI_AWADDR <= S_AXI_AWADDR_INT AFTER 50 ns;
S_AXI_AWVALID_I <= S_AWVALID_I;
S_AXI_AWVALID <= S_AXI_AWVALID_I AFTER 50 ns;
S_AXI_WVALID_I <= S_WVALID_I;
S_AXI_WVALID <= S_AXI_WVALID_I AFTER 50 ns;
S_AXI_WDATA <= (OTHERS=>'0') AFTER 50 ns WHEN ( S_WVALID_I ='0') ELSE AXI_WDATA AFTER 50 ns;
S_AXI_BREADY_I <= '1';
S_AXI_BREADY <= S_AXI_BREADY_I;
S_AXI_WSTRB <= (OTHERS => '1');
WRITE_FSM: PROCESS(CURRENT_STATE,DO_WRITE,S_AXI_BVALID,S_AXI_WREADY,S_AXI_WVALID_I,WR_COUNT,S_AXI_WLAST_I)
BEGIN
CASE CURRENT_STATE IS
WHEN WAIT_ENABLE =>
AXI_WRITE_GEN <= '0';
IF(DO_WRITE = '1') THEN
NEXT_STATE <= SEND_ADDR_CMD;
ELSE
NEXT_STATE<= WAIT_ENABLE;
END IF;
WHEN SEND_ADDR_CMD =>
AXI_WRITE_GEN <= '1';
NEXT_STATE <= WAIT_BVALID;
WHEN WAIT_BVALID =>
AXI_WRITE_GEN <= '0';
IF(S_AXI_WREADY='1' AND S_AXI_WVALID_I='1' AND S_AXI_WLAST_I='1') THEN
IF(WR_COUNT=WR_RD_DEEP_COUNT) THEN
NEXT_STATE <= WAIT_ENABLE;
ELSE
NEXT_STATE <= SEND_ADDR_CMD;
END IF;
ELSE
NEXT_STATE <= WAIT_BVALID;
END IF;
WHEN OTHERS =>
NEXT_STATE <= WAIT_ENABLE;
AXI_WRITE_GEN <= '0';
END CASE;
END PROCESS;
AXI_RD_ADDR_GEN: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN='0') THEN
AXI_READ_ADDR <= (OTHERS=>'0');
ELSIF(RISING_EDGE(S_ACLK)) THEN
IF((AXI_READ_ADDR>=AXI_DEPTH ) ) THEN
AXI_READ_ADDR <= (OTHERS=>'0');
ELSIF(S_AXI_RREADY_I='1' AND S_AXI_RVALID='1') THEN
AXI_READ_ADDR <= AXI_READ_ADDR + NUM_OF_BYTES;
END IF;
END IF;
END PROCESS;
S_AXI_RREADY <= S_AXI_RREADY_I AFTER 50 ns;
S_AXI_RREADY_I<= S_AXI_RREADY_OSC_I;
PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN = '0') THEN
RREADY_COUNT <=(OTHERS=>'0');
S_AXI_RREADY_OSC_I <='0';
ELSIF(RISING_EDGE(S_ACLK)) THEN
S_AXI_RREADY_OSC_I <=RREADY_COUNT(0) AND RREADY_COUNT(1);
RREADY_COUNT<= RREADY_COUNT +1;
END IF;
END PROCESS;
CHECK_RDATA <= S_AXI_RREADY_I AND S_AXI_RVALID;
READ_FSM: PROCESS(RD_CURRENT_STATE,DO_READ,S_AXI_RVALID,S_AXI_RREADY_I,RD_COUNT,S_AXI_RLAST)
BEGIN
CASE RD_CURRENT_STATE IS
WHEN RD_WAIT_ENABLE =>
AXI_READ_GEN <= '0';
IF(DO_READ = '1') THEN
RD_NEXT_STATE <= RD_SEND_ADDR_CMD;
ELSE
RD_NEXT_STATE <= RD_WAIT_ENABLE;
END IF;
WHEN RD_SEND_ADDR_CMD =>
AXI_READ_GEN <= '1';
RD_NEXT_STATE <= RD_WAIT_RVALID;
WHEN RD_WAIT_RVALID =>
AXI_READ_GEN <= '0';
IF(S_AXI_RVALID='1' AND S_AXI_RREADY_I='1' AND S_AXI_RLAST='1') THEN
IF(RD_COUNT = WR_RD_DEEP_COUNT ) THEN
RD_NEXT_STATE <= RD_WAIT_ENABLE;
ELSE
RD_NEXT_STATE <= RD_SEND_ADDR_CMD;
END IF;
ELSE
RD_NEXT_STATE <= RD_WAIT_RVALID;
END IF;
WHEN OTHERS =>
AXI_READ_GEN <= '0';
RD_NEXT_STATE <= RD_WAIT_ENABLE;
END CASE;
END PROCESS;
S_AXI_ARADDR_INT <= (OTHERS=>'0') WHEN ( S_ARVALID_I = '0') ELSE AXI_READ_ADDR;
S_AXI_ARADDR <= S_AXI_ARADDR_INT AFTER 50 ns;
S_AXI_ARVALID <= S_ARVALID_I AFTER 50 ns;
ARVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
BEGIN
IF(S_ARESETN ='0') THEN
S_ARVALID_I <= '0';
ELSIF( RISING_EDGE(S_ACLK)) THEN
IF(AXI_READ_GEN='1') THEN
S_ARVALID_I <= '1';
ELSIF(S_ARVALID_I='1' AND S_AXI_ARREADY='1') THEN
S_ARVALID_I <='0';
END IF;
END IF;
END PROCESS;
BMG_AXI_FULL_PROT_CHKER_INST: ENTITY work.BMG_AXI_FULL_PROTOCOL_CHKR
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR_INT,
S_AXI_AWVALID => S_AXI_AWVALID_I,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWID => AXI_AWID_INT,
S_AXI_BID => S_AXI_BID,
S_AXI_ARID => AXI_ARID_INT,
S_AXI_RID => S_AXI_RID,
S_AXI_AWLEN => S_AXI_AWLEN_I,
S_AXI_WLAST => S_AXI_WLAST_I,
S_AXI_WVALID => S_AXI_WVALID_I,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => '1',
S_AXI_ARADDR => S_AXI_ARADDR_INT,
S_AXI_ARVALID => S_ARVALID_I,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARLEN => S_AXI_ARLEN_I,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY_I,
S_AXI_RLAST => S_AXI_RLAST,
ERROR_FLAG => ERROR_FLAG
);
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/bmg_tb_pkg.vhd
Executable
+200
View File
@@ -0,0 +1,200 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
top/x300/coregen/axi4_bram_1kx64/simulation/data_gen.vhd
Executable
+140
View File
@@ -0,0 +1,140 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simcmds.tcl
Executable
+89
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@@ -0,0 +1,89 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
wcfg new
isim set radix hex
wave add /axi4_bram_1kx64_tb/status
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ACLK
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWADDR
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWLEN
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWSIZE
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWBURST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WDATA
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WSTRB
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WLAST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BRESP
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARADDR
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARLEN
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARSIZE
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARBURST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RDATA
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RRESP
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RLAST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ARESETN
run all
quit
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_isim.sh
Executable
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@@ -0,0 +1,71 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogcomp -work work ../../../axi4_bram_1kx64.v
vhpcomp -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
echo "Compiling Test Bench Files"
vhpcomp -work work ../bmg_tb_pkg.vhd
vhpcomp -work work ../random.vhd
vhpcomp -work work ../data_gen.vhd
vhpcomp -work work ../addr_gen.vhd
vhpcomp -work work ../bmg_axi_protocol_chkr.vhd
vhpcomp -work work ../axi_checker.vhd
vhpcomp -work work ../bmg_stim_gen.vhd
vhpcomp -work work ../axi4_bram_1kx64_synth.vhd
vhpcomp -work work ../axi4_bram_1kx64_tb.vhd
vlogcomp -work work $XILINX/verilog/src/glbl.v
fuse work.axi4_bram_1kx64_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi4_bram_1kx64_tb.exe
./axi4_bram_1kx64_tb.exe -gui -tclbatch simcmds.tcl
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_mti.bat
Executable
+3
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@@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_mti.do
Executable
+77
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@@ -0,0 +1,77 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
vlib work
vmap work work
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlog -work work ../../../axi4_bram_1kx64.v
vcom -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
echo "Compiling Test Bench Files"
vcom -work work ../bmg_tb_pkg.vhd
vcom -work work ../random.vhd
vcom -work work ../data_gen.vhd
vcom -work work ../addr_gen.vhd
vcom -work work ../bmg_axi_protocol_chkr.vhd
vcom -work work ../axi_checker.vhd
vcom -work work ../bmg_stim_gen.vhd
vcom -work work ../axi4_bram_1kx64_synth.vhd
vcom -work work ../axi4_bram_1kx64_tb.vhd
vlog -work work $env(XILINX)/verilog/src/glbl.v
vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.axi4_bram_1kx64_tb
#Disabled waveform to save the disk space
add log -r /*
#Ignore integer warnings at time 0
set StdArithNoWarnings 1
run 0
set StdArithNoWarnings 0
run -all
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_mti.sh
Executable
+3
View File
@@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_ncsim.sh
Executable
+72
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@@ -0,0 +1,72 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
mkdir work
echo "Compiling Core Verilog UNISIM/Behavioral model"
ncvlog -work work ../../../axi4_bram_1kx64.v
ncvhdl -v93 -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
echo "Compiling Test Bench Files"
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
ncvhdl -v93 -work work ../random.vhd
ncvhdl -v93 -work work ../data_gen.vhd
ncvhdl -v93 -work work ../addr_gen.vhd
ncvhdl -v93 -work work ../bmg_axi_protocol_chkr.vhd
ncvhdl -v93 -work work ../axi_checker.vhd
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
ncvhdl -v93 -work work ../axi4_bram_1kx64_synth.vhd
ncvhdl -v93 -work work ../axi4_bram_1kx64_tb.vhd
echo "Elaborating Design"
ncvlog -work work $XILINX/verilog/src/glbl.v
ncelab -access +rwc glbl work.axi4_bram_1kx64_tb
echo "Simulating Design"
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.axi4_bram_1kx64_tb
top/x300/coregen/axi4_bram_1kx64/simulation/functional/simulate_vcs.sh
Executable
+71
View File
@@ -0,0 +1,71 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
#!/bin/sh
rm -rf simv* csrc DVEfiles AN.DB
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogan +v2k ../../../axi4_bram_1kx64.v
vhdlan ../../example_design/axi4_bram_1kx64_exdes.vhd
echo "Compiling Test Bench Files"
vhdlan ../bmg_tb_pkg.vhd
vhdlan ../random.vhd
vhdlan ../data_gen.vhd
vhdlan ../addr_gen.vhd
vhdlan ../bmg_axi_protocol_chkr.vhd
vhdlan ../axi_checker.vhd
vhdlan ../bmg_stim_gen.vhd
vhdlan ../axi4_bram_1kx64_synth.vhd
vhdlan ../axi4_bram_1kx64_tb.vhd
echo "Elaborating Design"
vlogan +v2k $XILINX/verilog/src/glbl.v
vcs +vcs+lic+wait -debug axi4_bram_1kx64_tb glbl
echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl
top/x300/coregen/axi4_bram_1kx64/simulation/functional/ucli_commands.key
Executable
+4
View File
@@ -0,0 +1,4 @@
dump -file bmg_vcs.vpd -type VPD
dump -add axi4_bram_1kx64_tb
run
quit
top/x300/coregen/axi4_bram_1kx64/simulation/functional/vcs_session.tcl
Executable
+109
View File
@@ -0,0 +1,109 @@
#--------------------------------------------------------------------------------
#--
#-- BMG core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Filename: vcs_session.tcl
#
# Description:
# This is the VCS wave form file.
#
#--------------------------------------------------------------------------------
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
gui_open_window Wave
gui_sg_create axi4_bram_1kx64_Group
gui_list_add_group -id Wave.1 {axi4_bram_1kx64_Group}
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/status
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
gui_zoom -window Wave.1 -full
top/x300/coregen/axi4_bram_1kx64/simulation/functional/wave_mti.do
Executable
+62
View File
@@ -0,0 +1,62 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /axi4_bram_1kx64_tb/status
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 197
configure wave -valuecolwidth 106
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}
top/x300/coregen/axi4_bram_1kx64/simulation/functional/wave_ncsim.sv
Executable
+47
View File
@@ -0,0 +1,47 @@
window new WaveWindow -name "Waves for BMG Example Design"
waveform using "Waves for BMG Example Design"
waveform add -signals /axi4_bram_1kx64_tb/status
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
console submit -using simulator -wait no "run"
top/x300/coregen/axi4_bram_1kx64/simulation/random.vhd
Executable
+112
View File
@@ -0,0 +1,112 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simcmds.tcl
Executable
+89
View File
@@ -0,0 +1,89 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
wcfg new
isim set radix hex
wave add /axi4_bram_1kx64_tb/status
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ACLK
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWADDR
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWLEN
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWSIZE
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWBURST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WDATA
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WSTRB
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WLAST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BRESP
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARADDR
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARLEN
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARSIZE
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARBURST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RDATA
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RRESP
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RLAST
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RVALID
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RREADY
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ARESETN
run all
quit
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_isim.sh
Executable
+67
View File
@@ -0,0 +1,67 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
vlogcomp -work work ../../implement/results/routed.v
echo "Compiling Test Bench Files"
vhpcomp -work work ../bmg_tb_pkg.vhd
vhpcomp -work work ../random.vhd
vhpcomp -work work ../data_gen.vhd
vhpcomp -work work ../addr_gen.vhd
vhpcomp -work work ../bmg_axi_protocol_chkr.vhd
vhpcomp -work work ../axi_checker.vhd
vhpcomp -work work ../bmg_stim_gen.vhd
vhpcomp -work work ../axi4_bram_1kx64_synth.vhd
vhpcomp -work work ../axi4_bram_1kx64_tb.vhd
fuse -L simprims_ver work.axi4_bram_1kx64_tb work.glbl -o axi4_bram_1kx64_tb.exe
./axi4_bram_1kx64_tb.exe -sdftyp /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port=../../implement/results/routed.sdf -gui -tclbatch simcmds.tcl
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_mti.bat
Executable
+3
View File
@@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_mti.do
Executable
+76
View File
@@ -0,0 +1,76 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set work work
#--------------------------------------------------------------------------------
vlib work
vmap work work
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlog -work work ../../implement/results/routed.v
echo "Compiling Test Bench Files"
vcom -work work ../bmg_tb_pkg.vhd
vcom -work work ../random.vhd
vcom -work work ../data_gen.vhd
vcom -work work ../addr_gen.vhd
vcom -work work ../bmg_axi_protocol_chkr.vhd
vcom -work work ../axi_checker.vhd
vcom -work work ../bmg_stim_gen.vhd
vcom -work work ../axi4_bram_1kx64_synth.vhd
vcom -work work ../axi4_bram_1kx64_tb.vhd
vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port=../../implement/results/routed.sdf $work.axi4_bram_1kx64_tb $work.glbl -novopt
#Disabled waveform to save the disk space
add log -r /*
#Ignore integer warnings at time 0
set StdArithNoWarnings 1
run 0
set StdArithNoWarnings 0
run -all
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_mti.sh
Executable
+3
View File
@@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_ncsim.sh
Executable
+79
View File
@@ -0,0 +1,79 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set work work
#--------------------------------------------------------------------------------
mkdir work
ncvlog -work work ../../implement/results/routed.v
echo "Compiling Test Bench Files"
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
ncvhdl -v93 -work work ../random.vhd
ncvhdl -v93 -work work ../data_gen.vhd
ncvhdl -v93 -work work ../addr_gen.vhd
ncvhdl -v93 -work work ../bmg_axi_protocol_chkr.vhd
ncvhdl -v93 -work work ../axi_checker.vhd
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
ncvhdl -v93 -work work ../axi4_bram_1kx64_synth.vhd
ncvhdl -v93 -work work ../axi4_bram_1kx64_tb.vhd
echo "Compiling SDF file"
ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
echo "Generating SDF command file"
echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
echo 'SCOPE = :axi4_bram_1kx64_synth_inst:BMG_PORT,' >> sdf.cmd
echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
echo "Elaborating Design"
ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.axi4_bram_1kx64_tb
echo "Simulating Design"
ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.axi4_bram_1kx64_tb
top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_vcs.sh
Executable
+71
View File
@@ -0,0 +1,71 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
#!/bin/sh
rm -rf simv* csrc DVEfiles AN.DB
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogan +v2k ../../implement/results/routed.v
echo "Compiling Test Bench Files"
vhdlan ../bmg_tb_pkg.vhd
vhdlan ../random.vhd
vhdlan ../data_gen.vhd
vhdlan ../addr_gen.vhd
vhdlan ../bmg_axi_protocol_chkr.vhd
vhdlan ../axi_checker.vhd
vhdlan ../bmg_stim_gen.vhd
vhdlan ../axi4_bram_1kx64_synth.vhd
vhdlan ../axi4_bram_1kx64_tb.vhd
echo "Elaborating Design"
vcs +neg_tchk +vcs+lic+wait -debug axi4_bram_1kx64_tb glbl
echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl
top/x300/coregen/axi4_bram_1kx64/simulation/timing/ucli_commands.key
Executable
+4
View File
@@ -0,0 +1,4 @@
dump -file bmg_vcs.vpd -type VPD
dump -add axi4_bram_1kx64_tb
run
quit
top/x300/coregen/axi4_bram_1kx64/simulation/timing/vcs_session.tcl
Executable
+109
View File
@@ -0,0 +1,109 @@
#--------------------------------------------------------------------------------
#--
#-- BMG Generator v8.4 Core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Filename: vcs_session.tcl
#
# Description:
# This is the VCS wave form file.
#
#--------------------------------------------------------------------------------
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
gui_open_window Wave
gui_sg_create axi4_bram_1kx64_Group
gui_list_add_group -id Wave.1 {axi4_bram_1kx64_Group}
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/status
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
gui_zoom -window Wave.1 -full
top/x300/coregen/axi4_bram_1kx64/simulation/timing/wave_mti.do
Executable
+62
View File
@@ -0,0 +1,62 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /axi4_bram_1kx64_tb/status
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}
top/x300/coregen/axi4_bram_1kx64/simulation/timing/wave_ncsim.sv
Executable
+46
View File
@@ -0,0 +1,46 @@
window new WaveWindow -name "Waves for BMG Example Design"
waveform using "Waves for BMG Example Design"
waveform add -signals /axi4_bram_1kx64_tb/status
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
console submit -using simulator -wait no "run"