Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
@@ -0,0 +1,297 @@
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///////////////////////////////////////////////////////////////////
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//
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// USRP3 Task Libaray
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//
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///////////////////////////////////////////////////////////////////
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`define SID(a,b,c,d) ((a & 'hff) << 24) | ((b & 'hff) << 16)| ((c & 'hff) << 8) | (d & 'hff)
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`ifndef TB_FILE_IN_NUMBER
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`define TB_FILE_IN_NUMBER 0
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`endif
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`ifndef TB_FILE_OUT_NUMBER
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`define TB_FILE_OUT_NUMBER 0
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`endif
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`ifndef TB_FILE_GOLDEN_NUMBER
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`define TB_FILE_GOLDEN_NUMBER 0
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`endif
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`ifndef TB_FILE_IN_NAME
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`define TB_FILE_IN_NAME "tb_file_in"
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`endif
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`ifndef TB_FILE_OUT_NAME
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`define TB_FILE_OUT_NAME "tb_file_out"
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`endif
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`ifndef TB_FILE_GOLDEN_NAME
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`define TB_FILE_GOLDEN_NAME "tb_file_golden"
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`endif
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integer tb_file_in_desc[`TB_FILE_IN_NUMBER-1:0];
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/* -----\/----- EXCLUDED -----\/-----
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reg clk;
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reg reset;
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reg clear;
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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reg set_stb;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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`ifndef CHDR_IN_NUMBER
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`define CHDR_IN_NUMBER 1
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`endif
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reg [63:0] data_in[`CHDR_IN_NUMBER-1:0];
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reg last_in[`CHDR_IN_NUMBER-1:0];
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reg valid_in[`CHDR_IN_NUMBER-1:0];
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wire ready_in[`CHDR_IN_NUMBER-1:0];
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-----/\----- EXCLUDED -----/\----- */
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///////////////////////////////////////////////////////////////////
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//
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// open_files
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//
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// The "open_files" task opens all standard stimulus, response, and
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// golden response files to drive other tasks in the library.
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// Both the numbers of files and there names can be altered by pre-defining
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// the TB_FILE* pre-processor definitions. All files are assumed to be
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// readmemh style format and will use a ".hex" file extension.
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//
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///////////////////////////////////////////////////////////////////
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task open_files;
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reg [7:0] x;
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reg [7:0] y;
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reg [8*32:0] filename;
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begin
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x = 0;
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// Caveman verilog string handling to dynamicly form file name
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while (x != `TB_FILE_IN_NUMBER) begin
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y = x;
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filename = {`TB_FILE_IN_NAME,("0" + (y % 10))};
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while (y/10 >0) begin
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filename = {(filename << 8),("0" + (y % 10))};
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y = y/10;
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end
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// Always use .hex as file extention for readmemh style data
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filename = {filename,".hex"};
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tb_file_in_desc[x] = $fopen(filename);
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x = x + 1;
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end
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end
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endtask
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///////////////////////////////////////////////////////////////////
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//
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// close_files
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//
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// The "close_files" task closes all files opened by a previous
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// call to "open_files".
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//
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///////////////////////////////////////////////////////////////////
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task close_files;
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reg [7:0] x;
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begin
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x = 0;
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while (x != `TB_FILE_IN_NUMBER) begin
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$fclose(tb_file_in_desc[x]);
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x = x + 1;
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end
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end
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endtask // close_files
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///////////////////////////////////////////////////////////////////
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//
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// write_settings_bus
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//
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// The "write settings_bus" task performs a single settings bus
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// transaction in 3 clock cycles, the first and 3rd cycles being
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// idle cycles. "write_settings_bus" is not re-entrant and should
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// only be used sequentially in a single test bench thread.
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//
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///////////////////////////////////////////////////////////////////
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task write_setting_bus;
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input [15:0] address;
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input [31:0] data;
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begin
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@(posedge clk);
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set_stb <= 1'b0;
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set_addr <= 16'h0;
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set_data <= 32'h0;
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@(posedge clk);
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set_stb <= 1'b1;
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set_addr <= address;
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set_data <= data;
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@(posedge clk);
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set_stb <= 1'b0;
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set_addr <= 16'h0;
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set_data <= 32'h0;
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end
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endtask // write_setting_bus
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///////////////////////////////////////////////////////////////////
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//
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// Place 64bits of data on CHDR databus, set last if indicated.
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// Wait unitl ready asserted before returning with valid de-assrted.
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//
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///////////////////////////////////////////////////////////////////
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task automatic enqueue_line;
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input [7:0] input_port;
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input last;
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input [63:0] data;
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begin
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data_in[input_port] <= data;
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last_in[input_port] <= last;
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valid_in[input_port] <= 1;
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@(posedge clk);
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while (~ready_in[input_port]) begin
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@(posedge clk);
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end
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data_in[input_port] <= 0;
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last_in[input_port] <= 0;
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valid_in[input_port] <= 0;
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end
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endtask // enqueue_line
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///////////////////////////////////////////////////////////////////
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//
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// Place 64bits of data on CHDR databus, set last if indicated.
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// Wait unitl ready asserted before returning with valid de-assrted.
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//
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///////////////////////////////////////////////////////////////////
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task automatic dequeue_line;
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input [7:0] output_port;
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output last;
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output [63:0] data;
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begin
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while (~valid_out[output_port]) begin
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ready_out[output_port] <= 1;
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@(posedge clk);
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end
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// NOTE: A subtle constraint of Verilog is that non-blocking assignments can not be used
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// to an automatically allocated variable. Fall back to blocking assignent
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data = data_out[output_port];
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last = last_out[output_port];
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ready_out[output_port] <= 1;
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@(posedge clk);
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ready_out[output_port] <= 0;
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end
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endtask // enqueue_line
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///////////////////////////////////////////////////////////////////
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//
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// CHDR Header format:
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// Word1: FLAGS [63:60], SEQ_ID [59:48], SIZE [47:32], SID [31:0]
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// [63]ExtensionContext, [62]HasTrailer, [61]HasTime, [60]EOB
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// Word2: Time [63:0] (Optional, see header bit [61])
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// Word3+: Payload
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//
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///////////////////////////////////////////////////////////////////
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task automatic enqueue_chdr_pkt_count;
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input [7:0] input_port; // Which test bench CHDR ingress port
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input [11:0] seq_id; // CHDR sequence ID.
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input [15:0] chdr_size; // Total CHDR packet size in bytes.
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input has_time; // This CHDR packet has 64bit time field.
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input [63:0] chdr_time; // 64bit CHDR time value
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input is_extension; // This packet is flaged extension context
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input is_eob; // This packet is the end of a CHDR burst.
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input [31:0] chdr_sid; // CHDR SID address pair.
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integer i;
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reg [15:0] j;
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begin
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@(posedge clk);
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enqueue_line(input_port, 0, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid});
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if (has_time) // If time flag set add 64bit time as second word.
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enqueue_line(input_port, 0, chdr_time);
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j = 0;
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for (i = (has_time ? 24 : 16); i < chdr_size; i = i + 8) begin
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enqueue_line(input_port, 0 , {j,j+16'h1,j+16'h2,j+16'h3});
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j = j + 4;
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end
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// Populate last line with data even if sizes shows it's not used.
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enqueue_line(input_port, 1, {j,j+16'h1,j+16'h2,j+16'h3});
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end
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endtask // automatic
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task automatic dequeue_chdr_pkt_count;
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input [7:0] output_port; // Which test bench CHDR ingress port
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input [11:0] seq_id; // CHDR sequence ID.
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input [15:0] chdr_size; // Total CHDR packet size in bytes.
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input has_time; // This CHDR packet has 64bit time field.
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input [63:0] chdr_time; // 64bit CHDR time value
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input is_extension; // This packet is flaged extension context
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input is_eob; // This packet is the end of a CHDR burst.
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input [31:0] chdr_sid; // CHDR SID address pair.
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integer i;
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reg [15:0] j;
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reg last;
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reg [63:0] data;
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begin
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@(posedge clk);
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dequeue_line(output_port, last, data);
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if ({is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid} !== data)
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$display("FAILED: Output port: %3d Bad CHDR Header. Got %8x, expected %8x @ time: %d ",
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output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time);
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// else
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// $display("PASSED: Output port: %3d Bad CHDR Header. Got %8x, expected %8x @ time: %d ",
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// output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time);
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if (has_time) // If time flag set add 64bit time as second word.
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begin
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dequeue_line(output_port, last, data);
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if (data !== chdr_time)
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$display("FAILED: Output port: %3d Bad CHDR Time. Got %8x, expected %8x @ time: %d ",
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output_port, data, chdr_time, $time);
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// else
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// $display("PASSED: Output port: %3d Bad CHDR Time. Got %8x, expected %8x @ time: %d ",
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// output_port, data, chdr_time, $time);
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end
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j = 0;
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for (i = (has_time ? 24 : 16); i < chdr_size; i = i + 8) begin
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dequeue_line(output_port, last , data);
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if ({j,j+16'h1,j+16'h2,j+16'h3} !== data)
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$display("FAILED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ",
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output_port, data,{j,j+16'h1,j+16'h2,j+16'h3} ,$time);
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// else
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// $display("PASSED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ",
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// output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time);
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j = j + 4;
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end
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// Check only bytes included in packet
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dequeue_line(output_port, last, data);
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if (({j,j+16'h1,j+16'h2,j+16'h3} >> (8-j)) !== ( data>> (8-j)))
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$display("FAILED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ",
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output_port, data >> (8-j),
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{j,j+16'h1,j+16'h2,j+16'h3} >> (8-j),$time);
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// else
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// $display("PASSED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ",
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// output_port, data >> (8-j),
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// {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid} >> (8-j),$time);
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end
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endtask // dequeue_packet
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