Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053

sim/duc_chain_x300/dctest/.gitignore

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+fuse*
+isim*
+*.exe
+*.wcfg

sim/duc_chain_x300/dctest/run_isim

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+rm -rf fuse* *.exe isim
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/dsp \
+         --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen_dsp \
+	 --sourcelibdir ${XILINX}/verilog/src/unimacro \
+	 ../../../lib/dsp/duc_chain_x300_tb.v
+
+
+
+fuse work.duc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o duc_chain_x300_tb.exe
+
+# run the simulation scrip
+./duc_chain_x300_tb.exe  -tclbatch simcmds.tcl  # -gui 
+
+

sim/duc_chain_x300/dctest/simcmds.tcl

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+# file: simcmds.tcl
+
+# create the simulation script
+#vcd dumpfile isim.vcd
+#vcd dumpvars -m /bus_clk_gen_tb -l 0
+#wave add /
+run 1 s
+quit
+