Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,19 @@
+/bin/rm -r isim
+
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/axi \
+	 --sourcelibdir ../../../lib/fifo \
+	 --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen \
+	 ../../../lib/axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe  -gui #-tclbatch simcmds.tcl
+
+