Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.zpu_top_pkg.all;
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use work.wishbone_pkg.all;
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use work.zpupkg.all;
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use work.zpu_config.all;
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------------------------------------------------------------------------
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-- Top level ZPU + wishbone componenent to use in a verilog design:
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-- zpu_wb_top wraps around the zpu_system component.
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-- All IO lines are exposed as std_logic for verilog.
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------------------------------------------------------------------------
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entity zpu_wb_top is
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generic (
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dat_w: integer := 32;
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adr_w: integer := 16;
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sel_w: integer := 4
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);
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port (
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clk: in std_logic;
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rst: in std_logic;
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enb: in std_logic;
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-- wishbone interface
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dat_i: in std_logic_vector(dat_w-1 downto 0);
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ack_i: in std_logic;
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adr_o: out std_logic_vector(adr_w-1 downto 0);
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sel_o: out std_logic_vector(sel_w-1 downto 0);
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we_o: out std_logic;
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dat_o: out std_logic_vector(dat_w-1 downto 0);
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cyc_o: out std_logic;
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stb_o: out std_logic;
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-- misc zpu signals
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interrupt: in std_logic;
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zpu_status: out std_logic_vector(63 downto 0)
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);
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end zpu_wb_top;
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architecture syn of zpu_wb_top is
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--wishbone interface (records)
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signal zpu_wb_i: wishbone_bus_out;
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signal zpu_wb_o: wishbone_bus_in;
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begin
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--assign wishbone signals to records
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zpu_wb_i.dat <= dat_i;
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zpu_wb_i.ack <= ack_i;
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adr_o <= zpu_wb_o.adr;
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sel_o <= zpu_wb_o.sel;
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we_o <= zpu_wb_o.we;
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dat_o <= zpu_wb_o.dat;
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cyc_o <= zpu_wb_o.cyc;
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stb_o <= zpu_wb_o.stb;
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--instantiate the zpu system
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zpu_system0: zpu_system port map(
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cpu_clk => clk,
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areset => rst,
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enable => enb,
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interrupt => interrupt,
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zpu_status => zpu_status,
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zpu_wb_i => zpu_wb_i,
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zpu_wb_o => zpu_wb_o
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);
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end architecture syn;
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