Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
@@ -0,0 +1,168 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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library work;
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use work.zpu_config.all;
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package zpupkg is
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-- This bit is set for read/writes to IO
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-- FIX!!! eventually this should be set to wordSize-1 so as to
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-- to make the address of IO independent of amount of memory
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-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
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-- libraries.
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constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
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constant maxAddrBit : integer := maxAddrBitIncIO-1;
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constant ioBit : integer := maxAddrBit+1;
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constant wordSize : integer := 2**wordPower;
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constant wordBytes : integer := wordSize/8;
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constant minAddrBit : integer := byteBits;
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-- configurable internal stack size. Probably going to be 16 after toolchain is done
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constant stack_bits : integer := 5;
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constant stack_size : integer := 2**stack_bits;
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component dualport_ram is
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port (clk : in std_logic;
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memAWriteEnable : in std_logic;
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memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
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memAWrite : in std_logic_vector(wordSize-1 downto 0);
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memARead : out std_logic_vector(wordSize-1 downto 0);
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memBWriteEnable : in std_logic;
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memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
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memBWrite : in std_logic_vector(wordSize-1 downto 0);
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memBRead : out std_logic_vector(wordSize-1 downto 0));
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end component;
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component dram is
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port (clk : in std_logic;
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areset : in std_logic;
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mem_writeEnable : in std_logic;
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mem_readEnable : in std_logic;
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mem_addr : in std_logic_vector(maxAddrBit downto 0);
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mem_write : in std_logic_vector(wordSize-1 downto 0);
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mem_read : out std_logic_vector(wordSize-1 downto 0);
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mem_busy : out std_logic;
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mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
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end component;
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component trace is
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port(
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clk : in std_logic;
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begin_inst : in std_logic;
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pc : in std_logic_vector(maxAddrBitIncIO downto 0);
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opcode : in std_logic_vector(7 downto 0);
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sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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memA : in std_logic_vector(wordSize-1 downto 0);
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memB : in std_logic_vector(wordSize-1 downto 0);
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busy : in std_logic;
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intSp : in std_logic_vector(stack_bits-1 downto 0)
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);
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end component;
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component zpu_core is
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port ( clk : in std_logic;
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areset : in std_logic;
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enable : in std_logic;
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mem_req : out std_logic;
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mem_we : out std_logic;
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mem_ack : in std_logic;
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mem_read : in std_logic_vector(wordSize-1 downto 0);
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mem_write : out std_logic_vector(wordSize-1 downto 0);
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out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
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mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
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interrupt : in std_logic;
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break : out std_logic;
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zpu_status : out std_logic_vector(63 downto 0));
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end component;
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component timer is
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port(
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clk : in std_logic;
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areset : in std_logic;
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sample : in std_logic;
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reset : in std_logic;
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counter : out std_logic_vector(63 downto 0));
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end component;
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component zpuio is
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port ( areset : in std_logic;
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cpu_clk : in std_logic;
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clk_status : in std_logic_vector(2 downto 0);
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cpu_din : in std_logic_vector(15 downto 0);
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cpu_a : in std_logic_vector(20 downto 0);
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cpu_we : in std_logic_vector(1 downto 0);
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cpu_re : in std_logic;
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cpu_dout : inout std_logic_vector(15 downto 0));
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end component;
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-- opcode decode constants
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constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
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constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
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constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
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constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
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constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
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constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
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constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
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constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
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constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
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constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
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constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
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constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
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constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
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constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
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constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
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constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
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constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
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constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
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constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
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constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
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constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
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constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
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constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
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constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
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constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
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constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
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constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
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constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
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constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
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constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
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constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
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constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
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constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
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constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
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constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
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constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
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constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
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constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
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constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
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constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
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constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
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constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
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constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
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constant OpCode_Size : integer := 8;
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end zpupkg;
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