miegl/b210-k7-fpga
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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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lib/xge/sim/verilog/xge_mac.prj
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verilog work ../../rtl/verilog/fault_sm.v -i ../../rtl/include
verilog work ../../rtl/verilog/generic_mem_small.v -i ../../rtl/include
verilog work ../../rtl/verilog/generic_mem_medium.v -i ../../rtl/include
verilog work ../../rtl/verilog/generic_fifo_ctrl.v -i ../../rtl/include
verilog work ../../rtl/verilog/generic_fifo.v -i ../../rtl/include
verilog work ../../rtl/verilog/meta_sync.v -i ../../rtl/include
verilog work ../../rtl/verilog/meta_sync_single.v -i ../../rtl/include
verilog work ../../rtl/verilog/rx_hold_fifo.v -i ../../rtl/include
verilog work ../../rtl/verilog/rx_data_fifo.v -i ../../rtl/include
verilog work ../../rtl/verilog/rx_dequeue.v -i ../../rtl/include
verilog work ../../rtl/verilog/rx_enqueue.v -i ../../rtl/include
verilog work ../../rtl/verilog/sync_clk_core.v -i ../../rtl/include
verilog work ../../rtl/verilog/sync_clk_wb.v -i ../../rtl/include
verilog work ../../rtl/verilog/sync_clk_xgmii_tx.v -i ../../rtl/include
verilog work ../../rtl/verilog/tx_hold_fifo.v -i ../../rtl/include
verilog work ../../rtl/verilog/tx_data_fifo.v -i ../../rtl/include
verilog work ../../rtl/verilog/tx_dequeue.v -i ../../rtl/include
verilog work ../../rtl/verilog/tx_enqueue.v -i ../../rtl/include
verilog work ../../rtl/verilog/wishbone_if.v -i ../../rtl/include
verilog work ../../rtl/verilog/xge_mac.v -i ../../rtl/include
verilog work ../../tbench/verilog/tb_xge_mac.v -i ../../rtl/include