Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "defines.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Define MDIO to add support for clause 22 and clause 45 MDIO interface
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`define MDIO
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// If WB clock is 62.5MHz and max MDC spec is 2.5MHz, then divide by 25
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//`define MDC_HALF_PERIOD 13 // Closest int to 12.5
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`define MDC_HALF_PERIOD 100
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// CPU Registers
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`define CPUREG_CONFIG0 8'h00
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`define CPUREG_INT_PENDING 8'h04
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`define CPUREG_INT_STATUS 8'h08
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`define CPUREG_INT_MASK 8'h0c
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//`ifdef MDIO
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`define CPUREG_MDIO_DATA 8'h10
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`define CPUREG_MDIO_ADDR 8'h14
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`define CPUREG_MDIO_OP 8'h18
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`define CPUREG_MDIO_CONTROL 8'h1c
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`define CPUREG_MDIO_STATUS 8'h1c
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`define CPUREG_GPIO 8'h20
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//`endif
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// Ethernet codes
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`define IDLE 8'h07
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`define PREAMBLE 8'h55
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`define SEQUENCE 8'h9c
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`define SFD 8'hd5
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`define START 8'hfb
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`define TERMINATE 8'hfd
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`define ERROR 8'hfe
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`define LINK_FAULT_OK 2'd0
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`define LINK_FAULT_LOCAL 2'd1
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`define LINK_FAULT_REMOTE 2'd2
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`define FAULT_SEQ_LOCAL 1'b0
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`define FAULT_SEQ_REMOTE 1'b1
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`define LOCAL_FAULT 8'd1
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`define REMOTE_FAULT 8'd2
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`define PAUSE_FRAME 48'h010000c28001
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`define LANE0 7:0
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`define LANE1 15:8
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`define LANE2 23:16
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`define LANE3 31:24
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`define LANE4 39:32
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`define LANE5 47:40
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`define LANE6 55:48
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`define LANE7 63:56
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`define TXSTATUS_NONE 8'h0
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`define TXSTATUS_EOP 3'd6
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`define TXSTATUS_SOP 3'd7
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`define RXSTATUS_NONE 8'h0
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`define RXSTATUS_ERR 3'd5
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`define RXSTATUS_EOP 3'd6
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`define RXSTATUS_SOP 3'd7
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//
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// FIFO Size: 8 * (2^AWIDTH) will be the size in bytes
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// 7 --> 128 entries, 1024 bytes for data fifo
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//
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`define TX_DATA_FIFO_AWIDTH 9
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`define RX_DATA_FIFO_AWIDTH 9
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//
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// FIFO Size: Holding FIFOs are 16 deep
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//
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`define TX_HOLD_FIFO_AWIDTH 4
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`define RX_HOLD_FIFO_AWIDTH 4
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// Memory types
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`define MEM_AUTO_SMALL 1
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`define MEM_AUTO_MEDIUM 2
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`define MEM_AUTO_XILINX 3
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// Changed system packet interface to big endian (12/12/2009)
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// Comment out to use legacy mode
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`define BIGENDIAN
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