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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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lib/wishbone/axi_stream_to_wb.v
+22 -17
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@@ -1,19 +1,7 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// AXI stream to/from wishbone
// Input is an axi stream which wites into a BRAM.
@@ -40,7 +28,7 @@ module axi_stream_to_wb
//-- the wishbone interface
input clk_i, input rst_i,
input we_i, input stb_i, input cyc_i, output reg ack_o,
input [AWIDTH-1:0] adr_i, input [31:0] dat_i, output [31:0] dat_o,
input [AWIDTH-1:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
//-- the axi stream interface input
input [63:0] rx_tdata,
@@ -60,10 +48,23 @@ module axi_stream_to_wb
output [31:0] debug_tx
);
reg stb_i_del;
always @(posedge clk_i) begin
if (rst_i) stb_i_del <= 0;
else stb_i_del <= stb_i;
end
reg ack_o_del;
always @(posedge clk_i) begin
if (rst_i) ack_o_del <= 0;
else ack_o_del <= ack_o;
end
//drive the ack signal
always @(posedge clk_i) begin
if (rst_i) ack_o <= 0;
else ack_o <= stb_i & ~ack_o;
if (rst_i) ack_o <= 0;
else if (we_i) ack_o <= stb_i & ~ack_o;
else ack_o <= stb_i & stb_i_del & ~ack_o & ~ack_o_del;
end
//control registers, status
@@ -119,7 +120,11 @@ module axi_stream_to_wb
);
//select the data source, status, or upper/lower 32 from bram
assign dat_o = ctrl_addressed ? status : ((!adr_i[2])? rx_bram_data64[63:32]: rx_bram_data64[31:0]);
wire [31:0] dat_o_pipeline;
assign dat_o_pipeline = ctrl_addressed ? status : ((!adr_i[2])? rx_bram_data64[63:32]: rx_bram_data64[31:0]);
always @(posedge clk_i) begin
dat_o <= dat_o_pipeline;
end
//------------------------------------------------------------------
//-- block ram interface between wb and output stream