Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
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//
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// Copyright 2011 Ettus Research LLC
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//
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module simple_gemac_rx
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(input reset,
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input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
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output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
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input [47:0] ucast_addr, input [47:0] mcast_addr,
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input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
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output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
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output [31:0] debug );
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localparam RX_IDLE = 0;
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localparam RX_PREAMBLE = 1;
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localparam RX_FRAME = 2;
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localparam RX_GOODFRAME = 3;
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localparam RX_DO_PAUSE = 4;
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localparam RX_ERROR = 5;
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localparam RX_DROP = 6;
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localparam RX_PAUSE = 16;
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localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
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localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
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localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
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localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
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localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
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localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
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localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
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reg [7:0] rxd_d1;
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reg rx_dv_d1, rx_er_d1;
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assign rx_clk = GMII_RX_CLK;
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always @(posedge rx_clk)
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begin
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rx_dv_d1 <= GMII_RX_DV;
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rx_er_d1 <= GMII_RX_ER;
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rxd_d1 <= GMII_RXD;
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end
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reg [7:0] rx_state;
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wire [7:0] rxd_del;
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wire rx_dv_del, rx_er_del;
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reg go_filt;
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wire match_crc;
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wire clear_crc = rx_state == RX_IDLE;
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wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
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localparam DELAY = 6;
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delay_line #(.WIDTH(10)) rx_delay
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(.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
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always @(posedge rx_clk)
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if(reset)
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rx_ack <= 0;
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else
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rx_ack <= (rx_state == RX_GOODFRAME);
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wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
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wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
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(pass_bcast & is_bcast) | (pass_pause & is_pause);
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assign rx_data = rxd_del;
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assign rx_error = (rx_state == RX_ERROR);
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always @(posedge rx_clk)
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if(reset)
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rx_valid <= 0;
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else if(keep_packet)
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rx_valid <= 1;
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else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR))
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rx_valid <= 0;
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address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
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.address(ucast_addr), .match(is_ucast), .done());
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address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
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.address(mcast_addr), .match(is_mcast), .done());
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address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
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.address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
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address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
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.address(48'h0180_c200_0001), .match(is_pause), .done());
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address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
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.match(is_any_ucast), .done());
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always @(posedge rx_clk)
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go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
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reg [15:0] pkt_len_ctr;
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always @(posedge rx_clk)
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if(reset |(rx_state == RX_IDLE))
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pkt_len_ctr <= 0;
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else
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pkt_len_ctr <= pkt_len_ctr + 1;
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localparam MIN_PAUSE_LEN = 71; // 6
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wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN);
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always @(posedge rx_clk)
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if(reset)
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rx_state <= RX_IDLE;
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else
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if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE))
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rx_state <= RX_ERROR;
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else
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case(rx_state)
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RX_IDLE :
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if(rx_dv_d1)
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if(rxd_d1 == 8'h55)
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rx_state <= RX_PREAMBLE;
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else
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rx_state <= RX_ERROR;
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RX_PREAMBLE :
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if(~rx_dv_d1)
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rx_state <= RX_ERROR;
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else if(rxd_d1 == 8'hD5)
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rx_state <= RX_FRAME;
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else if(rxd_d1 != 8'h55)
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rx_state <= RX_ERROR;
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RX_FRAME :
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if(is_pause)
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rx_state <= RX_PAUSE;
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else if(~rx_dv_d1)
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if(match_crc)
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rx_state <= RX_GOODFRAME;
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else
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rx_state <= RX_ERROR;
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RX_PAUSE_CHK88 :
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if(rxd_d1 != 8'h88)
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rx_state <= RX_DROP;
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else
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rx_state <= RX_PAUSE_CHK08;
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RX_PAUSE_CHK08 :
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if(rxd_d1 != 8'h08)
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rx_state <= RX_DROP;
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else
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rx_state <= RX_PAUSE_CHK00;
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RX_PAUSE_CHK00 :
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if(rxd_d1 != 8'h00)
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rx_state <= RX_DROP;
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else
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rx_state <= RX_PAUSE_CHK01;
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RX_PAUSE_CHK01 :
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if(rxd_d1 != 8'h01)
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rx_state <= RX_DROP;
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else
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rx_state <= RX_PAUSE_STORE_MSB;
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RX_PAUSE_WAIT_CRC :
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if(pkt_long_enough)
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if(match_crc)
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rx_state <= RX_DO_PAUSE;
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else
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rx_state <= RX_DROP;
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RX_DO_PAUSE :
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rx_state <= RX_IDLE;
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RX_GOODFRAME :
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rx_state <= RX_IDLE;
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RX_DROP, RX_ERROR :
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if(~rx_dv_d1)
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rx_state <= RX_IDLE;
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default
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rx_state <= rx_state + 1;
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endcase // case (rx_state)
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assign pause_rcvd = (rx_state == RX_DO_PAUSE);
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crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
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.data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
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always @(posedge rx_clk)
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if(reset)
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pause_quanta_rcvd <= 0;
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else if(rx_state == RX_PAUSE_STORE_MSB)
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pause_quanta_rcvd[15:8] <= rxd_d1;
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else if(rx_state == RX_PAUSE_STORE_LSB)
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pause_quanta_rcvd[7:0] <= rxd_d1;
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assign debug = rx_state;
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endmodule // simple_gemac_rx
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