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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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lib/sim/tx/.gitignore
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*.log
*.exe
*.vcd
isim*
fuse*
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
Executable
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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
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initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h4);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 8 triggers Intra burst seq_id error
send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
Executable
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
Executable
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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
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initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h2);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 8 triggers Intra burst seq_id error
send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_policy_next_burst/run_isim
Executable
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
Executable
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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
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initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h4);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Inter burst sequence error
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_policy_next_packet/run_isim
Executable
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
Executable
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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
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initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h2);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Inter burst sequence error
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin