Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,16 @@
+iverilog -y . \
+-D SIM_SCRIPT=true \
+../../../vita/new_tx_tb.v \
+-y ../../../vita/ \
+-y ../../../fifo/ \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
+-y ../../../control/ \
+-y ../../../timing/ \
+-y ../../../dsp/  \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
+-y ../../../../../usrp2/models/ \
+-Wall \
+-o new_tx_tb.exe
+
+./new_tx_tb.exe
+