Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
@@ -0,0 +1,16 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../packet_proc/eth_dispatch_tb.v
+vlogcomp -work work ../../packet_proc/eth_dispatch.v
+vlogcomp -work work ../../fifo/axi_fifo_short.v
+vlogcomp -work work ../../fifo/axi_fifo.v
+vlogcomp -work work ../../control/ram_2port.v
+vlogcomp -work work ../../control/setting_reg.v
+vlogcomp -work work ../../sim/axi_probe_tb.v
+
+
+
+
+fuse work.eth_dispatch_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o eth_dispatch_tb.exe
+
+# run the simulation scrip
+./eth_dispatch_tb.exe -gui #-tclbatch simcmds.tcl