miegl/b210-k7-fpga
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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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lib/sim/axi_fifo/run_sim
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../fifo/axi_fifo_tb.v
vlogcomp -work work ../../fifo/axi_fifo.v
vlogcomp -work work ../../control/ram_2port.v
fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe
# run the simulation scrip
./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl