Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
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Executable
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iverilog \
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-s axi_crossbar_tb \
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-y ~/XILINX_verilog/ISE/verilog/src/unisims \
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-o axi_crossbar_tb \
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~/XILINX_verilog/ISE/verilog/src/glbl.v \
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../../control/axi_crossbar_tb.v \
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../../control/axi_crossbar.v \
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../../control/axi_slave_mux.v \
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../../control/axi_fifo_header.v \
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../../control/arb_qualify_master.v \
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../../control/setting_reg.v \
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../../fifo/monitor_axi_fifo.v \
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../../fifo/axi_fifo_short.v
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#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
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# run the simulation scrip
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#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
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