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Pushing the bulk of UHD-3.7.0 code.

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Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
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lib/sim/axi_chdr_tb.v
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//
// CHDR friendly AXI stream input
//
reg [63:0] i_tdata;
reg i_tlast;
reg i_tvalid;
wire i_tready;
//
// CHDR friendly AXI Stream output
//
wire [63:0] o_tdata;
wire o_tlast;
wire o_tvalid;
reg o_tready;
//
// This task sends a burst of CHDR packets with populated headers.
// The burst payload contains a ramp of incrementing amplitude strating at 0.
//
task send_ramp;
input [31:0] burst_count; // Number of CHDR packets in burst.
input [31:0] len; // Length of each CHDR packet in 32bit words.
input [63:0] send_time; // Optional 64 VITA time for first packet of burst.
input [11:0] start_seqnum; // Seeds initial seqnum of this burst.
input send_at; // Set this to include VITA time on first poacket in burst.
input [31:0] sid; // SID value for all CHDR packets in burst
reg [31:0] data;
reg [11:0] seqno;
begin
seqno = start_seqnum;
data = 0;
send_packet(len, data, send_time, seqno, (burst_count==1), send_at, sid);
seqno = seqno + 1;
data <= data + len;
if(burst_count > 2)
repeat (burst_count - 2)
begin
send_packet(len, data, 64'h0, seqno, 0, 0, sid);
seqno = seqno + 1;
data <= data + len;
end
if(burst_count > 1)
send_packet(len, data, 64'h0, seqno, 1, 0, sid);
end
endtask // send_ramp
//
// This task sends a burst of CHDR packets with populated headers
// Each packets payload is an incrementing count re-starting at the start value.
//
task send_burst;
input [31:0] burst_count; // Number of CHDR packets in burst.
input [31:0] len; // Length of each CHDR packet in 32bit words.
input [31:0] start_data; // Seed initial sample magnitude.
input [63:0] send_time; // Optional 64 VITA time for first packet of burst.
input [11:0] start_seqnum; // Seeds initial seqnum of this burst.
input send_at; // Set this to include VITA time on first packet in burst.
input [31:0] sid; // SID value for all CHDR packets in burst
reg [11:0] seqno;
begin
seqno = start_seqnum;
send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
seqno = seqno + 1;
if(burst_count > 2)
repeat (burst_count - 2)
begin
send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
seqno = seqno + 1;
end
if(burst_count > 1)
send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
end
endtask // send_burst
//
// Sends a single CHDR packet. Has valid CHDR headers and incrementing sample payload.
// Alter this with care, many other tasks depend on this task.
//
task send_packet;
input [31:0] len;
input [31:0] start_data;
input [63:0] send_time;
input [11:0] pkt_seqnum;
input eob;
input send_at;
input [31:0] sid;
reg [31:0] samp0, samp1;
begin
// Send a packet
samp0 <= start_data;
samp1 <= start_data + 1;
@(posedge clk);
i_tlast <= 0;
i_tdata <= { 1'b0, 1'b0 /*trl*/, send_at, eob, pkt_seqnum, len[15:0]+16'd2+send_at+send_at, sid };
i_tvalid <= 1;
@(posedge clk)
if(send_at)
begin
i_tdata <= send_time;
@(posedge clk);
end
repeat (len[31:1]+len[0]-1)
begin
i_tdata <= {samp0,samp1};
samp0 <= samp0 + 2;
samp1 <= samp1 + 2;
@(posedge clk);
end
i_tdata <= {samp0,samp1};
i_tlast <= 1'b1;
@(posedge clk);
i_tvalid <= 0;
@(posedge clk);
end
endtask // send_packet
//
// These 2 tasks stuff an incrementing count and then check for a match
// on Egress to test CHDR blocks for transparaent data pass through.
// CHDR fields are not inteligently populated by these tasks.
//
task send_raw_packet;
input [31:0] len;
reg [63:0] data;
begin
data = 0;
@(posedge clk);
repeat (len-1) begin
i_tlast <= 0;
i_tdata <= data;
i_tvalid <= 1;
@(posedge clk);
while (~i_tready) @(posedge clk);
data = data + 1;
end
i_tlast <= 1;
i_tdata <= data;
i_tvalid <= 1;
@(posedge clk);
while (~i_tready) @(posedge clk);
i_tvalid <= 0;
@(posedge clk);
end
endtask // send_raw_packet
task receive_raw_packet;
input [31:0] len;
output fail;
reg [63:0] data;
begin
data = 0;
fail = 0;
@(posedge clk);
repeat (len-1) begin
o_tready = 1;
@(posedge clk);
while (~o_tvalid) @(posedge clk);
//$display("Data = %d, o_tdata = %d, o_tlast = %d",data,o_tdata,o_tlast);
fail = fail || (data != o_tdata);
fail = fail || (o_tlast == 1);
data = data + 1;
end
o_tready = 1;
@(posedge clk);
while (~o_tvalid) @(posedge clk);
//$display("Data = %d, o_tdata = %d, o_tlast = %d",data,o_tdata,o_tlast);
fail = fail || (data != o_tdata);
fail = fail || (o_tlast == 0);
o_tready = 0;
@(posedge clk);
if (fail) $display("receive_raw_packet size %d failed",len);
end
endtask // receive_raw_packet
lib/sim/axi_crossbar/run_iverilog
Executable
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iverilog \
-s axi_crossbar_tb \
-y ~/XILINX_verilog/ISE/verilog/src/unisims \
-o axi_crossbar_tb \
~/XILINX_verilog/ISE/verilog/src/glbl.v \
../../control/axi_crossbar_tb.v \
../../control/axi_crossbar.v \
../../control/axi_slave_mux.v \
../../control/axi_fifo_header.v \
../../control/arb_qualify_master.v \
../../control/setting_reg.v \
../../fifo/monitor_axi_fifo.v \
../../fifo/axi_fifo_short.v
#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
# run the simulation scrip
#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
lib/sim/axi_crossbar/run_sim
Executable
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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../control/axi_crossbar_tb.v
vlogcomp -work work ../../control/axi_crossbar.v
vlogcomp -work work ../../control/axi_slave_mux.v
vlogcomp -work work ../../control/axi_forwarding_cam.v
vlogcomp -work work ../../control/setting_reg.v
vlogcomp -work work ../../fifo/monitor_axi_fifo.v
vlogcomp -work work ../../fifo/axi_fifo_short.v
fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
# run the simulation scrip
./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
lib/sim/axi_crossbar/simulation_script.v
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initial $dumpfile("axi_crossbar_tb.vcd");
initial $dumpvars(0,axi_crossbar_tb);
reg [15:0] x;
initial
begin
@(posedge clk);
reset <= 1;
repeat (5) @(posedge clk);
@(posedge clk);
reset <= 0;
@(posedge clk);
// 2x2 Switch so only mask one bit of SID for route dest.
// Each slave must have a unique address, logic doesn't check for this.
//
// Network Addr 0 & 1 go to Slave 0.
write_setting_bus(0,0); // 0.X goes to Port 0
write_setting_bus(1,0); // 1.X goes to Port 0
// Local Addr = 2
write_setting_bus(512,2);
// Host Addr 0 & 2 go to Slave 0...
write_setting_bus(256,0); // 2.0 goes to Port 0
write_setting_bus(258,0); // 2.2 goes to Port 0
// ...Host Addr 1 & 3 go to Slave 1...
write_setting_bus(257,1); // 2.1 goes to Port 1
write_setting_bus(259,1); // 2.3 goes to Port 1
//
@(posedge clk);
fork
begin
// Master0, addr 0.0 to Slave0
enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0});
// Master0, addr 2.0 to Slave0
enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0});
// Master0, addr 2.3 to Slave1
enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3});
// Master0, addr 2.2 to Slave0
enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2});
end
begin
// Master1, addr 1.0 to Slave0
enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0});
// Master1, addr 2.1 to Slave1
enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1});
// Master1, addr 2.3 to Slave1
enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3});
end
join
repeat (1000) @(posedge clk);
$finish;
end // initial begin
lib/sim/axi_dram_fifo/default.wcfg
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="axi_dram_fifo_tb" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="38" />
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">count_rx[31:0]</obj_property>
<obj_property name="ObjectShortName">count_rx[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">count_tx[31:0]</obj_property>
<obj_property name="ObjectShortName">count_tx[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_tlast</obj_property>
<obj_property name="ObjectShortName">i_tlast</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_tvalid</obj_property>
<obj_property name="ObjectShortName">i_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_tready</obj_property>
<obj_property name="ObjectShortName">i_tready</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">input_state[2:0]</obj_property>
<obj_property name="ObjectShortName">input_state[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">write_ctrl_ready</obj_property>
<obj_property name="ObjectShortName">write_ctrl_ready</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">write_ctrl_valid</obj_property>
<obj_property name="ObjectShortName">write_ctrl_valid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1">
<obj_property name="ElementShortName">occupied_input[5:0]</obj_property>
<obj_property name="ObjectShortName">occupied_input[5:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="group92" type="group">
<obj_property name="label">INPUT TIMEOUT</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property>
<obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">input_timeout_reset</obj_property>
<obj_property name="ObjectShortName">input_timeout_reset</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">input_timeout_triggered</obj_property>
<obj_property name="ObjectShortName">input_timeout_triggered</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group60" type="group">
<obj_property name="label">AXI_WADDR</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">write_addr_state[1:0]</obj_property>
<obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awvalid</obj_property>
<obj_property name="ObjectShortName">m_axi_awvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_awready</obj_property>
<obj_property name="ObjectShortName">m_axi_awready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">write_data_count[3:0]</obj_property>
<obj_property name="ObjectShortName">write_data_count[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="group61" type="group">
<obj_property name="label">AXI_WDATA</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_wlast</obj_property>
<obj_property name="ObjectShortName">m_axi_wlast</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_wvalid</obj_property>
<obj_property name="ObjectShortName">m_axi_wvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_wready</obj_property>
<obj_property name="ObjectShortName">m_axi_wready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group62" type="group">
<obj_property name="label">AXI_WRESP</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_bvalid</obj_property>
<obj_property name="ObjectShortName">m_axi_bvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_bready</obj_property>
<obj_property name="ObjectShortName">m_axi_bready</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ff00</obj_property>
<obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
<obj_property name="ElementShortName">space[10:0]</obj_property>
<obj_property name="ObjectShortName">space[10:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
<obj_property name="ElementShortName">occupied[10:0]</obj_property>
<obj_property name="ObjectShortName">occupied[10:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ffff</obj_property>
</wvobject>
<wvobject fp_name="group63" type="group">
<obj_property name="label">AXI_RADDR</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">read_addr_state[1:0]</obj_property>
<obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arvalid</obj_property>
<obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_arready</obj_property>
<obj_property name="ObjectShortName">m_axi_arready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group64" type="group">
<obj_property name="label">AXI_RDATA</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">read_data_state[1:0]</obj_property>
<obj_property name="ObjectShortName">read_data_state[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property>
<obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rlast</obj_property>
<obj_property name="ObjectShortName">m_axi_rlast</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rvalid</obj_property>
<obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">m_axi_rready</obj_property>
<obj_property name="ObjectShortName">m_axi_rready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">read_ctrl_valid</obj_property>
<obj_property name="ObjectShortName">read_ctrl_valid</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">read_ctrl_ready</obj_property>
<obj_property name="ObjectShortName">read_ctrl_ready</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">read_data_count[3:0]</obj_property>
<obj_property name="ObjectShortName">read_data_count[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">output_state[2:0]</obj_property>
<obj_property name="ObjectShortName">output_state[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1">
<obj_property name="ElementShortName">space_output[5:0]</obj_property>
<obj_property name="ObjectShortName">space_output[5:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="group80" type="group">
<obj_property name="label">DRAM FIFO OUT</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property>
<obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tvalid_output</obj_property>
<obj_property name="ObjectShortName">o_tvalid_output</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tready_output</obj_property>
<obj_property name="ObjectShortName">o_tready_output</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">update_write</obj_property>
<obj_property name="ObjectShortName">update_write</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">write_count[3:0]</obj_property>
<obj_property name="ObjectShortName">write_count[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">update_read</obj_property>
<obj_property name="ObjectShortName">update_read</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">read_count[3:0]</obj_property>
<obj_property name="ObjectShortName">read_count[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="group68" type="group">
<obj_property name="label">Output TImeout</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property>
<obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">output_timeout_reset</obj_property>
<obj_property name="ObjectShortName">output_timeout_reset</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">output_timeout_triggered</obj_property>
<obj_property name="ObjectShortName">output_timeout_triggered</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group76" type="group">
<obj_property name="label">Extract TLAST</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property>
<obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tvalid_i0</obj_property>
<obj_property name="ObjectShortName">o_tvalid_i0</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tready_i0</obj_property>
<obj_property name="ObjectShortName">o_tready_i0</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property>
<obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tvalid_i1</obj_property>
<obj_property name="ObjectShortName">o_tvalid_i1</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tready_i1</obj_property>
<obj_property name="ObjectShortName">o_tready_i1</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tlast_i1</obj_property>
<obj_property name="ObjectShortName">o_tlast_i1</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tlast</obj_property>
<obj_property name="ObjectShortName">o_tlast</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tvalid</obj_property>
<obj_property name="ObjectShortName">o_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_tready</obj_property>
<obj_property name="ObjectShortName">o_tready</obj_property>
</wvobject>
</wave_config>
lib/sim/axi_dram_fifo/run_isim
Executable
+16
View File
@@ -0,0 +1,16 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
vlogcomp -work work --sourcelibext .v \
--sourcelibdir ../../axi \
--sourcelibdir ../../fifo \
--sourcelibdir ../../../top/b250/coregen \
../../axi/axi_dram_fifo_tb.v
fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
# run the simulation scrip
./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl
#./source_flow_control_tb.exe
lib/sim/axi_fifo/run_sim
Executable
+11
View File
@@ -0,0 +1,11 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../fifo/axi_fifo_tb.v
vlogcomp -work work ../../fifo/axi_fifo.v
vlogcomp -work work ../../control/ram_2port.v
fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe
# run the simulation scrip
./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl
lib/sim/axi_probe_tb.v
+238
View File
@@ -0,0 +1,238 @@
//
// Copyright 2012 Ettus Research LLC
//
//
// This module is a SIMULATION ONLY bus monitor that probes AXI4-STREAM bus
// that transfer ETTUS non-CHDR VITA49.0 data, providing logging and diagnostoic info.
//
module axi_probe_tb
#(
parameter FILENAME="probe.txt",
parameter VITA_PORT0=0, // UDP ports to identify VITA
parameter VITA_PORT1=0, // UDP ports to identify VITA
parameter START_AT_VRL=0 // Flags already stripped back to VRL.
)
(
input clk,
input reset,
input clear,
input [63:0] tdata,
input tvalid,
input tready,
input tlast
);
localparam ARP = 16'h0806;
localparam IPv4 = 16'h0800;
localparam UDP = 8'h11;
localparam VRL = 1;
localparam WAIT_SOF = 0;
localparam LINE1 = 1;
localparam LINE2 = 2;
localparam LINE3 = 3;
localparam LINE4 = 4;
localparam LINE5 = 5;
localparam LINE6 = 6;
localparam LINE7 = 7;
localparam WAIT_EOF = 15;
reg [3:0] out_state;
reg [63:0] last_line;
reg [15:0] eth_proto;
reg [7:0] ip_proto;
reg vita_proto;
integer dump_file;
initial
begin
dump_file = $fopen(FILENAME,"w");
end
//
// Monitor packets leaving FIFO
//
always @(posedge clk)
if (reset | clear) begin
out_state <= WAIT_SOF;
end else
case(out_state)
//
// After RESET or the EOF of previous packet, the first cycle with
// output valid asserted is the SOF and presents the Header word.
// The cycle following the concurrent presentation of asserted output
// valid and output ready presents the word following the header.
//
WAIT_SOF:
if (tvalid && tready) begin
last_line <= 0;
eth_proto <= 0;
ip_proto <= 0;
vita_proto <= 0;
$fdisplay(dump_file,"------------------------------------------");
$fdisplay(dump_file,"Time = %1d",$time);
if (START_AT_VRL) begin
if (tdata[63:32] == "VRLP") begin
$fdisplay(dump_file,"VRL VITA49 PAYLOAD");
vita_proto <= VRL;
end
out_state <= LINE7;
end
else out_state <= LINE1;
last_line <= tdata;
end else begin
out_state <= WAIT_SOF;
end
//
LINE1: if (tvalid && tready) begin
$fdisplay(dump_file,"Dst MAC: %x:%x:%x:%x:%x:%x",
last_line[15:8],last_line[7:0],tdata[63:56],tdata[55:48],tdata[47:40],tdata[39:32]);
last_line = tdata;
out_state <= LINE2;
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end
//
LINE2: if (tvalid && tready) begin
$fdisplay(dump_file,"Src MAC: %x:%x:%x:%x:%x:%x",
last_line[31:24],last_line[23:16],last_line[15:8],last_line[7:0],
tdata[63:56],tdata[55:48]);
eth_proto = tdata[47:32];
// Protocol??
if (tdata[47:32] == ARP) begin
//ARP
$fdisplay(dump_file,"ARP packet");
if (tdata[31:16] == 'h0001)
$fdisplay(dump_file,"HTYPE = 1 (Ethernet)");
if (tdata[31:16] == 'h0800)
$fdisplay(dump_file,"PTYPE = 0x0800 (IPv4)");
out_state <= LINE3;
end else if (tdata[47:32] == IPv4) begin
// IPv4
$fdisplay(dump_file,"IPv4 packet");
$fdisplay(dump_file,"Packet Length: %1d",tdata[15:0]);
out_state <= LINE3;
end else
out_state <= WAIT_EOF;
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // case: LINE2
//
LINE3:
if (tvalid && tready) begin
// Protocol??
if (eth_proto == ARP) begin
$fdisplay(dump_file,"HLEN: %d PLEN: %d",tdata[63:56],tdata[55:48]);
if (tdata[47:32] == 1) $fdisplay(dump_file,"Operation: ARP REQUEST");
else if (tdata[47:32] == 2) $fdisplay(dump_file,"Operation: ARP REPLY");
else $fdisplay(dump_file,"Operation: UNKNOWN");
last_line = tdata;
// out_state <= LINE4;
out_state <= WAIT_EOF; // Add further ARP decode later if desired.
end else if (eth_proto == IPv4) begin
ip_proto = tdata[23:16];
if (tdata[23:16] == UDP) $fdisplay(dump_file,"IPv4 Protocol: UDP");
else $fdisplay(dump_file,"IPv4 Protocol: %x",tdata[23:16]);
out_state <= LINE4;
end else
out_state <= WAIT_EOF;
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // if (tvalid && tready)
//
LINE4:
if (tvalid && tready) begin
// Protocol??
if (eth_proto == IPv4) begin
$fdisplay(dump_file,"IP Src Address: %1d.%1d.%1d.%1d IP Dst Address: %1d.%1d.%1d.%1d",
tdata[63:56],tdata[55:48],tdata[47:40],tdata[39:32],
tdata[31:24],tdata[23:16],tdata[15:8],tdata[7:0]);
if (ip_proto == UDP)
out_state <= LINE5;
else
out_state <= WAIT_EOF;
end
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // if (tvalid && tready)
//
LINE5:
if (tvalid && tready) begin
// Protocol??
if (ip_proto == UDP) begin
$fdisplay(dump_file,"UDP Src Port: %d UDP Dst Port: %d",
tdata[63:48],tdata[47:32]);
$fdisplay(dump_file,"UDP Length: %1d",tdata[31:16]);
last_line = tdata;
out_state <= LINE6;
end
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // if (tvalid && tready)
//
LINE6:
if (tvalid && tready) begin
// Protocol??
if (tdata[63:32] == "VRLP") begin
$fdisplay(dump_file,"VRL VITA49 PAYLOAD");
// Expand VITA decode later
vita_proto <= VRL;
out_state <= LINE7;
end
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // if (tvalid && tready)
//
LINE7:
if (tvalid && tready) begin
// Protocol??
if (vita_proto == VRL) begin
$fdisplay(dump_file,"VRT: Packet Size: %1d StreamID: %x",tdata[47:32],tdata[31:0]);
out_state <= WAIT_EOF;
end
if (tlast) begin
$fdisplay(dump_file,"------------------------------------------");
out_state <= WAIT_SOF;
end
end // if (tvalid && tready)
//
// EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
//
WAIT_EOF:
if (tlast && tvalid && tready) begin
out_state <= WAIT_SOF;
end else begin
out_state <= WAIT_EOF;
end
endcase // case(in_state)
endmodule // axi_probe_tb
lib/sim/eth_dispatch/default.wcfg
+220
View File
@@ -0,0 +1,220 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="eth_dispatch_tb" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="47" />
<wvobject fp_name="/eth_dispatch_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/set_stb" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_stb</obj_property>
<obj_property name="ObjectShortName">set_stb</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/set_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">set_addr[15:0]</obj_property>
<obj_property name="ObjectShortName">set_addr[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/set_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">set_data[31:0]</obj_property>
<obj_property name="ObjectShortName">set_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/in_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">in_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/in_tuser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_tuser[3:0]</obj_property>
<obj_property name="ObjectShortName">in_tuser[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/in_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tvalid</obj_property>
<obj_property name="ObjectShortName">in_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/in_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tready</obj_property>
<obj_property name="ObjectShortName">in_tready</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/in_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tlast</obj_property>
<obj_property name="ObjectShortName">in_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/vita_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vita_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">vita_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/vita_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vita_tvalid</obj_property>
<obj_property name="ObjectShortName">vita_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/vita_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vita_tready</obj_property>
<obj_property name="ObjectShortName">vita_tready</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/vita_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vita_tlast</obj_property>
<obj_property name="ObjectShortName">vita_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/zpu_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">zpu_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">zpu_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/zpu_tuser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">zpu_tuser[3:0]</obj_property>
<obj_property name="ObjectShortName">zpu_tuser[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/zpu_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">zpu_tvalid</obj_property>
<obj_property name="ObjectShortName">zpu_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/zpu_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">zpu_tready</obj_property>
<obj_property name="ObjectShortName">zpu_tready</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/zpu_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">zpu_tlast</obj_property>
<obj_property name="ObjectShortName">zpu_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/xo_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">xo_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">xo_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/xo_tuser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">xo_tuser[3:0]</obj_property>
<obj_property name="ObjectShortName">xo_tuser[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/xo_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_tvalid</obj_property>
<obj_property name="ObjectShortName">xo_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/xo_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_tready</obj_property>
<obj_property name="ObjectShortName">xo_tready</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/xo_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_tlast</obj_property>
<obj_property name="ObjectShortName">xo_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/xo_pre_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">xo_pre_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">xo_pre_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/xo_pre_tuser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">xo_pre_tuser[3:0]</obj_property>
<obj_property name="ObjectShortName">xo_pre_tuser[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/xo_pre_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_pre_tlast</obj_property>
<obj_property name="ObjectShortName">xo_pre_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/xo_pre_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_pre_tvalid</obj_property>
<obj_property name="ObjectShortName">xo_pre_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/xo_pre_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">xo_pre_tready</obj_property>
<obj_property name="ObjectShortName">xo_pre_tready</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state[2:0]</obj_property>
<obj_property name="ObjectShortName">state[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/header_ram_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">header_ram_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">header_ram_addr[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/header_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">header_done</obj_property>
<obj_property name="ObjectShortName">header_done</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/out_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_tlast</obj_property>
<obj_property name="ObjectShortName">out_tlast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_eth_dst_addr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">is_eth_dst_addr</obj_property>
<obj_property name="ObjectShortName">is_eth_dst_addr</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_eth_broadcast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">is_eth_broadcast</obj_property>
<obj_property name="ObjectShortName">is_eth_broadcast</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_eth_type_ipv4" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">is_eth_type_ipv4</obj_property>
<obj_property name="ObjectShortName">is_eth_type_ipv4</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_ipv4_dst_addr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">is_ipv4_dst_addr</obj_property>
<obj_property name="ObjectShortName">is_ipv4_dst_addr</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_ipv4_proto_udp" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">is_ipv4_proto_udp</obj_property>
<obj_property name="ObjectShortName">is_ipv4_proto_udp</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/is_udp_dst_ports" type="array" db_ref_id="1">
<obj_property name="ElementShortName">is_udp_dst_ports[1:0]</obj_property>
<obj_property name="ObjectShortName">is_udp_dst_ports[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/my_mac" type="array" db_ref_id="1">
<obj_property name="ElementShortName">my_mac[47:0]</obj_property>
<obj_property name="ObjectShortName">my_mac[47:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/my_ip" type="array" db_ref_id="1">
<obj_property name="ElementShortName">my_ip[31:0]</obj_property>
<obj_property name="ObjectShortName">my_ip[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/my_port0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">my_port0[15:0]</obj_property>
<obj_property name="ObjectShortName">my_port0[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/my_port1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">my_port1[15:0]</obj_property>
<obj_property name="ObjectShortName">my_port1[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/axi_fifo_vita/rd_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rd_addr[9:0]</obj_property>
<obj_property name="ObjectShortName">rd_addr[9:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/axi_fifo_vita/empty_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">empty_reg</obj_property>
<obj_property name="ObjectShortName">empty_reg</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/axi_fifo_vita/read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">read</obj_property>
<obj_property name="ObjectShortName">read</obj_property>
</wvobject>
<wvobject fp_name="/eth_dispatch_tb/eth_dispatch_i/axi_fifo_vita/ram/dob" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dob[68:0]</obj_property>
<obj_property name="ObjectShortName">dob[68:0]</obj_property>
</wvobject>
</wave_config>
lib/sim/eth_dispatch/run_sim
Executable
+16
View File
@@ -0,0 +1,16 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../packet_proc/eth_dispatch_tb.v
vlogcomp -work work ../../packet_proc/eth_dispatch.v
vlogcomp -work work ../../fifo/axi_fifo_short.v
vlogcomp -work work ../../fifo/axi_fifo.v
vlogcomp -work work ../../control/ram_2port.v
vlogcomp -work work ../../control/setting_reg.v
vlogcomp -work work ../../sim/axi_probe_tb.v
fuse work.eth_dispatch_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o eth_dispatch_tb.exe
# run the simulation scrip
./eth_dispatch_tb.exe -gui #-tclbatch simcmds.tcl
lib/sim/eth_dispatch/simulation_script.v
+78
View File
@@ -0,0 +1,78 @@
initial $dumpfile("eth_dispatch_tb.vcd");
initial $dumpvars(0,eth_dispatch_tb);
reg [15:0] x;
localparam MAC=48'h010203040506;
localparam IP=(192<<24)|(168<<16)|2;
localparam PORT0=60000;
localparam PORT1=60001;
initial
begin
@(posedge clk);
reset <= 1;
repeat (5) @(posedge clk);
@(posedge clk);
reset <= 0;
@(posedge clk);
// Set my MAC address
write_setting_bus(0,MAC&32'hFFFFFFFF);
write_setting_bus(1,MAC>>32);
// Set my IP Address
write_setting_bus(2,IP);
// Set UDP ports for ViTA traffic
write_setting_bus(3,PORT1<<16|PORT0);
@(posedge clk);
enqueue_vita_pkt(MAC,IP,PORT0,10,0,{16'h0,8'hf,8'h5});
enqueue_vita_pkt(MAC,IP,16'h1234,10,0,{16'h0,8'h5,8'hc});
enqueue_vita_pkt(48'h223344556677,32'h02030405,16'h1234,10,0,{16'h0,8'hd,8'h7});
enqueue_arp_req(48'h112233445566,32'h09080706,MAC,IP);
/* -----\/----- EXCLUDED -----\/-----
// 2x2 Switch so only mask one bit of SID for route dest.
// Each slave must have a unique address, logic doesn't check for this.
//
// Network Addr 0 & 1 go to Slave 0.
write_setting_bus(0,0); // 0.X goes to Port 0
write_setting_bus(1,0); // 1.X goes to Port 0
// Local Addr = 2
write_setting_bus(512,2);
// Host Addr 0 & 2 go to Slave 0...
write_setting_bus(256,0); // 2.0 goes to Port 0
write_setting_bus(258,0); // 2.2 goes to Port 0
// ...Host Addr 1 & 3 go to Slave 1...
write_setting_bus(257,1); // 2.1 goes to Port 1
write_setting_bus(259,1); // 2.3 goes to Port 1
//
@(posedge clk);
fork
begin
// Master0, addr 0.0 to Slave0
enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0});
// Master0, addr 2.0 to Slave0
enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0});
// Master0, addr 2.3 to Slave1
enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3});
// Master0, addr 2.2 to Slave0
enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2});
end
begin
// Master1, addr 1.0 to Slave0
enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0});
// Master1, addr 2.1 to Slave1
enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1});
// Master1, addr 2.3 to Slave1
enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3});
end
join
-----/\----- EXCLUDED -----/\----- */
repeat (1000) @(posedge clk);
$finish;
end // initial begin
lib/sim/source_flow_control/test_window/default.wcfg
+114
View File
@@ -0,0 +1,114 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="source_flow_control_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="23" />
<wvobject fp_name="/source_flow_control_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/set_stb" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_stb</obj_property>
<obj_property name="ObjectShortName">set_stb</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/set_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">set_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">set_addr[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/set_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">set_data[31:0]</obj_property>
<obj_property name="ObjectShortName">set_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/in_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">in_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/in_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tlast</obj_property>
<obj_property name="ObjectShortName">in_tlast</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/in_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tvalid</obj_property>
<obj_property name="ObjectShortName">in_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/in_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_tready</obj_property>
<obj_property name="ObjectShortName">in_tready</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/out_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">out_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/out_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_tlast</obj_property>
<obj_property name="ObjectShortName">out_tlast</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/out_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_tvalid</obj_property>
<obj_property name="ObjectShortName">out_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/out_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_tready</obj_property>
<obj_property name="ObjectShortName">out_tready</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/fc_tdata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fc_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">fc_tdata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/fc_tvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fc_tvalid</obj_property>
<obj_property name="ObjectShortName">fc_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/fc_tready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fc_tready</obj_property>
<obj_property name="ObjectShortName">fc_tready</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/fc_tlast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fc_tlast</obj_property>
<obj_property name="ObjectShortName">fc_tlast</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/go_until_seqnum" type="array" db_ref_id="1">
<obj_property name="ElementShortName">go_until_seqnum[31:0]</obj_property>
<obj_property name="ObjectShortName">go_until_seqnum[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/current_seqnum" type="array" db_ref_id="1">
<obj_property name="ElementShortName">current_seqnum[31:0]</obj_property>
<obj_property name="ObjectShortName">current_seqnum[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/go" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">go</obj_property>
<obj_property name="ObjectShortName">go</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/window_size" type="array" db_ref_id="1">
<obj_property name="ElementShortName">window_size[31:0]</obj_property>
<obj_property name="ObjectShortName">window_size[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/window_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">window_reset</obj_property>
<obj_property name="ObjectShortName">window_reset</obj_property>
</wvobject>
<wvobject fp_name="/source_flow_control_tb/source_flow_control/always_go" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">always_go</obj_property>
<obj_property name="ObjectShortName">always_go</obj_property>
</wvobject>
</wave_config>
lib/sim/source_flow_control/test_window/run_isim
Executable
+16
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@@ -0,0 +1,16 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
vlogcomp -work work ../../../packet_proc/source_flow_control.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
fuse work.source_flow_control_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o source_flow_control_tb.exe
# run the simulation scrip
./source_flow_control_tb.exe -gui #-tclbatch simcmds.tcl
#./source_flow_control_tb.exe
lib/sim/source_flow_control/test_window/run_iverilog
Executable
+16
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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/.gitignore
+5
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@@ -0,0 +1,5 @@
*.log
*.exe
*.vcd
isim*
fuse*
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
Executable
+40
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@@ -0,0 +1,40 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
Executable
+16
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@@ -0,0 +1,16 @@
iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
+20
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@@ -0,0 +1,20 @@
initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h4);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 8 triggers Intra burst seq_id error
send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
Executable
+40
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@@ -0,0 +1,40 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
Executable
+16
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@@ -0,0 +1,16 @@
iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
+20
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@@ -0,0 +1,20 @@
initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h2);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 8 triggers Intra burst seq_id error
send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_policy_next_burst/run_isim
Executable
+40
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@@ -0,0 +1,40 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
Executable
+16
View File
@@ -0,0 +1,16 @@
iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
+25
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@@ -0,0 +1,25 @@
initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h4);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Inter burst sequence error
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin
lib/sim/tx/test_seq_error_policy_next_packet/run_isim
Executable
+40
View File
@@ -0,0 +1,40 @@
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
vlogcomp -work work ../../../dsp/duc_chain.v
vlogcomp -work work ../../../dsp/hb_interp.v
vlogcomp -work work ../../../dsp/small_hb_int.v
vlogcomp -work work ../../../dsp/cic_interp.v
vlogcomp -work work ../../../dsp/cic_int_shifter.v
vlogcomp -work work ../../../dsp/cic_strober.v
vlogcomp -work work ../../../dsp/cordic_stage.v
vlogcomp -work work ../../../dsp/cordic_z24.v
vlogcomp -work work ../../../dsp/clip.v
vlogcomp -work work ../../../dsp/round.v
vlogcomp -work work ../../../dsp/round_reg.v
vlogcomp -work work ../../../dsp/sign_extend.v
vlogcomp -work work ../../../dsp/add2_reg.v
vlogcomp -work work ../../../dsp/add2_and_round_reg.v
vlogcomp -work work ../../../dsp/srl.v
vlogcomp -work work ../../../dsp/acc.v
vlogcomp -work work ../../../dsp/clip_reg.v
vlogcomp -work work ../../../dsp/add2_and_round.v
vlogcomp -work work ../../../dsp/add2.v
vlogcomp -work work ../../../vita/new_tx_control.v
vlogcomp -work work ../../../vita/new_tx_deframer.v
vlogcomp -work work ../../../vita/tx_responder.v
vlogcomp -work work ../../../vita/context_packet_gen.v
vlogcomp -work work ../../../vita/trigger_context_pkt.v
vlogcomp -work work ../../../control/setting_reg.v
vlogcomp -work work ../../../control/ram_2port.v
vlogcomp -work work ../../../fifo/axi_fifo.v
vlogcomp -work work ../../../fifo/axi_mux4.v
vlogcomp -work work ../../../fifo/axi_fifo_short.v
vlogcomp -work work ../../../timing/time_compare.v
fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
# run the simulation scrip
#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
Executable
+16
View File
@@ -0,0 +1,16 @@
iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe
lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
+24
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@@ -0,0 +1,24 @@
initial
begin
tvalid <= 1'b0;
while(reset)
@(posedge clk);
write_setting_bus(SR_ERROR_POLICY,32'h2);
write_setting_bus(SR_PACKETS,32'h8000_0002);
write_setting_bus(SR_INTERP,32'h1);
// Burst of len 2
send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Inter burst sequence error
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
// Burst of 2
send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
end // initial begin