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fpga: x400: Add axi_inter_2x128_512_bd IP

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Original-commit: e88c447a1a890a38ee875c14ab55a713056709b9
This commit is contained in:
Wade Fife
2022-02-07 13:08:11 -07:00
parent 653c9bacf3
commit f5b6a04e5c
3 changed files with 449 additions and 0 deletions
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top/x400/ip/axi_inter_2x128_512_bd/Makefile.inc
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_2X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x128_512_bd/, \
axi_inter_2x128_512_bd.tcl \
)
IP_AXI_INTER_2X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
axi_inter_2x128_512_bd.tcl \
)
IP_AXI_INTER_2X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.bd \
)
BD_AXI_INTER_2X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
axi_inter_2x128_512_bd.bd.out \
axi_inter_2x128_512_bd/axi_inter_2x128_512_bd_ooc.xdc \
axi_inter_2x128_512_bd/synth/axi_inter_2x128_512_bd.v \
)
$(IP_AXI_INTER_2X128_512_BD_SRCS) $(BD_AXI_INTER_2X128_512_BD_OUTS) $(IP_AXI_INTER_2X128_512_BDTCL_SRCS): $(IP_AXI_INTER_2X128_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_2x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)