fpga: x400: Add axi_inter_2x128_512_bd IP
Original-commit: e88c447a1a890a38ee875c14ab55a713056709b9
This commit is contained in:
Wade Fife
@@ -9,6 +9,7 @@ include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc
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include $(IP_DIR)/ddr4_64bits/Makefile.inc
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include $(IP_DIR)/adc_100m_bd/Makefile.inc
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include $(IP_DIR)/adc_400m_bd/Makefile.inc
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@@ -30,6 +31,7 @@ $(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
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$(IP_AXI_INTER_2X128_512_BD_SRCS) \
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$(IP_ADC_100M_BD_SRCS) \
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$(IP_ADC_100M_HDL_SRCS) \
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$(IP_DAC_100M_BD_SRCS) \
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@@ -57,6 +59,7 @@ $(BD_X4XX_PS_RFDC_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \
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$(BD_AXI_INTER_2X128_512_BD_OUTS) \
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$(BD_ADC_100M_BD_OUTS) \
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$(BD_ADC_400M_BD_OUTS) \
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$(BD_DAC_100M_BD_OUTS) \
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@@ -0,0 +1,28 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_AXI_INTER_2X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x128_512_bd/, \
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axi_inter_2x128_512_bd.tcl \
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)
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IP_AXI_INTER_2X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
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axi_inter_2x128_512_bd.tcl \
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)
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IP_AXI_INTER_2X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
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axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.bd \
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)
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BD_AXI_INTER_2X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x128_512_bd/, \
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axi_inter_2x128_512_bd.bd.out \
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axi_inter_2x128_512_bd/axi_inter_2x128_512_bd_ooc.xdc \
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axi_inter_2x128_512_bd/synth/axi_inter_2x128_512_bd.v \
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)
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$(IP_AXI_INTER_2X128_512_BD_SRCS) $(BD_AXI_INTER_2X128_512_BD_OUTS) $(IP_AXI_INTER_2X128_512_BDTCL_SRCS): $(IP_AXI_INTER_2X128_512_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,axi_inter_2x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
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@@ -0,0 +1,418 @@
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################################################################
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# This is a generated script based on design: axi_inter_2x128_512_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source axi_inter_2x128_512_bd_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name axi_inter_2x128_512_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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# Add USER_COMMENTS on $design_name
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set_property USER_COMMENTS.comment_0 "Note 1: The ID width of the AXI interconnect (xbar) master changes depending on the axi_interconnect optimization strategy. It will be zero for 'minimize area' and non-zero for 'maximize performance'.
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Note 2: I have explicitly set ID width to 1 on the input ports to match our AXI master and to 4 on the output block to match the DRAM slave." [get_bd_designs $design_name]
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_crossbar:2.1\
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xilinx.com:ip:axi_dwidth_converter:2.1\
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xilinx.com:ip:axi_register_slice:2.1\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.PROTOCOL {AXI4} \
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] $M0_AXI
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set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {128} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {1} \
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CONFIG.HAS_CACHE {1} \
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CONFIG.HAS_LOCK {1} \
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CONFIG.HAS_PROT {1} \
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CONFIG.HAS_QOS {1} \
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CONFIG.HAS_REGION {1} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {1} \
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CONFIG.ID_WIDTH {1} \
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CONFIG.MAX_BURST_LENGTH {256} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {1} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $S0_AXI
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set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {128} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {1} \
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CONFIG.HAS_CACHE {1} \
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CONFIG.HAS_LOCK {1} \
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CONFIG.HAS_PROT {1} \
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CONFIG.HAS_QOS {1} \
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CONFIG.HAS_REGION {1} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {1} \
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CONFIG.ID_WIDTH {1} \
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CONFIG.MAX_BURST_LENGTH {256} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PHASE {0.000} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {1} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $S1_AXI
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# Create ports
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set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
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CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
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CONFIG.FREQ_HZ {350000000} \
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] $M0_AXI_ACLK
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set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_LOW} \
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] $M0_AXI_ARESETN
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set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
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CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
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CONFIG.FREQ_HZ {350000000} \
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] $S0_AXI_ACLK
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set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
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# Create instance: axi_crossbar_0, and set properties
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set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
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set_property -dict [ list \
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CONFIG.NUM_MI {1} \
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CONFIG.NUM_SI {2} \
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] $axi_crossbar_0
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# Create instance: axi_dwidth_converter_0, and set properties
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set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
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set_property -dict [ list \
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CONFIG.FIFO_MODE {1} \
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CONFIG.MI_DATA_WIDTH {256} \
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CONFIG.SI_DATA_WIDTH {128} \
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CONFIG.SYNCHRONIZATION_STAGES {3} \
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] $axi_dwidth_converter_0
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# Create instance: axi_dwidth_converter_1, and set properties
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set axi_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_1 ]
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set_property -dict [ list \
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CONFIG.FIFO_MODE {1} \
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CONFIG.MI_DATA_WIDTH {256} \
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CONFIG.SI_DATA_WIDTH {128} \
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CONFIG.SYNCHRONIZATION_STAGES {3} \
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] $axi_dwidth_converter_1
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# Create instance: axi_dwidth_converter_2, and set properties
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set axi_dwidth_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_2 ]
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set_property -dict [ list \
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CONFIG.ACLK_ASYNC {1} \
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CONFIG.FIFO_MODE {2} \
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||||
CONFIG.MI_DATA_WIDTH {512} \
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CONFIG.SI_DATA_WIDTH {256} \
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||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
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||||
] $axi_dwidth_converter_2
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||||
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||||
# Create instance: axi_register_slice_0, and set properties
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||||
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
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||||
set_property -dict [ list \
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||||
CONFIG.REG_AR {1} \
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||||
CONFIG.REG_AW {1} \
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||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_0
|
||||
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||||
# Create instance: axi_register_slice_1, and set properties
|
||||
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_1
|
||||
|
||||
# Create instance: axi_register_slice_2, and set properties
|
||||
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_2
|
||||
|
||||
# Create instance: axi_register_slice_3, and set properties
|
||||
set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_3
|
||||
|
||||
# Create instance: axi_register_slice_4, and set properties
|
||||
set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_4
|
||||
|
||||
# Create instance: axi_register_slice_5, and set properties
|
||||
set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ID_WIDTH {4} \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
] $axi_register_slice_5
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S0_AXI_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S1_AXI_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/M_AXI] [get_bd_intf_pins axi_register_slice_4/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/M_AXI] [get_bd_intf_pins axi_register_slice_5/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_register_slice_4/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_5/M_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_2/m_axi_aclk] [get_bd_pins axi_register_slice_5/aclk]
|
||||
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_2/m_axi_aresetn] [get_bd_pins axi_register_slice_5/aresetn]
|
||||
connect_bd_net -net S0_AXI_ACLK_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_dwidth_converter_1/s_axi_aclk] [get_bd_pins axi_dwidth_converter_2/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins axi_register_slice_4/aclk]
|
||||
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins axi_register_slice_4/aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
Reference in New Issue
Block a user