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fpga: tools: Fix HLS IP builder for Vivado 2021.1

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Original-commit: 9300a0718274ede56cda3f48e43c9f0e1df4674b
This commit is contained in:
Humberto Jimenez
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 959ce49389
commit f53e3f27fc
3 changed files with 7 additions and 12 deletions
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tools/scripts/setupenv_base.sh
+4
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@@ -170,6 +170,7 @@ if [[ ${VIVADO_VER^^} = "CMDLINE_ARG" ]]; then
fi
fi
export VIVADO_PATH=$VIVADO_BASE_PATH/$VIVADO_VER
export VIVADO_HLS_PATH=$VIVADO_BASE_PATH/../Vitis_HLS/$VIVADO_VER
echo "Setting up a ${BITNESS}-bit FPGA build environment for the ${DISPLAY_NAME}..."
#----------------------------------------------------------------------------
@@ -194,6 +195,9 @@ if [[ -e $VIVADO_PATH/.settings${BITNESS}-Vivado_Lab.sh ]]; then
else
$VIVADO_PATH/.settings${BITNESS}-Vivado.sh
fi
if [[ -e $(readlink -f $VIVADO_HLS_PATH)/.settings${BITNESS}-Vitis_HLS.sh ]]; then
$(readlink -f $VIVADO_HLS_PATH)/.settings${BITNESS}-Vitis_HLS.sh
fi
if [[ -e $(readlink -f $VIVADO_BASE_PATH/..)/DocNav/.settings${BITNESS}-DocNav.sh ]]; then
$(readlink -f $VIVADO_BASE_PATH/..)/DocNav/.settings${BITNESS}-DocNav.sh
fi