fpga: lib: Update xport_sv
- Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
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@@ -11,14 +11,14 @@
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - MTU: Log2 of the MTU of the packet in 64-bit words
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in 64-bit words) for the CPU egress path
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CPU egress path
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// - CHDR_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CHDR egress path
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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// - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
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// - PREAMBLE_BYTES: Number of bytes of Preamble expected
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// - ADD_SOF: Add a SOF indication into the tuser field
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// - ADD_SOF: Add a SOF indication into the tuser field of e2c
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// - SYNC: Set if MAC is not the same as bus_clk
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// - ENET_W: Width of the link to the Ethernet MAC
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// - CPU_W: Width of the CPU interface
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@@ -27,8 +27,8 @@
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module eth_ipv4_interface #(
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logic [15:0] PROTOVER = {8'd1, 8'd0},
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int MTU = 10,
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int CPU_FIFO_SIZE = MTU,
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int CPU_FIFO_SIZE = $clog2(8*1024),
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int CHDR_FIFO_SIZE = $clog2(8*1024),
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int NODE_INST = 0,
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int RT_TBL_SIZE = 6,
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int REG_AWIDTH = 14,
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@@ -98,6 +98,10 @@ module eth_ipv4_interface #(
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logic [31:0] bridge_ip_reg = DEFAULT_IP_ADDR;
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logic [15:0] bridge_udp_port = DEFAULT_UDP_PORT;
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logic bridge_en;
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logic cpu_dropped;
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logic chdr_dropped;
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logic [31:0] chdr_drop_count = 0;
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logic [31:0] cpu_drop_count = 0;
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always_comb begin : bridge_mux
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my_mac = bridge_en ? bridge_mac_reg : mac_reg;
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@@ -153,8 +157,16 @@ module eth_ipv4_interface #(
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if (bus_rst) begin
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reg_rd_resp <= 1'b0;
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reg_rd_data <= 32'd0;
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chdr_drop_count <= 32'd0;
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cpu_drop_count <= 32'd0;
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end
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else begin
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if (chdr_dropped) begin
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chdr_drop_count <= chdr_drop_count+1;
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end
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if (cpu_dropped) begin
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cpu_drop_count <= cpu_drop_count+1;
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end
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if (reg_rd_req) begin
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// Assert read response one cycle after read request
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reg_rd_resp <= 1'b1;
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@@ -185,7 +197,19 @@ module eth_ipv4_interface #(
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REG_BRIDGE_ENABLE:
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reg_rd_data <= {31'b0,bridge_en};
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// Drop counts are used to debug situations
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// Where the incoming data goes faster than
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// chdr can consume it
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REG_CHDR_DROPPED:
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begin
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reg_rd_data <= chdr_drop_count;
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chdr_drop_count <= 0; // clear when read
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end
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REG_CPU_DROPPED:
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begin
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reg_rd_data <= cpu_drop_count;
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cpu_drop_count <= 0; // clear when read
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end
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default:
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reg_rd_resp <= 1'b0;
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endcase
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@@ -197,10 +221,30 @@ module eth_ipv4_interface #(
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end
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end
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logic b_dropped_valid;
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logic e_cpu_dropped, b_cpu_dropped;
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logic e_chdr_dropped, b_chdr_dropped;
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// push over the clock domain
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// Sized to fit into 2 SRL's
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axi_fifo_2clk #(.WIDTH(2), .SIZE(4)) fifo_i (
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.reset(eth_rx.rst),
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.i_aclk(eth_rx.clk),
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.i_tdata({e_cpu_dropped, e_chdr_dropped}),
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.i_tvalid(e_cpu_dropped || e_chdr_dropped), .i_tready(/*not used*/),
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.o_aclk(bus_clk),
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.o_tdata({b_cpu_dropped, b_chdr_dropped}),
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.o_tvalid(b_dropped_valid), .o_tready(1'b1)
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);
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always_comb begin
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cpu_dropped = b_cpu_dropped && b_dropped_valid;
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chdr_dropped = b_chdr_dropped && b_dropped_valid;
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end
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eth_ipv4_chdr_adapter #(
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.PROTOVER (PROTOVER),
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.MTU (MTU),
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.CPU_FIFO_SIZE (CPU_FIFO_SIZE),
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.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE),
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.RT_TBL_SIZE (RT_TBL_SIZE),
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.NODE_INST (NODE_INST),
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.DROP_UNKNOWN_MAC(DROP_UNKNOWN_MAC),
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@@ -221,7 +265,9 @@ module eth_ipv4_interface #(
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.device_id (device_id),
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.my_mac (my_mac ),
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.my_ip (my_ip ),
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.my_udp_chdr_port(my_udp_chdr_port )
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.my_udp_chdr_port(my_udp_chdr_port),
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.chdr_dropped (e_chdr_dropped),
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.cpu_dropped (e_cpu_dropped)
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);
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