fpga: lib: Update xport_sv
- Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
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@@ -511,15 +511,29 @@ module chdr_xport_adapter #(
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data_fifo_o.tready = au.tready & pass_packet;
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end
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// Clock Crossing to the ethernet clock domain
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logic [47:0] e_my_mac;
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logic [31:0] e_my_ip;
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logic [15:0] e_my_udp_chdr_port;
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// crossing clock boundaries.
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// my_mac, my_ip, my_udp_chdr_port must be written
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// prior to traffic, or an inconsistent version will
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// exist for a clock period or 2. This would be better
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// done with a full handshake.
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synchronizer #(.WIDTH(96),.STAGES(1))
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e_info_sync (.clk(eth_rx.clk),.rst(eth_rx.rst),
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.in({my_mac,my_ip,my_udp_chdr_port}),
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.out({e_my_mac,e_my_ip,e_my_udp_chdr_port}));
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// add the UDP header back on before sending to EthTx
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eth_ipv4_add_udp #(
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.PREAMBLE_BYTES(PREAMBLE_BYTES),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES)
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) add_udp_i (
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.i(au), .o(eth_tx),
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.mac_src(my_mac),
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.ip_src(my_ip),
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.udp_src(my_udp_chdr_port),
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.mac_src(e_my_mac),
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.ip_src(e_my_ip),
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.udp_src(e_my_udp_chdr_port),
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.mac_dst(au_mac_dst),
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.ip_dst(au_ip_dst),
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.udp_dst(au_udp_dst)
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