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fpga: Update DRAM IO signatures

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This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.


Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
This commit is contained in:
Wade Fife
2020-09-03 15:26:33 -05:00
committed by Aaron Rossetto
parent d6849765ec
commit eab91d8ed0
4 changed files with 28 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e320/e320_core.v
+10 -10
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@@ -563,7 +563,7 @@ module e320_core #(
// AXI4 MM buses
wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1];
wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1];
wire [30:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1];
wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1];
wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1];
wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1];
@@ -587,7 +587,7 @@ module e320_core #(
wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1];
wire dram_axi_bready [0:NUM_DRAM_FIFOS-1];
wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1];
wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1];
wire [30:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1];
wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1];
wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1];
wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1];
@@ -611,7 +611,7 @@ module e320_core #(
.S00_AXI_ACLK (ddr3_dma_clk ),
.S00_AXI_ARESETN (~ddr3_dma_rst ),
.S00_AXI_AWID (dram_axi_awid [0]),
.S00_AXI_AWADDR (dram_axi_awaddr [0]),
.S00_AXI_AWADDR ({1'b0, dram_axi_awaddr[0]}),
.S00_AXI_AWLEN (dram_axi_awlen [0]),
.S00_AXI_AWSIZE (dram_axi_awsize [0]),
.S00_AXI_AWBURST (dram_axi_awburst [0]),
@@ -632,7 +632,7 @@ module e320_core #(
.S00_AXI_BVALID (dram_axi_bvalid [0]),
.S00_AXI_BREADY (dram_axi_bready [0]),
.S00_AXI_ARID (dram_axi_arid [0]),
.S00_AXI_ARADDR (dram_axi_araddr [0]),
.S00_AXI_ARADDR ({1'b0, dram_axi_araddr[0]}),
.S00_AXI_ARLEN (dram_axi_arlen [0]),
.S00_AXI_ARSIZE (dram_axi_arsize [0]),
.S00_AXI_ARBURST (dram_axi_arburst [0]),
@@ -653,7 +653,7 @@ module e320_core #(
.S01_AXI_ACLK (ddr3_dma_clk ),
.S01_AXI_ARESETN (~ddr3_dma_rst ),
.S01_AXI_AWID (dram_axi_awid [1]),
.S01_AXI_AWADDR (dram_axi_awaddr [1]),
.S01_AXI_AWADDR ({1'b0, dram_axi_awaddr[1]}),
.S01_AXI_AWLEN (dram_axi_awlen [1]),
.S01_AXI_AWSIZE (dram_axi_awsize [1]),
.S01_AXI_AWBURST (dram_axi_awburst [1]),
@@ -674,7 +674,7 @@ module e320_core #(
.S01_AXI_BVALID (dram_axi_bvalid [1]),
.S01_AXI_BREADY (dram_axi_bready [1]),
.S01_AXI_ARID (dram_axi_arid [1]),
.S01_AXI_ARADDR (dram_axi_araddr [1]),
.S01_AXI_ARADDR ({1'b0, dram_axi_araddr[1]}),
.S01_AXI_ARLEN (dram_axi_arlen [1]),
.S01_AXI_ARSIZE (dram_axi_arsize [1]),
.S01_AXI_ARBURST (dram_axi_arburst [1]),
@@ -695,7 +695,7 @@ module e320_core #(
.S02_AXI_ACLK (ddr3_dma_clk ),
.S02_AXI_ARESETN (~ddr3_dma_rst ),
.S02_AXI_AWID (dram_axi_awid [2]),
.S02_AXI_AWADDR (dram_axi_awaddr [2]),
.S02_AXI_AWADDR ({1'b0, dram_axi_awaddr[2]}),
.S02_AXI_AWLEN (dram_axi_awlen [2]),
.S02_AXI_AWSIZE (dram_axi_awsize [2]),
.S02_AXI_AWBURST (dram_axi_awburst [2]),
@@ -716,7 +716,7 @@ module e320_core #(
.S02_AXI_BVALID (dram_axi_bvalid [2]),
.S02_AXI_BREADY (dram_axi_bready [2]),
.S02_AXI_ARID (dram_axi_arid [2]),
.S02_AXI_ARADDR (dram_axi_araddr [2]),
.S02_AXI_ARADDR ({1'b0, dram_axi_araddr[2]}),
.S02_AXI_ARLEN (dram_axi_arlen [2]),
.S02_AXI_ARSIZE (dram_axi_arsize [2]),
.S02_AXI_ARBURST (dram_axi_arburst [2]),
@@ -737,7 +737,7 @@ module e320_core #(
.S03_AXI_ACLK (ddr3_dma_clk ),
.S03_AXI_ARESETN (~ddr3_dma_rst ),
.S03_AXI_AWID (dram_axi_awid [3]),
.S03_AXI_AWADDR (dram_axi_awaddr [3]),
.S03_AXI_AWADDR ({1'b0, dram_axi_awaddr[3]}),
.S03_AXI_AWLEN (dram_axi_awlen [3]),
.S03_AXI_AWSIZE (dram_axi_awsize [3]),
.S03_AXI_AWBURST (dram_axi_awburst [3]),
@@ -758,7 +758,7 @@ module e320_core #(
.S03_AXI_BVALID (dram_axi_bvalid [3]),
.S03_AXI_BREADY (dram_axi_bready [3]),
.S03_AXI_ARID (dram_axi_arid [3]),
.S03_AXI_ARADDR (dram_axi_araddr [3]),
.S03_AXI_ARADDR ({1'b0, dram_axi_araddr[3]}),
.S03_AXI_ARLEN (dram_axi_arlen [3]),
.S03_AXI_ARSIZE (dram_axi_arsize [3]),
.S03_AXI_ARBURST (dram_axi_arburst [3]),