From eab91d8ed0e5df6588946a5a0f11e49126ad87d0 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 2 Sep 2020 07:51:40 -0500 Subject: [PATCH] fpga: Update DRAM IO signatures This updates the IO signatures so that all devices and RFNoC blocks use the same IO signature for the DRAM. This is needed because the IO signatures must match between the RFNoC blocks and the devices. This means that some devices have extra bits in the IO signature for the address, but the extra bits will simply be ignored. Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a --- top/e320/e320_core.v | 20 ++++++++++---------- top/n3xx/n3xx_core.v | 20 ++++++++++---------- top/x300/bus_int.v | 4 ++-- top/x300/x300_core.v | 12 ++++++------ 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/top/e320/e320_core.v b/top/e320/e320_core.v index 92c2015..6af0ce3 100644 --- a/top/e320/e320_core.v +++ b/top/e320/e320_core.v @@ -563,7 +563,7 @@ module e320_core #( // AXI4 MM buses wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; - wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [30:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; @@ -587,7 +587,7 @@ module e320_core #( wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; - wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [30:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; @@ -611,7 +611,7 @@ module e320_core #( .S00_AXI_ACLK (ddr3_dma_clk ), .S00_AXI_ARESETN (~ddr3_dma_rst ), .S00_AXI_AWID (dram_axi_awid [0]), - .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWADDR ({1'b0, dram_axi_awaddr[0]}), .S00_AXI_AWLEN (dram_axi_awlen [0]), .S00_AXI_AWSIZE (dram_axi_awsize [0]), .S00_AXI_AWBURST (dram_axi_awburst [0]), @@ -632,7 +632,7 @@ module e320_core #( .S00_AXI_BVALID (dram_axi_bvalid [0]), .S00_AXI_BREADY (dram_axi_bready [0]), .S00_AXI_ARID (dram_axi_arid [0]), - .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARADDR ({1'b0, dram_axi_araddr[0]}), .S00_AXI_ARLEN (dram_axi_arlen [0]), .S00_AXI_ARSIZE (dram_axi_arsize [0]), .S00_AXI_ARBURST (dram_axi_arburst [0]), @@ -653,7 +653,7 @@ module e320_core #( .S01_AXI_ACLK (ddr3_dma_clk ), .S01_AXI_ARESETN (~ddr3_dma_rst ), .S01_AXI_AWID (dram_axi_awid [1]), - .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWADDR ({1'b0, dram_axi_awaddr[1]}), .S01_AXI_AWLEN (dram_axi_awlen [1]), .S01_AXI_AWSIZE (dram_axi_awsize [1]), .S01_AXI_AWBURST (dram_axi_awburst [1]), @@ -674,7 +674,7 @@ module e320_core #( .S01_AXI_BVALID (dram_axi_bvalid [1]), .S01_AXI_BREADY (dram_axi_bready [1]), .S01_AXI_ARID (dram_axi_arid [1]), - .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARADDR ({1'b0, dram_axi_araddr[1]}), .S01_AXI_ARLEN (dram_axi_arlen [1]), .S01_AXI_ARSIZE (dram_axi_arsize [1]), .S01_AXI_ARBURST (dram_axi_arburst [1]), @@ -695,7 +695,7 @@ module e320_core #( .S02_AXI_ACLK (ddr3_dma_clk ), .S02_AXI_ARESETN (~ddr3_dma_rst ), .S02_AXI_AWID (dram_axi_awid [2]), - .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWADDR ({1'b0, dram_axi_awaddr[2]}), .S02_AXI_AWLEN (dram_axi_awlen [2]), .S02_AXI_AWSIZE (dram_axi_awsize [2]), .S02_AXI_AWBURST (dram_axi_awburst [2]), @@ -716,7 +716,7 @@ module e320_core #( .S02_AXI_BVALID (dram_axi_bvalid [2]), .S02_AXI_BREADY (dram_axi_bready [2]), .S02_AXI_ARID (dram_axi_arid [2]), - .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARADDR ({1'b0, dram_axi_araddr[2]}), .S02_AXI_ARLEN (dram_axi_arlen [2]), .S02_AXI_ARSIZE (dram_axi_arsize [2]), .S02_AXI_ARBURST (dram_axi_arburst [2]), @@ -737,7 +737,7 @@ module e320_core #( .S03_AXI_ACLK (ddr3_dma_clk ), .S03_AXI_ARESETN (~ddr3_dma_rst ), .S03_AXI_AWID (dram_axi_awid [3]), - .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWADDR ({1'b0, dram_axi_awaddr[3]}), .S03_AXI_AWLEN (dram_axi_awlen [3]), .S03_AXI_AWSIZE (dram_axi_awsize [3]), .S03_AXI_AWBURST (dram_axi_awburst [3]), @@ -758,7 +758,7 @@ module e320_core #( .S03_AXI_BVALID (dram_axi_bvalid [3]), .S03_AXI_BREADY (dram_axi_bready [3]), .S03_AXI_ARID (dram_axi_arid [3]), - .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARADDR ({1'b0, dram_axi_araddr[3]}), .S03_AXI_ARLEN (dram_axi_arlen [3]), .S03_AXI_ARSIZE (dram_axi_arsize [3]), .S03_AXI_ARBURST (dram_axi_arburst [3]), diff --git a/top/n3xx/n3xx_core.v b/top/n3xx/n3xx_core.v index 712aef9..4062858 100644 --- a/top/n3xx/n3xx_core.v +++ b/top/n3xx/n3xx_core.v @@ -616,7 +616,7 @@ module n3xx_core #( // AXI4 MM buses wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; - wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [30:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; @@ -640,7 +640,7 @@ module n3xx_core #( wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; - wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [30:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; @@ -664,7 +664,7 @@ module n3xx_core #( .S00_AXI_ACLK (ddr3_dma_clk ), .S00_AXI_ARESETN (~ddr3_dma_rst ), .S00_AXI_AWID (dram_axi_awid [0]), - .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWADDR ({1,b0, dram_axi_awaddr[0]}), .S00_AXI_AWLEN (dram_axi_awlen [0]), .S00_AXI_AWSIZE (dram_axi_awsize [0]), .S00_AXI_AWBURST (dram_axi_awburst [0]), @@ -685,7 +685,7 @@ module n3xx_core #( .S00_AXI_BVALID (dram_axi_bvalid [0]), .S00_AXI_BREADY (dram_axi_bready [0]), .S00_AXI_ARID (dram_axi_arid [0]), - .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARADDR ({1,b0, dram_axi_araddr[0]}), .S00_AXI_ARLEN (dram_axi_arlen [0]), .S00_AXI_ARSIZE (dram_axi_arsize [0]), .S00_AXI_ARBURST (dram_axi_arburst [0]), @@ -706,7 +706,7 @@ module n3xx_core #( .S01_AXI_ACLK (ddr3_dma_clk ), .S01_AXI_ARESETN (~ddr3_dma_rst ), .S01_AXI_AWID (dram_axi_awid [1]), - .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWADDR ({1,b0, dram_axi_awaddr[1]}), .S01_AXI_AWLEN (dram_axi_awlen [1]), .S01_AXI_AWSIZE (dram_axi_awsize [1]), .S01_AXI_AWBURST (dram_axi_awburst [1]), @@ -727,7 +727,7 @@ module n3xx_core #( .S01_AXI_BVALID (dram_axi_bvalid [1]), .S01_AXI_BREADY (dram_axi_bready [1]), .S01_AXI_ARID (dram_axi_arid [1]), - .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARADDR ({1,b0, dram_axi_araddr[1]}), .S01_AXI_ARLEN (dram_axi_arlen [1]), .S01_AXI_ARSIZE (dram_axi_arsize [1]), .S01_AXI_ARBURST (dram_axi_arburst [1]), @@ -748,7 +748,7 @@ module n3xx_core #( .S02_AXI_ACLK (ddr3_dma_clk ), .S02_AXI_ARESETN (~ddr3_dma_rst ), .S02_AXI_AWID (dram_axi_awid [2]), - .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWADDR ({1,b0, dram_axi_awaddr[2]}), .S02_AXI_AWLEN (dram_axi_awlen [2]), .S02_AXI_AWSIZE (dram_axi_awsize [2]), .S02_AXI_AWBURST (dram_axi_awburst [2]), @@ -769,7 +769,7 @@ module n3xx_core #( .S02_AXI_BVALID (dram_axi_bvalid [2]), .S02_AXI_BREADY (dram_axi_bready [2]), .S02_AXI_ARID (dram_axi_arid [2]), - .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARADDR ({1,b0, dram_axi_araddr[2]}), .S02_AXI_ARLEN (dram_axi_arlen [2]), .S02_AXI_ARSIZE (dram_axi_arsize [2]), .S02_AXI_ARBURST (dram_axi_arburst [2]), @@ -790,7 +790,7 @@ module n3xx_core #( .S03_AXI_ACLK (ddr3_dma_clk ), .S03_AXI_ARESETN (~ddr3_dma_rst ), .S03_AXI_AWID (dram_axi_awid [3]), - .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWADDR ({1,b0, dram_axi_awaddr[3]}), .S03_AXI_AWLEN (dram_axi_awlen [3]), .S03_AXI_AWSIZE (dram_axi_awsize [3]), .S03_AXI_AWBURST (dram_axi_awburst [3]), @@ -811,7 +811,7 @@ module n3xx_core #( .S03_AXI_BVALID (dram_axi_bvalid [3]), .S03_AXI_BREADY (dram_axi_bready [3]), .S03_AXI_ARID (dram_axi_arid [3]), - .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARADDR ({1,b0, dram_axi_araddr[3]}), .S03_AXI_ARLEN (dram_axi_arlen [3]), .S03_AXI_ARSIZE (dram_axi_arsize [3]), .S03_AXI_ARBURST (dram_axi_arburst [3]), diff --git a/top/x300/bus_int.v b/top/x300/bus_int.v index 07446ad..4ca05c5 100644 --- a/top/x300/bus_int.v +++ b/top/x300/bus_int.v @@ -95,7 +95,7 @@ module bus_int #( input ddr3_axi_rst, // Write Address Ports output [1*2-1:0] ddr3_axi_awid, - output [32*2-1:0] ddr3_axi_awaddr, + output [30*2-1:0] ddr3_axi_awaddr, output [8*2-1:0] ddr3_axi_awlen, output [3*2-1:0] ddr3_axi_awsize, output [2*2-1:0] ddr3_axi_awburst, @@ -118,7 +118,7 @@ module bus_int #( input [1*2-1:0] ddr3_axi_bvalid, // Read Address Ports output [1*2-1:0] ddr3_axi_arid, - output [32*2-1:0] ddr3_axi_araddr, + output [30*2-1:0] ddr3_axi_araddr, output [8*2-1:0] ddr3_axi_arlen, output [3*2-1:0] ddr3_axi_arsize, output [2*2-1:0] ddr3_axi_arburst, diff --git a/top/x300/x300_core.v b/top/x300/x300_core.v index 5665c39..f4349b9 100644 --- a/top/x300/x300_core.v +++ b/top/x300/x300_core.v @@ -207,7 +207,7 @@ module x300_core #( // Memory Controller AXI4 MM buses wire s00_axi_awready, s01_axi_awready; wire [0:0] s00_axi_awid, s01_axi_awid; - wire [31:0] s00_axi_awaddr, s01_axi_awaddr; + wire [29:0] s00_axi_awaddr, s01_axi_awaddr; wire [7:0] s00_axi_awlen, s01_axi_awlen; wire [2:0] s00_axi_awsize, s01_axi_awsize; wire [1:0] s00_axi_awburst, s01_axi_awburst; @@ -227,7 +227,7 @@ module x300_core #( wire [0:0] s00_axi_buser, s01_axi_buser; wire s00_axi_arready, s01_axi_arready; wire [0:0] s00_axi_arid, s01_axi_arid; - wire [31:0] s00_axi_araddr, s01_axi_araddr; + wire [29:0] s00_axi_araddr, s01_axi_araddr; wire [7:0] s00_axi_arlen, s01_axi_arlen; wire [2:0] s00_axi_arsize, s01_axi_arsize; wire [1:0] s00_axi_arburst, s01_axi_arburst; @@ -399,7 +399,7 @@ module x300_core #( .S00_AXI_ACLK(ddr3_axi_clk_x2), // input S00_AXI_ACLK .S00_AXI_ARESETN(~ddr3_axi_rst), // input S00_AXI_ARESETN .S00_AXI_AWID(s00_axi_awid), // input [0 : 0] S00_AXI_AWID - .S00_AXI_AWADDR(s00_axi_awaddr), // input [31 : 0] S00_AXI_AWADDR + .S00_AXI_AWADDR({2'b0, s00_axi_awaddr}), // input [31 : 0] S00_AXI_AWADDR .S00_AXI_AWLEN(s00_axi_awlen), // input [7 : 0] S00_AXI_AWLEN .S00_AXI_AWSIZE(s00_axi_awsize), // input [2 : 0] S00_AXI_AWSIZE .S00_AXI_AWBURST(s00_axi_awburst), // input [1 : 0] S00_AXI_AWBURST @@ -419,7 +419,7 @@ module x300_core #( .S00_AXI_BVALID(s00_axi_bvalid), // output S00_AXI_BVALID .S00_AXI_BREADY(s00_axi_bready), // input S00_AXI_BREADY .S00_AXI_ARID(s00_axi_arid), // input [0 : 0] S00_AXI_ARID - .S00_AXI_ARADDR(s00_axi_araddr), // input [31 : 0] S00_AXI_ARADDR + .S00_AXI_ARADDR({2'b0, s00_axi_araddr}), // input [31 : 0] S00_AXI_ARADDR .S00_AXI_ARLEN(s00_axi_arlen), // input [7 : 0] S00_AXI_ARLEN .S00_AXI_ARSIZE(s00_axi_arsize), // input [2 : 0] S00_AXI_ARSIZE .S00_AXI_ARBURST(s00_axi_arburst), // input [1 : 0] S00_AXI_ARBURST @@ -439,7 +439,7 @@ module x300_core #( .S01_AXI_ACLK(ddr3_axi_clk_x2), // input S01_AXI_ACLK .S01_AXI_ARESETN(~ddr3_axi_rst), // input S00_AXI_ARESETN .S01_AXI_AWID(s01_axi_awid), // input [0 : 0] S01_AXI_AWID - .S01_AXI_AWADDR(s01_axi_awaddr), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWADDR({2'b0, s01_axi_awaddr}), // input [31 : 0] S01_AXI_AWADDR .S01_AXI_AWLEN(s01_axi_awlen), // input [7 : 0] S01_AXI_AWLEN .S01_AXI_AWSIZE(s01_axi_awsize), // input [2 : 0] S01_AXI_AWSIZE .S01_AXI_AWBURST(s01_axi_awburst), // input [1 : 0] S01_AXI_AWBURST @@ -459,7 +459,7 @@ module x300_core #( .S01_AXI_BVALID(s01_axi_bvalid), // output S01_AXI_BVALID .S01_AXI_BREADY(s01_axi_bready), // input S01_AXI_BREADY .S01_AXI_ARID(s01_axi_arid), // input [0 : 0] S01_AXI_ARID - .S01_AXI_ARADDR(s01_axi_araddr), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARADDR({2'b0, s01_axi_araddr}), // input [31 : 0] S01_AXI_ARADDR .S01_AXI_ARLEN(s01_axi_arlen), // input [7 : 0] S01_AXI_ARLEN .S01_AXI_ARSIZE(s01_axi_arsize), // input [2 : 0] S01_AXI_ARSIZE .S01_AXI_ARBURST(s01_axi_arburst), // input [1 : 0] S01_AXI_ARBURST