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@@ -1,338 +0,0 @@
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################################################################
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# This is a generated script based on design: adc_full_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source adc_full_bd_script.tcl
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# The design that will be created by this Tcl script contains the following
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# module references:
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# adc_iq_repacker
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# Please add the sources of those modules before sourcing this Tcl script.
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name adc_full_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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# Add USER_COMMENTS on $design_name
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set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axis_register_slice:1.1\
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xilinx.com:ip:xlconstant:1.1\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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##################################################################
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# CHECK Modules
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##################################################################
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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adc_iq_repacker\
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"
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set list_mods_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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lappend list_mods_missing $mod_vlnv
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}
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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] $adc_data_out
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set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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CONFIG.HAS_TKEEP {0} \
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CONFIG.HAS_TLAST {0} \
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CONFIG.HAS_TREADY {1} \
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CONFIG.HAS_TSTRB {0} \
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CONFIG.LAYERED_METADATA {undef} \
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CONFIG.TDATA_NUM_BYTES {16} \
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CONFIG.TDEST_WIDTH {0} \
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CONFIG.TID_WIDTH {0} \
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CONFIG.TUSER_WIDTH {0} \
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] $adc_i_data_in
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set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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CONFIG.HAS_TKEEP {0} \
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CONFIG.HAS_TLAST {0} \
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CONFIG.HAS_TREADY {1} \
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CONFIG.HAS_TSTRB {0} \
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CONFIG.LAYERED_METADATA {undef} \
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CONFIG.TDATA_NUM_BYTES {16} \
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CONFIG.TDEST_WIDTH {0} \
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CONFIG.TID_WIDTH {0} \
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CONFIG.TUSER_WIDTH {0} \
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] $adc_q_data_in
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# Create ports
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set enable_data_to_repacker_rclk [ create_bd_port -dir I enable_data_to_repacker_rclk ]
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set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
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set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 512000000 rfdc_clk ]
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set swap_iq_rclk [ create_bd_port -dir I swap_iq_rclk ]
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# Create instance: adc_data_to_axi, and set properties
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set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {1} \
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CONFIG.TDATA_NUM_BYTES {32} \
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] $adc_data_to_axi
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# Create instance: adc_i_data_from_axi, and set properties
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set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {0} \
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CONFIG.TDATA_NUM_BYTES {16} \
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] $adc_i_data_from_axi
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# Create instance: adc_iq_repacker, and set properties
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set block_name adc_iq_repacker
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set block_cell_name adc_iq_repacker
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if { [catch {set adc_iq_repacker [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $adc_iq_repacker eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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set_property -dict [ list \
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CONFIG.SPC {8} \
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] $adc_iq_repacker
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# Create instance: adc_q_data_from_axi, and set properties
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set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {0} \
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CONFIG.TDATA_NUM_BYTES {16} \
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] $adc_q_data_from_axi
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# Create instance: const_1, and set properties
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set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
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# Create interface connections
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connect_bd_intf_net -intf_net adc_i_data_in_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS]
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connect_bd_intf_net -intf_net adc_iq_repacker_0_data_out [get_bd_intf_pins adc_data_to_axi/S_AXIS] [get_bd_intf_pins adc_iq_repacker/data_out]
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connect_bd_intf_net -intf_net adc_q_data_from_axi1_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS]
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connect_bd_intf_net -intf_net adc_q_data_in_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS]
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# Create port connections
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connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_i_data_from_axi/m_axis_tdata] [get_bd_pins adc_iq_repacker/adc_i_in]
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connect_bd_net -net adc_i_data_from_axi_m_axis_tvalid [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] [get_bd_pins adc_iq_repacker/valid_in]
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connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_iq_repacker/adc_q_in] [get_bd_pins adc_q_data_from_axi/m_axis_tdata]
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connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout]
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connect_bd_net -net enable_data_to_repacker_rclk_1 [get_bd_ports enable_data_to_repacker_rclk] [get_bd_pins adc_iq_repacker/enable]
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connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn]
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connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_iq_repacker/clk] [get_bd_pins adc_q_data_from_axi/aclk]
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connect_bd_net -net swap_iq_rclk_1 [get_bd_ports swap_iq_rclk] [get_bd_pins adc_iq_repacker/swap_iq]
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# Create address segments
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# Restore current instance
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current_bd_instance $oldCurInst
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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Max Köhler