diff --git a/top/x400/Makefile.x4xx.inc b/top/x400/Makefile.x4xx.inc index 076cc5b..8e8c0f3 100644 --- a/top/x400/Makefile.x4xx.inc +++ b/top/x400/Makefile.x4xx.inc @@ -55,7 +55,7 @@ endif # Sources ################################################## TOP_SRCS = \ -x4xx.v \ +x4xx.sv \ x4xx_core.v \ x4xx_core_common.v \ x4xx_global_regs.v \ @@ -90,7 +90,8 @@ endif ifdef X440 TOP_SRCS += \ rf/100m/rf_core_100m.v \ -rf/full/rf_core_full.v \ +rf/full/rf_core_full.sv \ +rf/common/adc_iq_repacker.v \ rf/x440/x440_rf_reset_controller.vhd \ dboards/fbx/db_gpio_interface.v \ dboards/fbx/ctrlport_to_i2c_sync_ctrl.v \ diff --git a/top/x400/ip/Makefile.inc b/top/x400/ip/Makefile.inc index eefc18a..a89a306 100644 --- a/top/x400/ip/Makefile.inc +++ b/top/x400/ip/Makefile.inc @@ -34,7 +34,6 @@ include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc endif ifdef X440 -include $(IP_DIR)/adc_full_bd/Makefile.inc include $(IP_DIR)/adc_100m_bd/Makefile.inc include $(IP_DIR)/dac_100m_bd/Makefile.inc include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc @@ -76,7 +75,6 @@ endif ifdef X440 BD_SRCS += \ -$(IP_ADC_FULL_BD_SRCS) \ $(IP_ADC_FULL_HDL_SRCS) \ $(IP_ADC_100M_BD_SRCS) \ $(IP_ADC_100M_HDL_SRCS) \ @@ -128,7 +126,6 @@ endif ifdef X440 BD_OUTPUTS += \ -$(BD_ADC_FULL_BD_OUTS) \ $(BD_ADC_100M_BD_OUTS) \ $(BD_DAC_100M_BD_OUTS) endif diff --git a/top/x400/ip/adc_full_bd/Makefile.inc b/top/x400/ip/adc_full_bd/Makefile.inc deleted file mode 100644 index 49adb24..0000000 --- a/top/x400/ip/adc_full_bd/Makefile.inc +++ /dev/null @@ -1,38 +0,0 @@ -# -# Copyright 2022 Ettus Research, a National Instruments Brand -# -# SPDX-License-Identifier: LGPL-3.0-or-later -# - -include $(TOOLS_DIR)/make/viv_ip_builder.mak - -IP_ADC_FULL_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_full_bd/, \ -adc_full_bd.tcl \ -) - -IP_ADC_FULL_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \ -common/adc_iq_repacker.v \ -) - -IP_ADC_FULL_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ -adc_full_bd.tcl \ -) - -IP_ADC_FULL_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ -adc_full_bd/adc_full_bd.bd \ -) - -BD_ADC_FULL_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ -adc_full_bd.bd.out \ -adc_full_bd/adc_full_bd_ooc.xdc \ -adc_full_bd/synth/adc_full_bd.v \ -) - -EMPTY_IP_SRCS = - -.INTERMEDIATE: IP_ADC_FULL_BD_TRGT -$(IP_ADC_FULL_BD_SRCS) $(BD_ADC_FULL_BD_OUTS) $(IP_ADC_FULL_BDTCL_SRCS): IP_ADC_FULL_BD_TRGT - @: - -IP_ADC_FULL_BD_TRGT: $(IP_ADC_FULL_ORIG_SRCS) $(IP_ADC_FULL_HDL_SRCS) - $(call BUILD_VIVADO_BDTCL,adc_full_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_FULL_HDL_SRCS),) diff --git a/top/x400/ip/adc_full_bd/adc_full_bd.tcl b/top/x400/ip/adc_full_bd/adc_full_bd.tcl deleted file mode 100644 index bcd8c25..0000000 --- a/top/x400/ip/adc_full_bd/adc_full_bd.tcl +++ /dev/null @@ -1,338 +0,0 @@ - -################################################################ -# This is a generated script based on design: adc_full_bd -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2021.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source adc_full_bd_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# adc_iq_repacker - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-2-e -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name adc_full_bd - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - - # Add USER_COMMENTS on $design_name - set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axis_register_slice:1.1\ -xilinx.com:ip:xlconstant:1.1\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -adc_iq_repacker\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {512000000} \ - ] $adc_data_out - - set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {512000000} \ - CONFIG.HAS_TKEEP {0} \ - CONFIG.HAS_TLAST {0} \ - CONFIG.HAS_TREADY {1} \ - CONFIG.HAS_TSTRB {0} \ - CONFIG.LAYERED_METADATA {undef} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TDEST_WIDTH {0} \ - CONFIG.TID_WIDTH {0} \ - CONFIG.TUSER_WIDTH {0} \ - ] $adc_i_data_in - - set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {512000000} \ - CONFIG.HAS_TKEEP {0} \ - CONFIG.HAS_TLAST {0} \ - CONFIG.HAS_TREADY {1} \ - CONFIG.HAS_TSTRB {0} \ - CONFIG.LAYERED_METADATA {undef} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TDEST_WIDTH {0} \ - CONFIG.TID_WIDTH {0} \ - CONFIG.TUSER_WIDTH {0} \ - ] $adc_q_data_in - - - # Create ports - set enable_data_to_repacker_rclk [ create_bd_port -dir I enable_data_to_repacker_rclk ] - set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] - set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 512000000 rfdc_clk ] - set swap_iq_rclk [ create_bd_port -dir I swap_iq_rclk ] - - # Create instance: adc_data_to_axi, and set properties - set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {1} \ - CONFIG.TDATA_NUM_BYTES {32} \ - ] $adc_data_to_axi - - # Create instance: adc_i_data_from_axi, and set properties - set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {0} \ - CONFIG.TDATA_NUM_BYTES {16} \ - ] $adc_i_data_from_axi - - # Create instance: adc_iq_repacker, and set properties - set block_name adc_iq_repacker - set block_cell_name adc_iq_repacker - if { [catch {set adc_iq_repacker [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $adc_iq_repacker eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - set_property -dict [ list \ - CONFIG.SPC {8} \ - ] $adc_iq_repacker - - # Create instance: adc_q_data_from_axi, and set properties - set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {0} \ - CONFIG.TDATA_NUM_BYTES {16} \ - ] $adc_q_data_from_axi - - # Create instance: const_1, and set properties - set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] - - # Create interface connections - connect_bd_intf_net -intf_net adc_i_data_in_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS] - connect_bd_intf_net -intf_net adc_iq_repacker_0_data_out [get_bd_intf_pins adc_data_to_axi/S_AXIS] [get_bd_intf_pins adc_iq_repacker/data_out] - connect_bd_intf_net -intf_net adc_q_data_from_axi1_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS] - connect_bd_intf_net -intf_net adc_q_data_in_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS] - - # Create port connections - connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_i_data_from_axi/m_axis_tdata] [get_bd_pins adc_iq_repacker/adc_i_in] - connect_bd_net -net adc_i_data_from_axi_m_axis_tvalid [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] [get_bd_pins adc_iq_repacker/valid_in] - connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_iq_repacker/adc_q_in] [get_bd_pins adc_q_data_from_axi/m_axis_tdata] - connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout] - connect_bd_net -net enable_data_to_repacker_rclk_1 [get_bd_ports enable_data_to_repacker_rclk] [get_bd_pins adc_iq_repacker/enable] - connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn] - connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_iq_repacker/clk] [get_bd_pins adc_q_data_from_axi/aclk] - connect_bd_net -net swap_iq_rclk_1 [get_bd_ports swap_iq_rclk] [get_bd_pins adc_iq_repacker/swap_iq] - - # Create address segments - - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/top/x400/ip/adc_full_bd/hdl_sources.tcl b/top/x400/ip/adc_full_bd/hdl_sources.tcl deleted file mode 100644 index f8a9765..0000000 --- a/top/x400/ip/adc_full_bd/hdl_sources.tcl +++ /dev/null @@ -1,6 +0,0 @@ -set script_loc [file normalize [info script]] -set script_dir [file dirname $script_loc] - -# Vivado's block diagram default library for files not belonging to any special -# library is called xil_defaultlib -read_verilog -library xil_defaultlib $script_dir/../../rf/common/adc_iq_repacker.v diff --git a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh index c653951..0c05ea9 100644 --- a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh @@ -89,13 +89,13 @@ // Enumerated type RF_CORE_FULL_VERSION localparam RF_CORE_FULL_VERSION_SIZE = 7; - localparam RF_CORE_FULL_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MINOR + localparam RF_CORE_FULL_CURRENT_VERSION_MINOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MINOR localparam RF_CORE_FULL_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_BUILD localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD localparam RF_CORE_FULL_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MAJOR localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME = 'h22062900; // RF_CORE_FULL_VERSION:RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME + localparam RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME = 'h24080915; // RF_CORE_FULL_VERSION:RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME //=============================================================================== // Register Group VERSIONING_REGS diff --git a/top/x400/rf/full/Makefile.srcs b/top/x400/rf/full/Makefile.srcs index db56ac3..6d71885 100644 --- a/top/x400/rf/full/Makefile.srcs +++ b/top/x400/rf/full/Makefile.srcs @@ -5,5 +5,5 @@ # RF_FULL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/full/, \ -rf_core_full.v \ +rf_core_full.sv \ )) diff --git a/top/x400/rf/full/rf_core_full.sv b/top/x400/rf/full/rf_core_full.sv new file mode 100644 index 0000000..4a16b5e --- /dev/null +++ b/top/x400/rf/full/rf_core_full.sv @@ -0,0 +1,256 @@ +// +// Copyright 2024 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rf_core_full +// +// Description: +// +// Top-level wrapper for the ADC/DAC processing logic. One of these wrappers +// exists for every supported Data Rate. An instance of this core should +// exist per dboard. +// +// Data/RF Specs: +// DBs: 1 +// RX/DB: via parameter NUM_ADC_CHANNELS +// TX/DB: via parameter NUM_DAC_CHANNELS +// Data Rate: rfdc_clk @ RADIO_SPC +// + +`default_nettype none + +module rf_core_full # ( + parameter NUM_ADC_CHANNELS = 4, + parameter NUM_DAC_CHANNELS = 4, + parameter RADIO_SPC = 8 +) ( + + //--------------------------------------------------------------------------- + // Clocking + //--------------------------------------------------------------------------- + + // Main Clock Inputs + input wire rfdc_clk, + + // AXI4-Lite Config Clock + // This clock is used to synchronize status bits for the RFDC + // registers in the AXI-S clock domain. + input wire s_axi_config_clk, + + //--------------------------------------------------------------------------- + // RFDC Data Interfaces + //--------------------------------------------------------------------------- + // All ports here are in the rfdc_clk domain. + + // ADC + input wire [16*RADIO_SPC-1:0] adc_data_in_i_tdata [0:NUM_ADC_CHANNELS-1], + output wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tready, + input wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tvalid, + input wire [16*RADIO_SPC-1:0] adc_data_in_q_tdata [0:NUM_ADC_CHANNELS-1], + output wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tready, + input wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tvalid, + + // DAC + output wire [32*RADIO_SPC-1:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1], + input wire [NUM_ADC_CHANNELS-1:0] dac_data_out_tready, + output wire [NUM_ADC_CHANNELS-1:0] dac_data_out_tvalid, + + //--------------------------------------------------------------------------- + // User Data Interfaces + //--------------------------------------------------------------------------- + // All ports here are in the rfdc_clk domain on the X440. + + // ADC + // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire [32*RADIO_SPC-1:0] adc_data_out_tdata [0:NUM_ADC_CHANNELS-1], + output wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tvalid, + + // DAC + input wire [32*RADIO_SPC-1:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1], + output wire [NUM_ADC_CHANNELS-1:0] dac_data_in_tready, + input wire [NUM_ADC_CHANNELS-1:0] dac_data_in_tvalid, + + //--------------------------------------------------------------------------- + // Miscellaneous + //--------------------------------------------------------------------------- + + // Invert I/Q control signals from RFDC to DSP chain. + input wire [NUM_ADC_CHANNELS-1:0] invert_adc_iq_rclk, + input wire [NUM_ADC_CHANNELS-1:0] invert_dac_iq_rclk, + + // Control/status vectors from/to RFDC. + // Notice these are all in the s_axi_config_clk domain. + output wire [ 9:0] dsp_info_sclk, + output wire [15:0] axi_status_sclk, + output wire [15:0] rfdc_info_sclk, + + // Resets. + input wire adc_enable_data_rclk, + input wire adc_rfdc_axi_resetn_rclk, + + // Version (Constant) + output wire [95:0] version_info +); + + `include "../../regmap/x440/rfdc_regs_regmap_utils.vh" + `include "../../regmap/x440/versioning_regs_regmap_utils.vh" + `include "../../regmap/versioning_utils.vh" + + //--------------------------------------------------------------------------- + // Resets, Debug and Misc. + //--------------------------------------------------------------------------- + wire [15:0] axi_status; + + // Group all these status bits together. They don't toggle frequently so data + // coherency is not an issue here. + // Using constants for DB0 since the bits are the 16 LSBs in a 32-bit vector. + // DB1 simply uses the 16 MSBs when wiring the status vector. + // There is no tready going to the ADC (one has to be always ready for ADC + // data), but it is still a component of the axi_status vector as a generic + // AXI stream status. Report 1'b1 to the status vector consistent with being + // always ready + assign axi_status[USER_ADC_TREADY_MSB :USER_ADC_TREADY ] = '1; + assign axi_status[USER_ADC_TVALID_MSB :USER_ADC_TVALID ] = adc_data_out_tvalid; + assign axi_status[RFDC_ADC_I_TVALID_MSB:RFDC_ADC_I_TVALID] = adc_data_in_i_tvalid; + assign axi_status[RFDC_ADC_Q_TVALID_MSB:RFDC_ADC_Q_TVALID] = adc_data_in_q_tvalid; + assign axi_status[RFDC_ADC_I_TREADY_MSB:RFDC_ADC_I_TREADY] = adc_data_in_i_tready; + assign axi_status[RFDC_ADC_Q_TREADY_MSB:RFDC_ADC_Q_TREADY] = adc_data_in_q_tready; + assign axi_status[RFDC_DAC_TVALID_MSB :RFDC_DAC_TVALID ] = dac_data_out_tvalid; + assign axi_status[RFDC_DAC_TREADY_MSB :RFDC_DAC_TREADY ] = dac_data_out_tready; + + synchronizer #( + .WIDTH (16), + .STAGES (2), + .INITIAL_VAL (0), + .FALSE_PATH_TO_IN (1) + ) synchronizer_axis_status ( + .clk (s_axi_config_clk), + .rst (1'b0), + .in (axi_status), + .out (axi_status_sclk) + ); + + // Drive the DSP info vector with information on this specific DSP chain. + assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS; + assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS; + + // This RF core always consumes 8 SPC from the gearbox per I/Q signal + assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8); + assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16); + // This RF core module contains no additional resampling + assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd1; + + //--------------------------------------------------------------------------- + // ADC Post-Processing + //--------------------------------------------------------------------------- + + // ADC Data from the RFDC arrives here with separate I and Q + // streams. It gets combined to a single stream. + for (genvar adc_num = 0; adc_num < (NUM_ADC_CHANNELS); adc_num++) + begin : adc_gen + //signals between packer and register + wire [32*RADIO_SPC-1:0] packer_to_reg_tdata; + wire packer_to_reg_tvalid; + + adc_iq_repacker #( + .SPC (RADIO_SPC), + .SAMPLE_WIDTH (16) + ) iq_repacker ( + .clk (rfdc_clk), + .adc_q_in (adc_data_in_q_tdata[adc_num]), + .adc_i_in (adc_data_in_i_tdata[adc_num]), + .valid_in (adc_data_in_i_tvalid[adc_num]), // taking I stream valid bit only to reduce complexity + .enable (adc_enable_data_rclk), + .swap_iq (invert_adc_iq_rclk[adc_num]), + .data_out_tdata (packer_to_reg_tdata), + .data_out_tvalid (packer_to_reg_tvalid) + ); + + // Create instances of axi_fifo_flop2 module for each ADC channel + axi_fifo_flop2 #( + .WIDTH (32*RADIO_SPC) + ) adc_reg ( + .clk (rfdc_clk), + .reset ('0), + .clear ('0), + .i_tdata (packer_to_reg_tdata), + .i_tvalid (packer_to_reg_tvalid), + .i_tready (), + .o_tdata (adc_data_out_tdata[adc_num]), + .o_tvalid (adc_data_out_tvalid[adc_num]), + .o_tready ('1), + .space (), + .occupied () + ); + end + + //--------------------------------------------------------------------------- + // DAC Pre-Processing + //--------------------------------------------------------------------------- + + for (genvar dac_num = 0; dac_num < NUM_DAC_CHANNELS; dac_num++) + begin : dac_swap_gen + + for (genvar sample_num = 0; sample_num < RADIO_SPC; sample_num++) + begin : sample_swap_gen + + assign dac_data_out_tdata[dac_num][32*sample_num+00 +: 16] = invert_dac_iq_rclk[dac_num] ? + dac_data_in_tdata[dac_num][32*sample_num+16 +: 16] : + dac_data_in_tdata[dac_num][32*sample_num+00 +: 16]; + assign dac_data_out_tdata[dac_num][32*sample_num+16 +: 16] = invert_dac_iq_rclk[dac_num] ? + dac_data_in_tdata[dac_num][32*sample_num+00 +: 16] : + dac_data_in_tdata[dac_num][32*sample_num+16 +: 16]; + end + end + + assign dac_data_out_tvalid = dac_data_in_tvalid; + assign dac_data_in_tready = dac_data_out_tready; + + //--------------------------------------------------------------------------- + // Version + //--------------------------------------------------------------------------- + + // Version metadata, constants come from auto-generated + // versioning_regs_regmap_utils.vh + assign version_info = build_component_versions( + RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME, + build_version( + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR, + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR, + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD + ), + build_version( + RF_CORE_FULL_CURRENT_VERSION_MAJOR, + RF_CORE_FULL_CURRENT_VERSION_MINOR, + RF_CORE_FULL_CURRENT_VERSION_BUILD + ) + ); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// +// Full BW RF core.{BR/} +// For guidance on when to update these revision numbers, +// please refer to the register map documentation accordingly: +//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION +//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION +//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/rf/full/rf_core_full.v b/top/x400/rf/full/rf_core_full.v deleted file mode 100644 index b13afe4..0000000 --- a/top/x400/rf/full/rf_core_full.v +++ /dev/null @@ -1,436 +0,0 @@ -// -// Copyright 2023 Ettus Research, a National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: rf_core_full -// -// Description: -// -// Top-level wrapper for the ADC/DAC processing logic. One of these wrappers -// exists for every supported Data Rate. An instance of this core should -// exist per dboard. -// -// Data/RF Specs: -// DBs: 1 -// RX/DB: 4 -// TX/DB: 4 -// Data Rate: rfdc_clk @ 8 SPC -// -// Input Clocks, all aligned to one another and coming from same MMCM -// rfdc_clk: 15.625 to 250 MHz -// rfdc_clk_2x: 2 * rfdc_clk -// - -`default_nettype none - -module rf_core_full # ( - parameter NUM_ADC_CHANNELS = 4, - parameter NUM_DAC_CHANNELS = 4 -) ( - - //--------------------------------------------------------------------------- - // Clocking - //--------------------------------------------------------------------------- - - // Main Clock Inputs - input wire rfdc_clk, - input wire rfdc_clk_2x, - - // AXI4-Lite Config Clock - // This clock is used to synchronize status bits for the RFDC - // registers in the AXI-S clock domain. - input wire s_axi_config_clk, - - - //--------------------------------------------------------------------------- - // RFDC Data Interfaces - //--------------------------------------------------------------------------- - // All ports here are in the rfdc_clk domain. - - // ADC - input wire [127:0] adc_data_in_i_tdata_0, - output wire adc_data_in_i_tready_0, - input wire adc_data_in_i_tvalid_0, - input wire [127:0] adc_data_in_q_tdata_0, - output wire adc_data_in_q_tready_0, - input wire adc_data_in_q_tvalid_0, - input wire [127:0] adc_data_in_i_tdata_1, - output wire adc_data_in_i_tready_1, - input wire adc_data_in_i_tvalid_1, - input wire [127:0] adc_data_in_q_tdata_1, - output wire adc_data_in_q_tready_1, - input wire adc_data_in_q_tvalid_1, - input wire [127:0] adc_data_in_i_tdata_2, - output wire adc_data_in_i_tready_2, - input wire adc_data_in_i_tvalid_2, - input wire [127:0] adc_data_in_q_tdata_2, - output wire adc_data_in_q_tready_2, - input wire adc_data_in_q_tvalid_2, - input wire [127:0] adc_data_in_i_tdata_3, - output wire adc_data_in_i_tready_3, - input wire adc_data_in_i_tvalid_3, - input wire [127:0] adc_data_in_q_tdata_3, - output wire adc_data_in_q_tready_3, - input wire adc_data_in_q_tvalid_3, - - - // DAC - output wire [255:0] dac_data_out_tdata_0, - input wire dac_data_out_tready_0, - output wire dac_data_out_tvalid_0, - output wire [255:0] dac_data_out_tdata_1, - input wire dac_data_out_tready_1, - output wire dac_data_out_tvalid_1, - output wire [255:0] dac_data_out_tdata_2, - input wire dac_data_out_tready_2, - output wire dac_data_out_tvalid_2, - output wire [255:0] dac_data_out_tdata_3, - input wire dac_data_out_tready_3, - output wire dac_data_out_tvalid_3, - - - //--------------------------------------------------------------------------- - // User Data Interfaces - //--------------------------------------------------------------------------- - // All ports here are in the rfdc_clk domain on the X440. - - // ADC - output wire [255:0] adc_data_out_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire adc_data_out_tvalid_0, - output wire [255:0] adc_data_out_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire adc_data_out_tvalid_1, - output wire [255:0] adc_data_out_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire adc_data_out_tvalid_2, - output wire [255:0] adc_data_out_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire adc_data_out_tvalid_3, - - // DAC - input wire [255:0] dac_data_in_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire dac_data_in_tready_0, - input wire dac_data_in_tvalid_0, - input wire [255:0] dac_data_in_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire dac_data_in_tready_1, - input wire dac_data_in_tvalid_1, - input wire [255:0] dac_data_in_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire dac_data_in_tready_2, - input wire dac_data_in_tvalid_2, - input wire [255:0] dac_data_in_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs - output wire dac_data_in_tready_3, - input wire dac_data_in_tvalid_3, - - //--------------------------------------------------------------------------- - // Miscellaneous - //--------------------------------------------------------------------------- - - // Invert I/Q control signals from RFDC to DSP chain. - input wire [3:0] invert_adc_iq_rclk2, - input wire [3:0] invert_dac_iq_rclk2, - - // Control/status vectors from/to RFDC. - // Notice these are all in the s_axi_config_clk domain. - output wire [9:0] dsp_info_sclk, - output wire [15:0] axi_status_sclk, - output wire [15:0] rfdc_info_sclk, - - // Resets. - input wire adc_enable_data_rclk, - input wire adc_rfdc_axi_resetn_rclk, - - // Version (Constant) - output wire [95:0] version_info -); - - `include "../../regmap/x440/rfdc_regs_regmap_utils.vh" - `include "../../regmap/x440/versioning_regs_regmap_utils.vh" - `include "../../regmap/versioning_utils.vh" - - // ADC data interface from RFDC. - wire [127:0] adc_data_in_i_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I) - wire [127:0] adc_data_in_q_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (Q) - wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tready; - wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tready; - wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tvalid; - wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tvalid; - // DAC data interface to RFDC. - wire [255:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) - wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tready; - wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tvalid; - - // ADC data interface to user. - wire [255:0] adc_data_out_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I + Q) - wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tready; - wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tvalid; - // DAC data interface from user. - wire [255:0] dac_data_in_tdata_preswap [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) - wire [255:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) - wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tready; - wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tvalid; - - wire [15:0] axi_status; - - - //--------------------------------------------------------------------------- - // Resets, Debug and Misc. - //--------------------------------------------------------------------------- - - // Group all these status bits together. They don't toggle frequently so data - // coherency is not an issue here. - // Using constants for DB0 since the bits are the 16 LSBs in a 32-bit vector. - // DB1 simply uses the 16 MSBs when wiring the status vector. - assign axi_status[USER_ADC_TREADY_MSB :USER_ADC_TREADY ] = adc_data_out_tready[1:0]; - assign axi_status[USER_ADC_TVALID_MSB :USER_ADC_TVALID ] = adc_data_out_tvalid[1:0]; - assign axi_status[RFDC_ADC_I_TVALID_MSB:RFDC_ADC_I_TVALID] = adc_data_in_i_tvalid[1:0]; - assign axi_status[RFDC_ADC_Q_TVALID_MSB:RFDC_ADC_Q_TVALID] = adc_data_in_q_tvalid[1:0]; - assign axi_status[RFDC_ADC_I_TREADY_MSB:RFDC_ADC_I_TREADY] = adc_data_in_i_tready[1:0]; - assign axi_status[RFDC_ADC_Q_TREADY_MSB:RFDC_ADC_Q_TREADY] = adc_data_in_q_tready[1:0]; - assign axi_status[RFDC_DAC_TVALID_MSB :RFDC_DAC_TVALID ] = dac_data_out_tvalid[1:0]; - assign axi_status[RFDC_DAC_TREADY_MSB :RFDC_DAC_TREADY ] = dac_data_out_tready[1:0]; - - synchronizer #( - .WIDTH (16), - .STAGES (2), - .INITIAL_VAL (0), - .FALSE_PATH_TO_IN (1) - ) synchronizer_axis_status ( - .clk (s_axi_config_clk), - .rst (1'b0), - .in (axi_status), - .out (axi_status_sclk) - ); - - // Drive the DSP info vector with information on this specific DSP chain. - assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS; - assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS; - - // This RF core always consumes 8 SPC from the gearbox per I/Q signal - assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8); - assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16); - // This RF core module contains no additional resampling - assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd1; - - //--------------------------------------------------------------------------- - // ADC Post-Processing - //--------------------------------------------------------------------------- - - // Data comes from the RFDC as 8 SPC, separate streams for each channel and - // I/Q. - assign adc_data_in_i_tdata[0] = adc_data_in_i_tdata_0; - assign adc_data_in_q_tdata[0] = adc_data_in_q_tdata_0; - assign adc_data_in_i_tdata[1] = adc_data_in_i_tdata_1; - assign adc_data_in_q_tdata[1] = adc_data_in_q_tdata_1; - assign adc_data_in_i_tdata[2] = adc_data_in_i_tdata_2; - assign adc_data_in_q_tdata[2] = adc_data_in_q_tdata_2; - assign adc_data_in_i_tdata[3] = adc_data_in_i_tdata_3; - assign adc_data_in_q_tdata[3] = adc_data_in_q_tdata_3; - - assign adc_data_in_i_tready_0 = adc_data_in_i_tready[0]; - assign adc_data_in_i_tvalid[0] = adc_data_in_i_tvalid_0; - assign adc_data_in_q_tready_0 = adc_data_in_q_tready[0]; - assign adc_data_in_q_tvalid[0] = adc_data_in_q_tvalid_0; - assign adc_data_in_i_tready_1 = adc_data_in_i_tready[1]; - assign adc_data_in_i_tvalid[1] = adc_data_in_i_tvalid_1; - assign adc_data_in_q_tready_1 = adc_data_in_q_tready[1]; - assign adc_data_in_q_tvalid[1] = adc_data_in_q_tvalid_1; - assign adc_data_in_i_tready_2 = adc_data_in_i_tready[2]; - assign adc_data_in_i_tvalid[2] = adc_data_in_i_tvalid_2; - assign adc_data_in_q_tready_2 = adc_data_in_q_tready[2]; - assign adc_data_in_q_tvalid[2] = adc_data_in_q_tvalid_2; - assign adc_data_in_i_tready_3 = adc_data_in_i_tready[3]; - assign adc_data_in_i_tvalid[3] = adc_data_in_i_tvalid_3; - assign adc_data_in_q_tready_3 = adc_data_in_q_tready[3]; - assign adc_data_in_q_tvalid[3] = adc_data_in_q_tvalid_3; - - // ADC Data from the RFDC arrives here as 8 SPC with separate I and Q - // streams. It leaves the adc_full_rate_bd as 8 SPC with I and Q packed into - // a single 256 bit word. - genvar adc_num; - generate - for (adc_num=0; adc_num < (NUM_ADC_CHANNELS); adc_num = adc_num + 1) - begin : adc_gen - adc_full_bd adc_full_bd_gen ( - .enable_data_to_repacker_rclk (adc_enable_data_rclk), - .rfdc_adc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk), - .rfdc_clk (rfdc_clk), - .swap_iq_rclk (invert_adc_iq_rclk2 [adc_num]), - .adc_q_data_in_tvalid (adc_data_in_q_tvalid[adc_num]), - .adc_q_data_in_tready (adc_data_in_q_tready[adc_num]), - .adc_q_data_in_tdata (adc_data_in_q_tdata [adc_num]), - .adc_i_data_in_tvalid (adc_data_in_i_tvalid[adc_num]), - .adc_i_data_in_tready (adc_data_in_i_tready[adc_num]), - .adc_i_data_in_tdata (adc_data_in_i_tdata [adc_num]), - .adc_data_out_tvalid (adc_data_out_tvalid [adc_num]), - .adc_data_out_tdata (adc_data_out_tdata [adc_num]) - ); - end - endgenerate - - // Data is released to the user as 8 SPC, separate streams for each channel. - assign adc_data_out_tdata_0 = adc_data_out_tdata[0]; - assign adc_data_out_tdata_1 = adc_data_out_tdata[1]; - assign adc_data_out_tdata_2 = adc_data_out_tdata[2]; - assign adc_data_out_tdata_3 = adc_data_out_tdata[3]; - - // There is no tready going to the ADC (one has to be always ready for ADC - // data), but it is still a component of the axi_status vector as a generic - // AXI stream status. Report 1'b1 to the status vector consistent with being - // always ready - assign adc_data_out_tready[0] = 1'b1; - assign adc_data_out_tvalid_0 = adc_data_out_tvalid[0]; - assign adc_data_out_tready[1] = 1'b1; - assign adc_data_out_tvalid_1 = adc_data_out_tvalid[1]; - assign adc_data_out_tready[2] = 1'b1; - assign adc_data_out_tvalid_2 = adc_data_out_tvalid[2]; - assign adc_data_out_tready[3] = 1'b1; - assign adc_data_out_tvalid_3 = adc_data_out_tvalid[3]; - - //--------------------------------------------------------------------------- - // DAC Pre-Processing - //--------------------------------------------------------------------------- - - // Data comes from the user as 8 SPC, separate streams for each channel. - assign dac_data_in_tdata_preswap[0] = dac_data_in_tdata_0; - assign dac_data_in_tdata_preswap[1] = dac_data_in_tdata_1; - assign dac_data_in_tdata_preswap[2] = dac_data_in_tdata_2; - assign dac_data_in_tdata_preswap[3] = dac_data_in_tdata_3; - - assign dac_data_in_tready_0 = dac_data_in_tready[0]; - assign dac_data_in_tvalid[0] = dac_data_in_tvalid_0; - assign dac_data_in_tready_1 = dac_data_in_tready[1]; - assign dac_data_in_tvalid[1] = dac_data_in_tvalid_1; - assign dac_data_in_tready_2 = dac_data_in_tready[2]; - assign dac_data_in_tvalid[2] = dac_data_in_tvalid_2; - assign dac_data_in_tready_3 = dac_data_in_tready[3]; - assign dac_data_in_tvalid[3] = dac_data_in_tvalid_3; - - genvar dac_num; - generate - for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1) - begin : dac_swap_gen - //IO and Q0 swap - assign dac_data_in_tdata[dac_num][15:00] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][31:16]) : (dac_data_in_tdata_preswap[dac_num][15:0]); - assign dac_data_in_tdata[dac_num][31:16] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][15:00]) : (dac_data_in_tdata_preswap[dac_num][31:16]); - - //I1 and Q1 swap - assign dac_data_in_tdata[dac_num][47:32] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][63:48]) : (dac_data_in_tdata_preswap[dac_num][47:32]); - assign dac_data_in_tdata[dac_num][63:48] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][47:32]) : (dac_data_in_tdata_preswap[dac_num][63:48]); - - //I2 and Q2 swap - assign dac_data_in_tdata[dac_num][79:64] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][95:80]) : (dac_data_in_tdata_preswap[dac_num][79:64]); - assign dac_data_in_tdata[dac_num][95:80] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][79:64]) : (dac_data_in_tdata_preswap[dac_num][95:80]); - - //I3 and Q3 swap - assign dac_data_in_tdata[dac_num][111:96] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][127:112]) : (dac_data_in_tdata_preswap[dac_num][111:96]); - assign dac_data_in_tdata[dac_num][127:112] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][111:96]) : (dac_data_in_tdata_preswap[dac_num][127:112]); - - //I4 and Q4 swap - assign dac_data_in_tdata[dac_num][143:128] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][159:144]) : (dac_data_in_tdata_preswap[dac_num][143:128]); - assign dac_data_in_tdata[dac_num][159:144] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][143:128]) : (dac_data_in_tdata_preswap[dac_num][159:144]); - - //I5 and Q5 swap - assign dac_data_in_tdata[dac_num][175:160] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][191:176]) : (dac_data_in_tdata_preswap[dac_num][175:160]); - assign dac_data_in_tdata[dac_num][191:176] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][175:160]) : (dac_data_in_tdata_preswap[dac_num][191:176]); - - //I6 and Q6 swap - assign dac_data_in_tdata[dac_num][207:192] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][223:208]) : (dac_data_in_tdata_preswap[dac_num][207:192]); - assign dac_data_in_tdata[dac_num][223:208] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][207:192]) : (dac_data_in_tdata_preswap[dac_num][223:208]); - - //I7 and Q7 swap - assign dac_data_in_tdata[dac_num][239:224] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][255:240]) : (dac_data_in_tdata_preswap[dac_num][239:224]); - assign dac_data_in_tdata[dac_num][255:240] = invert_dac_iq_rclk2[dac_num] ? - (dac_data_in_tdata_preswap[dac_num][239:224]) : (dac_data_in_tdata_preswap[dac_num][255:240]); - - end - endgenerate - - // These streams are then connected to data out, no need for a bd, and form a single - // stream per channel, 8 SPC, packed: MSB [Sample7Q, Sample7I, ... , - // Sample0Q, Sample0I] LSB. - generate - for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1) - begin : dac_gen - assign dac_data_out_tdata[dac_num] = dac_data_in_tdata[dac_num]; - assign dac_data_out_tvalid[dac_num] = dac_data_in_tvalid[dac_num]; - assign dac_data_in_tready[dac_num] = dac_data_out_tready[dac_num]; - end - endgenerate - - // Data is released to the RFDC as 8 SPC, separate streams per channel (I/Q - // together). - assign dac_data_out_tdata_0 = dac_data_out_tdata[0]; - assign dac_data_out_tdata_1 = dac_data_out_tdata[1]; - assign dac_data_out_tdata_2 = dac_data_out_tdata[2]; - assign dac_data_out_tdata_3 = dac_data_out_tdata[3]; - - assign dac_data_out_tready[0] = dac_data_out_tready_0; - assign dac_data_out_tvalid_0 = dac_data_out_tvalid[0]; - assign dac_data_out_tready[1] = dac_data_out_tready_1; - assign dac_data_out_tvalid_1 = dac_data_out_tvalid[1]; - assign dac_data_out_tready[2] = dac_data_out_tready_2; - assign dac_data_out_tvalid_2 = dac_data_out_tvalid[2]; - assign dac_data_out_tready[3] = dac_data_out_tready_3; - assign dac_data_out_tvalid_3 = dac_data_out_tvalid[3]; - - - //--------------------------------------------------------------------------- - // Version - //--------------------------------------------------------------------------- - - // Version metadata, constants come from auto-generated - // versioning_regs_regmap_utils.vh - assign version_info = build_component_versions( - RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME, - build_version( - RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR, - RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR, - RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD - ), - build_version( - RF_CORE_FULL_CURRENT_VERSION_MAJOR, - RF_CORE_FULL_CURRENT_VERSION_MINOR, - RF_CORE_FULL_CURRENT_VERSION_BUILD - ) - ); - -endmodule - -`default_nettype wire - -//XmlParse xml_on -// -// -// -// -// Full BW RF core.{BR/} -// For guidance on when to update these revision numbers, -// please refer to the register map documentation accordingly: -//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION -//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION -//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED -// -// -// -// -// -// -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/x4xx.v b/top/x400/x4xx.sv similarity index 96% rename from top/x400/x4xx.v rename to top/x400/x4xx.sv index ce99028..c73b9e9 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.sv @@ -2131,73 +2131,29 @@ module x4xx ( .version_info (rf_core_version[db_i]) ); end else if (RF_CORE == "FULL") begin : gen_rf_core_full - localparam ADC_AXIS_W = 128; - localparam DAC_AXIS_W = 256; rf_core_full #( .NUM_ADC_CHANNELS(NUM_CH_PER_DB), - .NUM_DAC_CHANNELS(NUM_CH_PER_DB) + .NUM_DAC_CHANNELS(NUM_CH_PER_DB), + .RADIO_SPC(RADIO_SPC) ) rf_core_full_i ( .rfdc_clk (rfdc_clk[db_i]), - .rfdc_clk_2x (rfdc_clk_2x[db_i]), .s_axi_config_clk (clk40), - .adc_data_in_i_tdata_0 (adc_tile_dout_i_tdata[NUM_CH_PER_DB*db_i+0][ADC_AXIS_W-1:0]), - .adc_data_in_i_tready_0 (adc_tile_dout_i_tready[NUM_CH_PER_DB*db_i+0]), - .adc_data_in_i_tvalid_0 (adc_tile_dout_i_tvalid[NUM_CH_PER_DB*db_i+0]), - .adc_data_in_q_tdata_0 (adc_tile_dout_q_tdata[NUM_CH_PER_DB*db_i+0][ADC_AXIS_W-1:0]), - .adc_data_in_q_tready_0 (adc_tile_dout_q_tready[NUM_CH_PER_DB*db_i+0]), - .adc_data_in_q_tvalid_0 (adc_tile_dout_q_tvalid[NUM_CH_PER_DB*db_i+0]), - .adc_data_in_i_tdata_1 (adc_tile_dout_i_tdata[NUM_CH_PER_DB*db_i+1][ADC_AXIS_W-1:0]), - .adc_data_in_i_tready_1 (adc_tile_dout_i_tready[NUM_CH_PER_DB*db_i+1]), - .adc_data_in_i_tvalid_1 (adc_tile_dout_i_tvalid[NUM_CH_PER_DB*db_i+1]), - .adc_data_in_q_tdata_1 (adc_tile_dout_q_tdata[NUM_CH_PER_DB*db_i+1][ADC_AXIS_W-1:0]), - .adc_data_in_q_tready_1 (adc_tile_dout_q_tready[NUM_CH_PER_DB*db_i+1]), - .adc_data_in_q_tvalid_1 (adc_tile_dout_q_tvalid[NUM_CH_PER_DB*db_i+1]), - .adc_data_in_i_tdata_2 (adc_tile_dout_i_tdata[NUM_CH_PER_DB*db_i+2][ADC_AXIS_W-1:0]), - .adc_data_in_i_tready_2 (adc_tile_dout_i_tready[NUM_CH_PER_DB*db_i+2]), - .adc_data_in_i_tvalid_2 (adc_tile_dout_i_tvalid[NUM_CH_PER_DB*db_i+2]), - .adc_data_in_q_tdata_2 (adc_tile_dout_q_tdata[NUM_CH_PER_DB*db_i+2][ADC_AXIS_W-1:0]), - .adc_data_in_q_tready_2 (adc_tile_dout_q_tready[NUM_CH_PER_DB*db_i+2]), - .adc_data_in_q_tvalid_2 (adc_tile_dout_q_tvalid[NUM_CH_PER_DB*db_i+2]), - .adc_data_in_i_tdata_3 (adc_tile_dout_i_tdata[NUM_CH_PER_DB*db_i+3][ADC_AXIS_W-1:0]), - .adc_data_in_i_tready_3 (adc_tile_dout_i_tready[NUM_CH_PER_DB*db_i+3]), - .adc_data_in_i_tvalid_3 (adc_tile_dout_i_tvalid[NUM_CH_PER_DB*db_i+3]), - .adc_data_in_q_tdata_3 (adc_tile_dout_q_tdata[NUM_CH_PER_DB*db_i+3][ADC_AXIS_W-1:0]), - .adc_data_in_q_tready_3 (adc_tile_dout_q_tready[NUM_CH_PER_DB*db_i+3]), - .adc_data_in_q_tvalid_3 (adc_tile_dout_q_tvalid[NUM_CH_PER_DB*db_i+3]), - .dac_data_out_tdata_0 (dac_tile_din_tdata[NUM_CH_PER_DB*db_i+0][DAC_AXIS_W-1:0]), - .dac_data_out_tready_0 (dac_tile_din_tready[NUM_CH_PER_DB*db_i+0]), - .dac_data_out_tvalid_0 (dac_tile_din_tvalid[NUM_CH_PER_DB*db_i+0]), - .dac_data_out_tdata_1 (dac_tile_din_tdata[NUM_CH_PER_DB*db_i+1][DAC_AXIS_W-1:0]), - .dac_data_out_tready_1 (dac_tile_din_tready[NUM_CH_PER_DB*db_i+1]), - .dac_data_out_tvalid_1 (dac_tile_din_tvalid[NUM_CH_PER_DB*db_i+1]), - .dac_data_out_tdata_2 (dac_tile_din_tdata[NUM_CH_PER_DB*db_i+2][DAC_AXIS_W-1:0]), - .dac_data_out_tready_2 (dac_tile_din_tready[NUM_CH_PER_DB*db_i+2]), - .dac_data_out_tvalid_2 (dac_tile_din_tvalid[NUM_CH_PER_DB*db_i+2]), - .dac_data_out_tdata_3 (dac_tile_din_tdata[NUM_CH_PER_DB*db_i+3][DAC_AXIS_W-1:0]), - .dac_data_out_tready_3 (dac_tile_din_tready[NUM_CH_PER_DB*db_i+3]), - .dac_data_out_tvalid_3 (dac_tile_din_tvalid[NUM_CH_PER_DB*db_i+3]), - .adc_data_out_tdata_0 (adc_data_out_tdata[NUM_CH_PER_DB*db_i+0]), - .adc_data_out_tvalid_0 (adc_data_out_tvalid[NUM_CH_PER_DB*db_i+0]), - .adc_data_out_tdata_1 (adc_data_out_tdata[NUM_CH_PER_DB*db_i+1]), - .adc_data_out_tvalid_1 (adc_data_out_tvalid[NUM_CH_PER_DB*db_i+1]), - .adc_data_out_tdata_2 (adc_data_out_tdata[NUM_CH_PER_DB*db_i+2]), - .adc_data_out_tvalid_2 (adc_data_out_tvalid[NUM_CH_PER_DB*db_i+2]), - .adc_data_out_tdata_3 (adc_data_out_tdata[NUM_CH_PER_DB*db_i+3]), - .adc_data_out_tvalid_3 (adc_data_out_tvalid[NUM_CH_PER_DB*db_i+3]), - .dac_data_in_tdata_0 (dac_data_in_tdata[NUM_CH_PER_DB*db_i+0]), - .dac_data_in_tready_0 (dac_data_in_tready[NUM_CH_PER_DB*db_i+0]), - .dac_data_in_tvalid_0 (dac_data_in_tvalid[NUM_CH_PER_DB*db_i+0]), - .dac_data_in_tdata_1 (dac_data_in_tdata[NUM_CH_PER_DB*db_i+1]), - .dac_data_in_tready_1 (dac_data_in_tready[NUM_CH_PER_DB*db_i+1]), - .dac_data_in_tvalid_1 (dac_data_in_tvalid[NUM_CH_PER_DB*db_i+1]), - .dac_data_in_tdata_2 (dac_data_in_tdata[NUM_CH_PER_DB*db_i+2]), - .dac_data_in_tready_2 (dac_data_in_tready[NUM_CH_PER_DB*db_i+2]), - .dac_data_in_tvalid_2 (dac_data_in_tvalid[NUM_CH_PER_DB*db_i+2]), - .dac_data_in_tdata_3 (dac_data_in_tdata[NUM_CH_PER_DB*db_i+3]), - .dac_data_in_tready_3 (dac_data_in_tready[NUM_CH_PER_DB*db_i+3]), - .dac_data_in_tvalid_3 (dac_data_in_tvalid[NUM_CH_PER_DB*db_i+3]), - .invert_adc_iq_rclk2 (swapped_invert_adc_iq_rclk2[4*db_i +: 4]), - .invert_dac_iq_rclk2 (swapped_invert_dac_iq_rclk2[4*db_i +: 4]), + .adc_data_in_i_tdata (adc_tile_dout_i_tdata [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_in_i_tready (adc_tile_dout_i_tready [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_in_i_tvalid (adc_tile_dout_i_tvalid [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_in_q_tdata (adc_tile_dout_q_tdata [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_in_q_tready (adc_tile_dout_q_tready [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_in_q_tvalid (adc_tile_dout_q_tvalid [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_out_tdata (dac_tile_din_tdata [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_out_tready (dac_tile_din_tready [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_out_tvalid (dac_tile_din_tvalid [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_out_tdata (adc_data_out_tdata [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .adc_data_out_tvalid (adc_data_out_tvalid [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_in_tdata (dac_data_in_tdata [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_in_tready (dac_data_in_tready [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .dac_data_in_tvalid (dac_data_in_tvalid [NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .invert_adc_iq_rclk (swapped_invert_adc_iq_rclk2[NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), + .invert_dac_iq_rclk (swapped_invert_dac_iq_rclk2[NUM_CH_PER_DB*db_i +: NUM_CH_PER_DB]), .dsp_info_sclk (rf_dsp_info_clk40[10*db_i+:10]), .rfdc_info_sclk (rf_rfdc_info_clk40[16*db_i+:16]), .axi_status_sclk (rf_axi_status_clk40[16*db_i +: 16]), @@ -2881,7 +2837,7 @@ module x4xx ( .qsfp1_tx_n (qsfp1_tx_n), .qsfp1_rx_p (qsfp1_rx_p), .qsfp1_rx_n (qsfp1_rx_n), - .qsfp1_recovered_clk (rx_rec_clk_out1), + .qsfp1_recovered_clk (rx_rec_clk_out1), .qsfp1_device_id (device_id), .qsfp1_rx_irq (eth1_rx_irq), .qsfp1_tx_irq (eth1_tx_irq),