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fpga: x400: Add CE clock

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Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
This commit is contained in:
Wade Fife
2023-10-18 22:23:55 -05:00
parent 2612487d43
commit ea0b8f4012
15 changed files with 453 additions and 384 deletions
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top/x400/x4xx.v
+56
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@@ -482,6 +482,61 @@ module x4xx (
);
`endif
// Compute Engine Clock
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// __ce_clk__266.66667______0.000______50.0_______94.562_____97.786
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________200____________0.010
wire ce_gen_clkfbout;
wire ce_gen_clkout0;
wire ce_clk;
PLLE4_ADV #(
.COMPENSATION ("AUTO" ),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1 ),
.CLKFBOUT_MULT (4 ),
.CLKFBOUT_PHASE (0.000 ),
.CLKOUT0_DIVIDE (3 ),
.CLKOUT0_PHASE (0.000 ),
.CLKOUT0_DUTY_CYCLE(0.500 ),
.CLKIN_PERIOD (5.000 )
) ce_clk_gen_i (
.CLKFBOUT (ce_gen_clkfbout),
.CLKOUT0 (ce_gen_clkout0 ),
.CLKOUT0B ( ),
.CLKOUT1 ( ),
.CLKOUT1B ( ),
.CLKFBIN (ce_gen_clkfbout),
.CLKIN (clk200 ),
.DADDR (7'h0 ),
.DCLK (1'b0 ),
.DEN (1'b0 ),
.DI (16'h0 ),
.DO ( ),
.DRDY ( ),
.DWE (1'b0 ),
.CLKOUTPHYEN(1'b0 ),
.CLKOUTPHY ( ),
.LOCKED ( ),
.PWRDWN (1'b0 ),
.RST (areset )
);
BUFG bufg_ce_i (
.O(ce_clk ),
.I(ce_gen_clkout0)
);
//---------------------------------------------------------------------------
// PPS Handling
//---------------------------------------------------------------------------
@@ -2973,6 +3028,7 @@ module x4xx (
.rfnoc_chdr_rst (bus_clk_rst),
.rfnoc_ctrl_clk (clk40),
.rfnoc_ctrl_rst (clk40_rst),
.ce_clk (ce_clk),
.dram0_sys_clk_p (DRAM0_REFCLK_P),
.dram0_sys_clk_n (DRAM0_REFCLK_N),
.dram0_ck_t (DRAM0_CLK_P),