fpga: x400: Add CE clock

Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
2023-10-18 22:23:55 -05:00
parent 2612487d43
commit ea0b8f4012
15 changed files with 453 additions and 384 deletions
@@ -52,6 +52,7 @@ create_clock -name clk166 -period  6.000 \
 create_clock -name clk200 -period  5.000 \
  [get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[3]}]

+create_generated_clock -name ce_clk [get_pins {ce_clk_gen_i/CLKOUT0}]

 ###############################################################################
 # Sync to DB synthesizer sync CPLD input