fpga: x4xx: add option for incremental Vivado build
So far only the implementation after opt_run is affected by the changes. Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
This commit is contained in:
Max Köhler
@@ -16,6 +16,7 @@ SIMULATION = 0
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# - BUILD_DIR must be defined globally
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# - DESIGN_SRCS must be defined and should contain all source files
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# - VERILOG_DEFS must be defined and should contain all PP defines
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# - INCR_BUILD can be defined and runs parts of the Vivado flow in incremental mode
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# -------------------------------------------------------------------
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BUILD_VIVADO_DESIGN = \
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@ \
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@@ -26,6 +27,7 @@ BUILD_VIVADO_DESIGN = \
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export VIV_MODE=$(VIVADO_MODE); \
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export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
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export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
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export VIV_INCR_BUILD=$(INCR_BUILD); \
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cd $(BUILD_DIR); \
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$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
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@@ -13,18 +13,18 @@ namespace eval ::vivado_strategies {
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check_strategy \
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print_strategy
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variable g_viv_version [version -short]
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# Required environment variables
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variable g_output_dir $::env(VIV_OUTPUT_DIR)
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}
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# ---------------------------------------------------
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# Return a preset strategy with the most commonly used options
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# ---------------------------------------------------
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proc ::vivado_strategies::get_impl_preset {preset} {
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variable g_viv_version
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set strategy [dict create]
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switch -nocase $preset {
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"Default" {
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dict set strategy "implementation.incremental" 0
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dict set strategy "opt_design.is_enabled" 1
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dict set strategy "opt_design.directive" "Default"
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dict set strategy "post_opt_power_opt_design.is_enabled" 0
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@@ -38,6 +38,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
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dict set strategy "post_route_phys_opt_design.directive" "Default"
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}
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"Performance_Explore" {
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dict set strategy "implementation.incremental" 0
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dict set strategy "opt_design.is_enabled" 1
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dict set strategy "opt_design.directive" "Explore"
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dict set strategy "post_opt_power_opt_design.is_enabled" 0
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@@ -51,6 +52,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
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dict set strategy "post_route_phys_opt_design.directive" "Explore"
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}
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"Performance_ExplorePostRoutePhysOpt" {
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dict set strategy "implementation.incremental" 0
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dict set strategy "opt_design.is_enabled" 1
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dict set strategy "opt_design.directive" "Explore"
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dict set strategy "post_opt_power_opt_design.is_enabled" 0
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@@ -71,7 +73,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
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# Execute the specified implementation strategy
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# ---------------------------------------------------
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proc ::vivado_strategies::implement_design {strategy} {
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variable g_viv_version
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variable g_output_dir
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# Check strategy for validity and print
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vivado_strategies::check_strategy $strategy
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@@ -85,6 +87,17 @@ proc ::vivado_strategies::implement_design {strategy} {
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opt_design -directive $opt_dir
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}
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# Reading former post-route checkpoint for incremental implementation.
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# This will set all consecutive operations into incremental operation mode in case there
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# is a post_route checkpoint from a previous run.
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if [dict get $strategy "implementation.incremental"] {
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set impl_checkpoint $g_output_dir/post_route.dcp
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if {[file exists $impl_checkpoint]} {
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# read incremental checkpoint
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read_checkpoint -incremental $impl_checkpoint
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}
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}
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# Optimize dynamic power using intelligent clock gating after optimization
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if [dict get $strategy "post_opt_power_opt_design.is_enabled"] {
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power_opt_design
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@@ -133,10 +146,9 @@ proc ::vivado_strategies::implement_design {strategy} {
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# Sanity-check the specified strategy
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# ---------------------------------------------------
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proc ::vivado_strategies::check_strategy {strategy} {
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variable g_viv_version
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set strategy_options [dict keys $strategy]
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set required_options {\
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implementation.incremental \
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opt_design.is_enabled \
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opt_design.directive \
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post_opt_power_opt_design.is_enabled \
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@@ -165,8 +177,6 @@ proc ::vivado_strategies::check_strategy {strategy} {
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# Print strategy parameters to the console
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# ---------------------------------------------------
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proc ::vivado_strategies::print_strategy {strategy} {
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variable g_viv_version
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foreach opt [dict keys $strategy] {
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set val [dict get $strategy $opt]
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puts " * $opt = $val"
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+5
-1
@@ -82,6 +82,9 @@ DEFS += $(OPTIONS)
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Default value for incremental Vivado build is disabled.
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INCR_BUILD ?= 0
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# Defaults specific to the various targets:
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
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@@ -107,7 +110,7 @@ endif
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TOP ?= x4xx
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# vivado_build($1=Device, $2=Definitions, $3=Defaults)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 INCR_BUILD=$(INCR_BUILD)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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# vivado_build($1=Device, $2=Option)
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@@ -325,6 +328,7 @@ help: ##Show this help message.
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##
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##Supported Options
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##-----------------
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##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs
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##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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@@ -11,13 +11,13 @@ source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
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vivado_utils::initialize_project
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# STEP#2: Run synthesis
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vivado_utils::synthesize_design
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vivado_utils::generate_post_synth_reports
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# STEP#3: Run implementation strategy
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set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
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# Enable incremental build
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dict set strategy "implementation.incremental" $::env(VIV_INCR_BUILD)
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# Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
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set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
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# Vivado has been underestimating routing delays.
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